dissertation_thesis/ariths-gen
1
0
Fork 0
mirror of https://github.com/ehw-fit/ariths-gen.git synced 2025-04-10 17:22:11 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity
32 Commits 6 Branches 3 Tags
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Vojta Mrazek 915f494331 workflow
2021-03-23 13:41:56 +01:00
.github/workflows
workflow
2021-03-23 13:41:56 +01:00
Prezentace
Also uploading previously presented presentation.
2021-02-09 21:03:34 +01:00
Tests
Implemented unsigned dadda multiplier circuit. Updated generation of export formats. TBD: Proper testing, modification of dadda with cla adder, write shell script for Verilog and Blif equivalence check.
2021-03-15 01:08:47 +01:00
.gitignore
Implemented generation to flat Verilog format and improved some other minor bits of code.
2021-02-16 10:41:29 +01:00
arithmetic_circuits_generator.py
Pushing circuits generation example.
2021-03-22 10:49:54 +01:00
arithmetic_circuits.py
Did some code refactoring concerning one bit circuits generation. Added multiple one/multi bit circuits. TBD: Generate and test different circuits, implement divider circuits, comment code, add verification/optimization of Verilog/BLIF files using yosys tool.
2021-03-22 00:22:01 +01:00
logic_gates.py
Implemented unsigned dadda multiplier circuit. Updated generation of export formats. TBD: Proper testing, modification of dadda with cla adder, write shell script for Verilog and Blif equivalence check.
2021-03-15 01:08:47 +01:00
multi_bit_circuits.py
Pushing circuits generation example.
2021-03-22 10:49:54 +01:00
one_bit_circuits.py
Did some code refactoring concerning one bit circuits generation. Added multiple one/multi bit circuits. TBD: Generate and test different circuits, implement divider circuits, comment code, add verification/optimization of Verilog/BLIF files using yosys tool.
2021-03-22 00:22:01 +01:00
README.md
Initial commit
2020-11-21 17:33:07 +01:00
wire_components.py
Implemented unsigned dadda multiplier circuit. Updated generation of export formats. TBD: Proper testing, modification of dadda with cla adder, write shell script for Verilog and Blif equivalence check.
2021-03-15 01:08:47 +01:00

README.md

bc_arithmetic_circuits_generator

FIT BUT bachelor's degree project

Description
Generator of arithmetic circuits (multipliers, adders) and approximate circuits
approximate-computingblifrtlverilog
Readme 74 MiB
Languages
C 59.1%
Verilog 38.4%
Coq 2.2%
Python 0.3%