dissertation_thesis/ariths-gen
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Updating some minor changes.

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This commit is contained in:
honzastor 2021-03-28 18:17:10 +02:00
parent 6f02fa94d1
commit acd3d51a62
3 changed files with 19 additions and 33 deletions
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2
arithmetic_circuits.py
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@ -377,7 +377,7 @@ class arithmetic_circuit():
return "(" + ",".join([str(self.get_circuit_wire_index(o)) for o in self.out.bus[::-1]]) + ")"
# Generating flat CGP chromosome representation of circuit
def get_cgp_code(self, file_object):
def get_cgp_code_flat(self, file_object):
file_object.write(self.get_parameters_cgp())
file_object.write(self.get_triplet_cgp())
file_object.write(self.get_output_cgp())

23
arithmetic_circuits_generator.py
View File

@ -12,7 +12,14 @@ if __name__ == "__main__":
a = bus(N=N, prefix="a")
b = bus(N=1, prefix="b")
name = f"test"
circuit = unsigned_ripple_carry_adder(a,b, prefix=name)
circuit.get_c_code_flat(open(f'{name}.c', 'w'))
#circuit = signed_dadda_multiplier(a, b, prefix=name, unsigned_adder_class_name=unsigned_ripple_carry_adder)
#circuit.get_v_code_hier(open(f"{name}.v", "w"))
#circuit.get_blif_code_hier(open(f"{name}.blif", "w"))
"""
name = f"h_u_wallace_cla{N}"
circuit = unsigned_wallace_multiplier(a, b, prefix=name, unsigned_adder_class_name=unsigned_carry_lookahead_adder)
circuit.get_v_code_hier(open(f"{name}.v", "w"))
@ -29,7 +36,7 @@ if __name__ == "__main__":
name = f"h_s_dadda_cla{N}"
circuit = signed_dadda_multiplier(a, b, prefix=name, unsigned_adder_class_name=unsigned_carry_lookahead_adder)
circuit.get_v_code_hier(open(f"{name}.v", "w"))
"""
"""
# RCA
@ -108,7 +115,6 @@ if __name__ == "__main__":
circuit.get_v_code_hier(open(f"{name}.v", "w"))
name = f"h_u_dadda_pg_rca{N}"
circuit = unsigned_dadda_multiplier(a, b, prefix=name, unsigned_adder_class_name=unsigned_pg_ripple_carry_adder)
circuit.get_v_code_hier(open(f"{name}.v", "w"))
@ -117,7 +123,6 @@ if __name__ == "__main__":
circuit = signed_dadda_multiplier(a, b, prefix=name, unsigned_adder_class_name=unsigned_pg_ripple_carry_adder)
circuit.get_v_code_hier(open(f"{name}.v", "w"))
name = f"h_u_dadda_cla{N}"
circuit = unsigned_dadda_multiplier(a, b, prefix=name, unsigned_adder_class_name=unsigned_carry_lookahead_adder)
circuit.get_v_code_hier(open(f"{name}.v", "w"))
@ -127,18 +132,6 @@ if __name__ == "__main__":
circuit.get_v_code_hier(open(f"{name}.v", "w"))
"""
w1 = wire(name="a")
w2 = wire(name="b")
w3 = wire(name="cin")

27
multi_bit_circuits.py
View File

@ -26,20 +26,15 @@ class unsigned_ripple_carry_adder(arithmetic_circuit):
for input_index in range(self.N):
# First adder is a half adder
if input_index == 0:
obj_ha = half_adder(self.a.get_wire(input_index), self.b.get_wire(input_index), prefix=self.prefix+"_ha")
self.add_component(obj_ha)
self.out.connect(input_index, obj_ha.get_sum_wire())
if input_index == (self.N-1):
self.out.connect(self.N, obj_ha.get_carry_wire())
obj_adder = half_adder(self.a.get_wire(input_index), self.b.get_wire(input_index), prefix=self.prefix+"_ha")
# Rest adders are full adders
else:
obj_fa = full_adder(self.a.get_wire(input_index), self.b.get_wire(input_index), self.get_previous_component().get_carry_wire(), prefix=self.prefix+"_fa"+str(input_index))
self.add_component(obj_fa)
self.out.connect(input_index, obj_fa.get_sum_wire())
if input_index == (self.N-1):
self.out.connect(self.N, obj_fa.get_carry_wire())
obj_adder = full_adder(self.a.get_wire(input_index), self.b.get_wire(input_index), self.get_previous_component().get_carry_wire(), prefix=self.prefix+"_fa"+str(input_index))
self.add_component(obj_adder)
self.out.connect(input_index, obj_adder.get_sum_wire())
if input_index == (self.N-1):
self.out.connect(self.N, obj_adder.get_carry_wire())
class signed_ripple_carry_adder(unsigned_ripple_carry_adder, arithmetic_circuit):
@ -77,13 +72,11 @@ class unsigned_pg_ripple_carry_adder(arithmetic_circuit):
constant_wire_0 = constant_wire_value_0(self.a.get_wire(), self.b.get_wire())
self.add_component(constant_wire_0)
obj_fa_cla = full_adder_pg(self.a.get_wire(input_index), self.b.get_wire(input_index), constant_wire_0.out.get_wire(), prefix=self.prefix+"_fa"+str(input_index))
self.add_component(obj_fa_cla)
self.out.connect(input_index, obj_fa_cla.get_sum_wire())
else:
obj_fa_cla = full_adder_pg(self.a.get_wire(input_index), self.b.get_wire(input_index), self.get_previous_component().out, prefix=self.prefix+"_fa"+str(input_index))
self.add_component(obj_fa_cla)
self.out.connect(input_index, obj_fa_cla.get_sum_wire())
self.add_component(obj_fa_cla)
self.out.connect(input_index, obj_fa_cla.get_sum_wire())
obj_and = and_gate(self.get_previous_component().c, self.get_previous_component().get_propagate_wire(), prefix=self.prefix+"_and"+str(input_index))
obj_or = or_gate(obj_and.out, self.get_previous_component().get_generate_wire(), prefix=self.prefix+"_or"+str(input_index))