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Author SHA1 Message Date
honzastor
c9ddb834f7 Generated flat Verilog adder and gate circuits. Minor update to C code logic gates. 2021-02-16 10:38:36 +01:00
honzastor
193d504120 Generated hierarchical C code circuits and updated testing script correspondigly. 2021-02-12 01:45:26 +01:00
honzastor
397d3bc658 Added generation of hierarchical C code for implemented circuits. 2021-02-12 01:43:44 +01:00
honzastor
94af6fec34 Also uploading previously presented presentation. 2021-02-09 21:03:34 +01:00
honzastor
f1142b51d9 Implemented basic tests for generated flat C code circuits. 2021-02-09 21:02:50 +01:00
honzastor
de127e8c46 Added signed rca circuit. 2021-02-09 20:53:53 +01:00
honzastor
ee73047199 Edited example circuits generation. 2021-01-18 19:34:05 +01:00
honzastor
4f8de30911 Implementation organized into multiple scripts. Added basic generation example call. Adjusting code to PEP8 standard (except long lines).) 2021-01-18 19:29:31 +01:00
root
b7c896872e Made small bugfixes in C code generation. 2020-12-28 15:11:22 +01:00
root
2a4609234c Merge branch 'develop' of https://github.com/honzastor/bc_arithmetic_circuits_generator into develop 2020-12-28 01:31:05 +01:00
root
6fe6d2c3d6 Changed implementaion of generating C code from circuits. 2020-12-28 01:30:52 +01:00
Jan Klhůfek
b3e0e9f48f
Delete generator_test.py 2020-12-28 01:29:53 +01:00
root
e15fa5aed5 Changed code generation to C language. 2020-12-28 00:41:01 +01:00
root
67a1dfa148 Updated C code generation wire names. 2020-12-13 14:53:20 +01:00
root
01f473e727 Added c code generation for logic gates, one bit adders, rca. 2020-12-11 22:57:32 +01:00
root
f18f6159f5 Started work on exporting adders into .c files. Needs optimization. 2020-12-11 03:48:04 +01:00
root
7fba0f0aea Added ripple carry adder and started work on C code generation. 2020-12-10 22:37:10 +01:00
root
99d23be531 Implemented logic for wire, bus, logic gates, and 1-bit adders. 2020-12-10 03:52:00 +01:00
Jan Klhůfek
77f1e794c1
Initial commit 2020-11-21 17:33:07 +01:00