honzastor
ce36ebf77b
Fixed hierarchical BLIF generation for popcount_compare.
2024-04-17 18:47:41 +02:00
honzastor
f4b816fc09
Fix for workflow tests
2024-04-14 16:36:45 +02:00
honzastor
6003886eb7
Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later
2024-04-14 16:29:10 +02:00
honzastor
97e79b93da
Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue.
2024-04-13 17:04:03 +02:00
honzastor
739d5fafce
Added documentation to Recursive multiplier and hopefully fixed some issues with popcount output generation.
2024-04-08 21:37:34 +02:00
Vojta Mrazek
4e331f0525
popcount with variable sizes
2024-04-08 13:48:25 +02:00
Jan Klhůfek
211dd49fb5
Merge pull request #25 from ehw-fit/popcount
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Popcount
2024-04-05 12:40:39 +02:00
Vojta Mrazek
0180735dd5
workflow to node.js 20
2024-04-05 11:27:41 +02:00
Vojta Mrazek
84a41ad93c
test unique #21
2024-04-05 11:25:37 +02:00
Vojta Mrazek
77724ad115
workflow update
2024-04-05 11:21:42 +02:00
Vojta Mrazek
128b1309a1
popcount fixes
2024-04-05 09:24:03 +02:00
Vojta Mrazek
8468c5b8fd
Merge pull request #24 from ehw-fit/devel
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Devel merge to popcount
2024-04-05 09:19:26 +02:00
Vojta Mrazek
1219d7bec5
Merge branch 'popcount' into devel
2024-04-05 09:19:04 +02:00
Vojta Mrazek
2cf7b921ea
Popcount implementation
2024-04-05 08:46:02 +02:00
honzastor
da733cf44e
Added instantiation of wires and buses from inputs. Hopefully fixed now.
2024-03-28 00:06:53 +01:00
honzastor
cd3441ff00
Removed error tests from overall testing.
2024-03-27 23:44:34 +01:00
honzastor
21a6437eb8
Additional type hint fix.
2024-03-27 23:19:40 +01:00
honzastor
73101eb055
Type hint bugfix for pytest.
2024-03-27 23:10:06 +01:00
honzastor
d013a40145
Added unsigned recursive multiplier and made some bugfixes.
2024-03-27 23:00:13 +01:00
Vojta Mrazek
2e1694ccd5
popcount and compare
2024-03-22 14:19:23 +01:00
honzastor
7e1112cf81
Added individual input bus attributes to CGP Circuit objects to allow for the generation of output CGP representation.
2024-03-06 00:42:12 +01:00
Vojta Mrazek
f853a46703
CGP circuit checks
2023-04-13 12:09:07 +02:00
Vojta Mrazek
a44b0638a1
Implementation of QuAd approximate adder
2023-03-28 13:55:58 +02:00
Vojta Mrazek
a4741db191
connection checks (asserts)
2023-03-28 11:16:55 +02:00
Vojta Mrazek
44e0a920d1
MUX support of constant values
2023-03-24 12:11:42 +01:00
Vojta Mrazek
49bbc86a0f
accepts a wire as a bus
2023-03-23 13:39:32 +01:00
Vojta Mrazek
363e402e16
workflow: docs
2023-03-23 08:00:37 +01:00
Vojta Mrazek
d16ab17512
Merge pull request #20 from ehw-fit/main
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Main to devel
2023-03-23 07:53:54 +01:00
honzastor
7cf34d04f3
Bugfix in conditional statement.
2023-03-22 18:14:55 +01:00
honzastor
b88c502343
Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).
2023-03-22 17:57:51 +01:00
Jan Klhůfek
cf747918bf
Merge pull request #19 from ehw-fit/devel
2023-02-24 14:12:40 +01:00
Vojta Mrazek
bb4c6d35a7
page deploy
2023-02-24 13:41:36 +01:00
Jan Klhůfek
6bbe9eb253
Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers. ( #18 )
2023-02-24 13:34:35 +01:00
honzastor
d52e67bb25
Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.
2023-02-24 11:13:46 +01:00
Jan Klhůfek
2d7e157453
Merge pull request #17 from ehw-fit/devel
2023-02-22 18:59:31 +01:00
Vojta Mrazek
283f9c79f5
Merge branch 'main' into devel
2023-02-22 12:12:20 +01:00
Vojta Mrazek
d022195e48
Workflow ( #16 )
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* workflow
* workflow
* workflow
2023-02-22 12:08:21 +01:00
Vojta Mrazek
da4347148c
workflow python 3.6 version
2023-02-22 10:00:32 +01:00
Vojta Mrazek
60c4d3d24e
workflow python 3.6 version
2023-02-22 09:55:19 +01:00
Vojta Mrazek
6dd69c5aaa
Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel
2023-02-22 09:52:34 +01:00
Vojta Mrazek
43b3d65463
workflow modification, bus indexing
2023-02-22 09:52:06 +01:00
Vojta Mrazek
71a1d45045
string description ( #15 )
2023-02-22 09:45:14 +01:00
Vojta Mrazek
35240abc63
fix bug in python interpretation
2023-02-22 09:43:24 +01:00
Vojta Mrazek
a4a48dea57
Create codeql-analysis.yml ( #14 )
2022-05-26 10:08:35 +02:00
Jan Klhůfek
56c86c13ca
New multipliers ( #13 )
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* #10 CGP Circuits as inputs (#11 )
* CGP Circuits as inputs
* #10 support of signed output in general circuit
* input as output works
* output connected to input (c)
* automated verilog testing
* output rename
* Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup.
* Typos fix and code cleanup.
* Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.
* Updated automated testing scripts.
* Small bugfix in python code generation (I initially thought this line is useless).
* Updated generated circuits folder.
Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
2022-04-17 16:00:00 +02:00
Honza
f17e87738e
Updated generated circuits folder.
2022-04-17 13:41:32 +02:00
Honza
b1ddc8c387
Small bugfix in python code generation (I initially thought this line is useless).
2022-04-17 13:25:10 +02:00
Honza
5d2f4e07e7
Updated automated testing scripts.
2022-04-17 13:06:46 +02:00
Honza
c0dcf42499
Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.
2022-04-17 13:04:17 +02:00
Jan Klhůfek
5475e3aa75
Added ArXiv badge and paper reference ( #12 )
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* Update README.md
* Update README.md
* Update README.md
* Update README.md
2022-03-25 07:19:38 +01:00
