dissertation_thesis/ariths-gen-mig
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
202 Commits 1 Branch 1 Tag
Commit Graph

202 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
honzastor
cd3441ff00 Removed error tests from overall testing. 2024-03-27 23:44:34 +01:00
honzastor
21a6437eb8 Additional type hint fix. 2024-03-27 23:19:40 +01:00
honzastor
73101eb055 Type hint bugfix for pytest. 2024-03-27 23:10:06 +01:00
honzastor
d013a40145 Added unsigned recursive multiplier and made some bugfixes. 2024-03-27 23:00:13 +01:00
Vojta Mrazek
2e1694ccd5 popcount and compare 2024-03-22 14:19:23 +01:00
honzastor
7e1112cf81 Added individual input bus attributes to CGP Circuit objects to allow for the generation of output CGP representation. 2024-03-06 00:42:12 +01:00
Vojta Mrazek
f853a46703 CGP circuit checks 2023-04-13 12:09:07 +02:00
Vojta Mrazek
a44b0638a1 Implementation of QuAd approximate adder 2023-03-28 13:55:58 +02:00
Vojta Mrazek
a4741db191 connection checks (asserts) 2023-03-28 11:16:55 +02:00
Vojta Mrazek
44e0a920d1 MUX support of constant values 2023-03-24 12:11:42 +01:00
Vojta Mrazek
49bbc86a0f accepts a wire as a bus 2023-03-23 13:39:32 +01:00
Vojta Mrazek
363e402e16 workflow: docs 2023-03-23 08:00:37 +01:00
Vojta Mrazek
d16ab17512
Merge pull request #20 from ehw-fit/main 
Main to devel
 2023-03-23 07:53:54 +01:00
honzastor
7cf34d04f3 Bugfix in conditional statement. 2023-03-22 18:14:55 +01:00
honzastor
b88c502343 Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated). 2023-03-22 17:57:51 +01:00
Jan Klhůfek
cf747918bf
Merge pull request #19 from ehw-fit/devel 2023-02-24 14:12:40 +01:00
Vojta Mrazek
bb4c6d35a7 page deploy 2023-02-24 13:41:36 +01:00
Jan Klhůfek
6bbe9eb253
Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers. (#18) 2023-02-24 13:34:35 +01:00
honzastor
d52e67bb25 Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers. 2023-02-24 11:13:46 +01:00
Jan Klhůfek
2d7e157453
Merge pull request #17 from ehw-fit/devel 2023-02-22 18:59:31 +01:00
Vojta Mrazek
283f9c79f5
Merge branch 'main' into devel 2023-02-22 12:12:20 +01:00
Vojta Mrazek
d022195e48
Workflow (#16) 
* workflow

* workflow

* workflow
 2023-02-22 12:08:21 +01:00
Vojta Mrazek
da4347148c workflow python 3.6 version 2023-02-22 10:00:32 +01:00
Vojta Mrazek
60c4d3d24e workflow python 3.6 version 2023-02-22 09:55:19 +01:00
Vojta Mrazek
6dd69c5aaa Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel 2023-02-22 09:52:34 +01:00
Vojta Mrazek
43b3d65463 workflow modification, bus indexing 2023-02-22 09:52:06 +01:00
Vojta Mrazek
71a1d45045
string description (#15) 2023-02-22 09:45:14 +01:00
Vojta Mrazek
35240abc63 fix bug in python interpretation 2023-02-22 09:43:24 +01:00
Vojta Mrazek
a4a48dea57
Create codeql-analysis.yml (#14) 2022-05-26 10:08:35 +02:00
Jan Klhůfek
56c86c13ca
New multipliers (#13) 
* #10 CGP Circuits as inputs (#11)

* CGP Circuits as inputs

* #10 support of signed output in general circuit

* input as output works

* output connected to input (c)

* automated verilog testing

* output rename

* Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup.

* Typos fix and code cleanup.

* Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.

* Updated automated testing scripts.

* Small bugfix in python code generation (I initially thought this line is useless).

* Updated generated circuits folder.

Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
 2022-04-17 16:00:00 +02:00
Honza
f17e87738e Updated generated circuits folder. 2022-04-17 13:41:32 +02:00
Honza
b1ddc8c387 Small bugfix in python code generation (I initially thought this line is useless). 2022-04-17 13:25:10 +02:00
Honza
5d2f4e07e7 Updated automated testing scripts. 2022-04-17 13:06:46 +02:00
Honza
c0dcf42499 Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. 2022-04-17 13:04:17 +02:00
Jan Klhůfek
5475e3aa75
Added ArXiv badge and paper reference (#12) 
* Update README.md

* Update README.md

* Update README.md

* Update README.md
 2022-03-25 07:19:38 +01:00
Honza
9e186d10ed Typos fix and code cleanup. 2022-02-18 17:24:09 +01:00
Honza
6f05db002e Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. 2022-02-18 17:00:31 +01:00
Vojta Mrazek
3c47407f80 output rename 2022-02-07 11:29:12 +01:00
Vojta Mrazek
1c2efef024 automated verilog testing 2022-02-02 13:19:54 +01:00
Vojta Mrazek
ee8621ef4d output connected to input (c) 2022-02-02 12:53:18 +01:00
Vojta Mrazek
dc705106b4 input as output works 2022-02-02 11:19:32 +01:00
Vojta Mrazek
1e44c2e3dc
#10 CGP Circuits as inputs (#11) 
* CGP Circuits as inputs

* #10 support of signed output in general circuit
 2022-02-01 13:23:26 +01:00
Vojta Mrazek
d445f9e3c7
Merge pull request #9 from ehw-fit/devel 
Develop
v1.0 		2022-01-13 16:16:02 +01:00
Vojta Mrazek
5646334b7f workflow axmult typo 2022-01-13 16:11:48 +01:00
Vojta Mrazek
aeacd72d24 Readme, axmults in workflow 2022-01-13 16:10:51 +01:00
Honza
13c085f169 Fixed a small bug – missing ending semicolon in generation of library desired HA/FA to Verilog. Added script for generation of AX multipliers. 2022-01-13 13:11:24 +01:00
Vojta Mrazek
d641595c3e Support of PDK in HA and FA 2022-01-13 12:37:09 +01:00
Honza
18b44226d8 Small bugfixes and removal of redundant code. 2022-01-07 20:36:51 +01:00
Honza
d9b56e8a00 Fixed generation of unsigned variants of BAM and TM multipliers. Signed versions don't guarantee correct funcionality atm. 2022-01-06 19:23:56 +01:00
Honza
2075c0edf5 Another fix 2022-01-06 06:46:11 +01:00