bb94958118
Fix unsigned mul test
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2024-11-14 15:22:46 +01:00
c476479827
Fix mux with wrong gate ordering
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2024-11-14 15:15:17 +01:00
Lukas Plevac
09a12f3df7
Fully working xorGateComponent
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2024-10-10 13:33:09 +02:00
Lukas Plevac
c61244c966
Fixed RCA by test
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2024-10-08 14:28:38 +02:00
Lukas Plevac
ad9f62e3de
Added support for MIG excluded xor and xnor gate
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2024-10-07 15:19:55 +02:00
honzastor
b87f8350fc
Added ripple borrow subtractor circuit and updated automated testing.
2024-10-01 18:42:11 +02:00
Vojta Mrazek
bc0104de12
ripple cary subtractor
2024-07-09 09:22:11 +02:00
honzastor
f4b816fc09
Fix for workflow tests
2024-04-14 16:36:45 +02:00
honzastor
6003886eb7
Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later
2024-04-14 16:29:10 +02:00
honzastor
97e79b93da
Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue.
2024-04-13 17:04:03 +02:00
honzastor
739d5fafce
Added documentation to Recursive multiplier and hopefully fixed some issues with popcount output generation.
2024-04-08 21:37:34 +02:00
Vojta Mrazek
84a41ad93c
test unique #21
2024-04-05 11:25:37 +02:00
Vojta Mrazek
128b1309a1
popcount fixes
2024-04-05 09:24:03 +02:00
Vojta Mrazek
1219d7bec5
Merge branch 'popcount' into devel
2024-04-05 09:19:04 +02:00
Vojta Mrazek
2cf7b921ea
Popcount implementation
2024-04-05 08:46:02 +02:00
honzastor
da733cf44e
Added instantiation of wires and buses from inputs. Hopefully fixed now.
2024-03-28 00:06:53 +01:00
honzastor
cd3441ff00
Removed error tests from overall testing.
2024-03-27 23:44:34 +01:00
honzastor
d013a40145
Added unsigned recursive multiplier and made some bugfixes.
2024-03-27 23:00:13 +01:00
Vojta Mrazek
2e1694ccd5
popcount and compare
2024-03-22 14:19:23 +01:00
Vojta Mrazek
a44b0638a1
Implementation of QuAd approximate adder
2023-03-28 13:55:58 +02:00
Vojta Mrazek
49bbc86a0f
accepts a wire as a bus
2023-03-23 13:39:32 +01:00
honzastor
d52e67bb25
Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.
2023-02-24 11:13:46 +01:00
Vojta Mrazek
283f9c79f5
Merge branch 'main' into devel
2023-02-22 12:12:20 +01:00
Vojta Mrazek
43b3d65463
workflow modification, bus indexing
2023-02-22 09:52:06 +01:00
Vojta Mrazek
35240abc63
fix bug in python interpretation
2023-02-22 09:43:24 +01:00
Jan Klhůfek
56c86c13ca
New multipliers ( #13 )
...
* #10 CGP Circuits as inputs (#11 )
* CGP Circuits as inputs
* #10 support of signed output in general circuit
* input as output works
* output connected to input (c)
* automated verilog testing
* output rename
* Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup.
* Typos fix and code cleanup.
* Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.
* Updated automated testing scripts.
* Small bugfix in python code generation (I initially thought this line is useless).
* Updated generated circuits folder.
Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
2022-04-17 16:00:00 +02:00
Honza
5d2f4e07e7
Updated automated testing scripts.
2022-04-17 13:06:46 +02:00
Honza
9e186d10ed
Typos fix and code cleanup.
2022-02-18 17:24:09 +01:00
Vojta Mrazek
3c47407f80
output rename
2022-02-07 11:29:12 +01:00
Vojta Mrazek
1c2efef024
automated verilog testing
2022-02-02 13:19:54 +01:00
Vojta Mrazek
ee8621ef4d
output connected to input (c)
2022-02-02 12:53:18 +01:00
Vojta Mrazek
dc705106b4
input as output works
2022-02-02 11:19:32 +01:00
Vojta Mrazek
1e44c2e3dc
#10 CGP Circuits as inputs ( #11 )
...
* CGP Circuits as inputs
* #10 support of signed output in general circuit
2022-02-01 13:23:26 +01:00
Honza
d9b56e8a00
Fixed generation of unsigned variants of BAM and TM multipliers. Signed versions don't guarantee correct funcionality atm.
2022-01-06 19:23:56 +01:00
Honza
2075c0edf5
Another fix
2022-01-06 06:46:11 +01:00
Honza
b66c1bdfe0
Import fix
2022-01-06 06:42:26 +01:00
Honza
9aa0fb1858
Added broken array multiplier and truncated multiplier implementations. Tried testing them, but seems buggy. Needs further work.
2022-01-06 06:39:58 +01:00
honzastor
d41c5f3c94
Updated exportation of signed arithmetic circuits to python representation. Also unified some methods from arithmetic_circuit.py into general_circuit.py.
2021-10-10 22:15:13 +02:00
honzastor
16c1757bc3
Added signedness support for the output C code representation. Also modified the testing scripts and the chr2c.py converter accordingly and did some documentation changes (even made a small change in readme.md). Signedness support for the output python representation is TBD.
2021-10-09 23:45:54 +02:00
Vojta Mrazek
152a6b1583
Python eval ( #4 )
...
* #3 basic clean up arithmetic circuit and general circuit
* #3 implementation of python generator
* #3 pytest in actions
* #3 pytest in actions fix
2021-10-04 11:58:28 +02:00
Vojta Mrazek
f1303864ca
test all
2021-09-07 09:44:23 +02:00
Vojta Mrazek
fffb928875
auto test MAC
2021-09-07 08:32:52 +02:00
Vojta Mrazek
c6e542231c
CGP tests; reversed output order
2021-06-23 13:43:58 +02:00
Vojta Mrazek
cfe0ca6b4b
Automated testing, preparing the package for publishing ( #1 )
...
* automated pandoc deploy
* automated pandoc deploy (v2)
* automated pandoc deploy (v2)
* automated pdoc deploy (v3)
* automated pdoc deploy (v4)
* automated pdoc deploy (v5)
* automated pdoc deploy (v5)
* prepare for python project
* 8-bit testing
* 8-bit testing
* 8-bit testing (v2)
* 8-bit testing (v3)
* update of sign
2021-06-18 12:38:11 +02:00
