diff --git a/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py b/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
index d48a0d9..18f0e49 100644
--- a/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
+++ b/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
@@ -26,6 +26,7 @@ class FullAdder(ThreeInputOneBitCircuit):
         name (str, optional): Name of full adder. Defaults to "fa".
     """
     use_verilog_instance = False
+    disable_generation   = False
 
     def __init__(self, a: Wire = Wire(name="a"), b: Wire = Wire(name="b"), c: Wire = Wire(name="cin"), prefix: str = "", name: str = "fa"):
         super().__init__(a, b, c, prefix=prefix, name=name)