From 6c8c791fb5bf75ab6424b86dfbb6312d2b8a33a9 Mon Sep 17 00:00:00 2001 From: Lukas Plevac Date: Sun, 19 Jan 2025 18:34:06 +0100 Subject: [PATCH] Code generation fix --- .../one_bit_components/three_input_one_bit_components.py | 1 + 1 file changed, 1 insertion(+) diff --git a/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py b/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py index d48a0d9..18f0e49 100644 --- a/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py +++ b/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py @@ -26,6 +26,7 @@ class FullAdder(ThreeInputOneBitCircuit): name (str, optional): Name of full adder. Defaults to "fa". """ use_verilog_instance = False + disable_generation = False def __init__(self, a: Wire = Wire(name="a"), b: Wire = Wire(name="b"), c: Wire = Wire(name="cin"), prefix: str = "", name: str = "fa"): super().__init__(a, b, c, prefix=prefix, name=name)