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This commit is contained in:
Lukáš Plevač 2023-12-03 21:22:55 +01:00
parent c6a162fe59
commit b92289e7d5
78 changed files with 3567 additions and 7860 deletions
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3
Makefile
View File

@ -1,3 +1,6 @@
run:
/tools/Xilinx/Vivado/2023.2/bin/vivado
build:
cd synth && \
/tools/Xilinx/Vivado/2023.2/bin/vivado -mode batch -source filter.tcl

3
comp/block_memory.vhd
View File

@ -48,6 +48,9 @@ architecture behavioral of block_memory is
signal memory : memory_type;
signal memory_data : std_logic_vector(ITEM_WIDTH-1 downto 0);
signal memory_data_valid : std_logic;
attribute ramstyle : string;
attribute ramstyle of memory : signal is "M20K";
begin

106
comp/jenkins_final.vhd
View File

@ -69,54 +69,88 @@ begin
s(0).valid <= INPUT_VALID;
-- Stage 1: c ^= b; c -= rot(b,14);
s(1).a <= s(0).a;
s(1).b <= s(0).b;
s(1).c <= (s(0).c xor s(0).b) - rot(s(0).b, 14);
s(1).key <= s(0).key;
s(1).valid <= s(0).valid;
stage1_p : process ( clk ) is
begin
if rising_edge ( clk ) then
s(1).a <= s(0).a;
s(1).b <= s(0).b;
s(1).c <= (s(0).c xor s(0).b) - rot(s(0).b, 14);
s(1).key <= s(0).key;
s(1).valid <= s(0).valid;
end if;
end process;
-- Stage 2: a ^= c; a -= rot(c,11);
s(2).a <= (s(1).a xor s(1).c) - rot(s(1).c, 11);
s(2).b <= s(1).b;
s(2).c <= s(1).c;
s(2).key <= s(1).key;
s(2).valid <= s(1).valid;
stage2_p : process ( clk ) is
begin
if rising_edge ( clk ) then
s(2).a <= (s(1).a xor s(1).c) - rot(s(1).c, 11);
s(2).b <= s(1).b;
s(2).c <= s(1).c;
s(2).key <= s(1).key;
s(2).valid <= s(1).valid;
end if;
end process;
-- Stage 3: b ^= a; b -= rot(a,25);
s(3).a <= s(2).a;
s(3).b <= (s(2).b xor s(2).a) - rot(s(2).a, 25);
s(3).c <= s(2).c;
s(3).key <= s(2).key;
s(3).valid <= s(2).valid;
stage3_p : process ( clk ) is
begin
if rising_edge ( clk ) then
s(3).a <= s(2).a;
s(3).b <= (s(2).b xor s(2).a) - rot(s(2).a, 25);
s(3).c <= s(2).c;
s(3).key <= s(2).key;
s(3).valid <= s(2).valid;
end if;
end process;
-- Stage 4: c ^= b; c -= rot(b,16);
s(4).a <= s(3).a;
s(4).b <= s(3).b;
s(4).c <= (s(3).c xor s(3).b) - rot(s(3).b, 16);
s(4).key <= s(3).key;
s(4).valid <= s(3).valid;
stage4_p : process ( clk ) is
begin
if rising_edge ( clk ) then
s(4).a <= s(3).a;
s(4).b <= s(3).b;
s(4).c <= (s(3).c xor s(3).b) - rot(s(3).b, 16);
s(4).key <= s(3).key;
s(4).valid <= s(3).valid;
end if;
end process;
-- Stage 5: a ^= c; a -= rot(c,4);
s(5).a <= (s(4).a xor s(4).c) - rot(s(4).c, 4);
s(5).b <= s(4).b;
s(5).c <= s(4).c;
s(5).key <= s(4).key;
s(5).valid <= s(4).valid;
stage5_p : process ( clk ) is
begin
if rising_edge ( clk ) then
s(5).a <= (s(4).a xor s(4).c) - rot(s(4).c, 4);
s(5).b <= s(4).b;
s(5).c <= s(4).c;
s(5).key <= s(4).key;
s(5).valid <= s(4).valid;
end if;
end process;
-- Stage 6: b ^= a; b -= rot(a,14);
s(6).a <= s(5).a;
s(6).b <= (s(5).b xor s(5).a) - rot(s(5).a, 14);
s(6).c <= s(5).c;
s(6).key <= s(5).key;
s(6).valid <= s(5).valid;
stage6_p : process ( clk ) is
begin
if rising_edge ( clk ) then
s(6).a <= s(5).a;
s(6).b <= (s(5).b xor s(5).a) - rot(s(5).a, 14);
s(6).c <= s(5).c;
s(6).key <= s(5).key;
s(6).valid <= s(5).valid;
end if;
end process;
-- Stage 7: c ^= b; c -= rot(b,24);
s(7).a <= s(6).a;
s(7).b <= s(6).b;
s(7).c <= (s(6).c xor s(6).b) - rot(s(6).b, 24);
s(7).key <= s(6).key;
s(7).valid <= s(6).valid;
stage7_p : process ( clk ) is
begin
if rising_edge ( clk ) then
s(7).a <= s(6).a;
s(7).b <= s(6).b;
s(7).c <= (s(6).c xor s(6).b) - rot(s(6).b, 24);
s(7).key <= s(6).key;
s(7).valid <= s(6).valid;
end if;
end process;
-- Output connections
OUTPUT_A <= s(STAGES).a;

93
comp/jenkins_mix.vhd
View File

@ -68,47 +68,78 @@ begin
s(0).key <= INPUT_KEY;
s(0).valid <= INPUT_VALID;
-- Stage 1: a -= c; a ^= rot(c, 4); c += b;
s(1).a <= (s(0).a - s(0).c) xor rot(s(0).c, 4);
s(1).b <= s(0).b;
s(1).c <= s(0).c + s(0).b;
s(1).key <= s(0).key;
s(1).valid <= s(0).valid;
stage1_p : process ( clk ) is
begin
if rising_edge ( clk ) then
s(1).a <= (s(0).a - s(0).c) xor rot(s(0).c, 4);
s(1).b <= s(0).b;
s(1).c <= s(0).c + s(0).b;
s(1).key <= s(0).key;
s(1).valid <= s(0).valid;
end if;
end process;
-- Stage 2: b -= a; b ^= rot(a, 6); a += c;
s(2).a <= s(1).a + s(1).c;
s(2).b <= (s(1).b - s(1).a) xor rot(s(1).a, 6);
s(2).c <= s(1).c;
s(2).key <= s(1).key;
s(2).valid <= s(1).valid;
stage2_p : process ( clk ) is
begin
if rising_edge ( clk ) then
s(2).a <= s(1).a + s(1).c;
s(2).b <= (s(1).b - s(1).a) xor rot(s(1).a, 6);
s(2).c <= s(1).c;
s(2).key <= s(1).key;
s(2).valid <= s(1).valid;
end if;
end process;
-- Stage 3: c -= b; c ^= rot(b, 8); b += a;
s(3).a <= s(2).a;
s(3).b <= s(2).b + s(2).a;
s(3).c <= (s(2).c - s(2).b) xor rot(s(2).b, 8);
s(3).key <= s(2).key;
s(3).valid <= s(2).valid;
stage3_p : process ( clk ) is
begin
if rising_edge ( clk ) then
s(3).a <= s(2).a;
s(3).b <= s(2).b + s(2).a;
s(3).c <= (s(2).c - s(2).b) xor rot(s(2).b, 8);
s(3).key <= s(2).key;
s(3).valid <= s(2).valid;
end if;
end process;
-- Stage 4: a -= c; a ^= rot(c,16); c += b;
s(4).a <= (s(3).a - s(3).c) xor rot(s(3).c, 16);
s(4).b <= s(3).b;
s(4).c <= s(3).c + s(3).b;
s(4).key <= s(3).key;
s(4).valid <= s(3).valid;
stage4_p : process ( clk ) is
begin
if rising_edge ( clk ) then
s(4).a <= (s(3).a - s(3).c) xor rot(s(3).c, 16);
s(4).b <= s(3).b;
s(4).c <= s(3).c + s(3).b;
s(4).key <= s(3).key;
s(4).valid <= s(3).valid;
end if;
end process;
-- Stage 5: b -= a; b ^= rot(a,19); a += c;
s(5).a <= s(4).a + s(4).c;
s(5).b <= (s(4).b - s(4).a) xor rot(s(4).a, 19);
s(5).c <= s(4).c;
s(5).key <= s(4).key;
s(5).valid <= s(4).valid;
stage5_p : process ( clk ) is
begin
if rising_edge ( clk ) then
s(5).a <= s(4).a + s(4).c;
s(5).b <= (s(4).b - s(4).a) xor rot(s(4).a, 19);
s(5).c <= s(4).c;
s(5).key <= s(4).key;
s(5).valid <= s(4).valid;
end if;
end process;
-- Stage 6: c -= b; c ^= rot(b, 4); b += a;
s(6).a <= s(5).a;
s(6).b <= s(5).b + s(5).a;
s(6).c <= (s(5).c - s(5).b) xor rot(s(5).b, 4);
s(6).key <= s(5).key;
s(6).valid <= s(5).valid;
stage6_p : process ( clk ) is
begin
if rising_edge ( clk ) then
s(6).a <= s(5).a;
s(6).b <= s(5).b + s(5).a;
s(6).c <= (s(5).c - s(5).b) xor rot(s(5).b, 4);
s(6).key <= s(5).key;
s(6).valid <= s(5).valid;
end if;
end process;
-- Output connections
OUTPUT_A <= s(STAGES).a;

2
synth/filter_vivado.cache/wt/project.wpc
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@ -1,4 +1,4 @@
version:1
6d6f64655f636f756e7465727c42617463684d6f6465:1
6d6f64655f636f756e7465727c4755494d6f6465:1
6d6f64655f636f756e7465727c4755494d6f6465:2
eof:

8
synth/filter_vivado.cache/wt/synthesis.wdf
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@ -45,7 +45,7 @@ version:1
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a323273:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323235322e3335394d42:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3937312e3130394d42:00:00
eof:55709678
73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a303873:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323236392e3735344d42:00:00
73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3937342e3137324d42:00:00
eof:920102437

4
synth/filter_vivado.cache/wt/webtalk_pa.xml
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@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Sun Dec 3 18:51:31 2023">
<application name="pa" timeStamp="Sun Dec 3 21:14:11 2023">
<section name="Project Information" visible="false">
<property name="ProjectID" value="c9dd3875e3334360b2616c96fbb25f60" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
<property name="ProjectIteration" value="7" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">

15
synth/filter_vivado.runs/.jobs/vrs_config_10.xml Normal file
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@ -0,0 +1,15 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
</Parameters>
<ProductInfo Name="vivado"/>
</Runs>

12
synth/filter_vivado.runs/.jobs/vrs_config_4.xml Normal file
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@ -0,0 +1,12 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
</Parameters>
<ProductInfo Name="vivado"/>
</Runs>

12
synth/filter_vivado.runs/.jobs/vrs_config_5.xml Normal file
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@ -0,0 +1,12 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="impl_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
</Parameters>
<ProductInfo Name="vivado"/>
</Runs>

15
synth/filter_vivado.runs/.jobs/vrs_config_6.xml Normal file
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@ -0,0 +1,15 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
</Parameters>
<ProductInfo Name="vivado"/>
</Runs>

15
synth/filter_vivado.runs/.jobs/vrs_config_7.xml Normal file
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@ -0,0 +1,15 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
</Parameters>
<ProductInfo Name="vivado"/>
</Runs>

15
synth/filter_vivado.runs/.jobs/vrs_config_8.xml Normal file
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@ -0,0 +1,15 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
</Parameters>
<ProductInfo Name="vivado"/>
</Runs>

15
synth/filter_vivado.runs/.jobs/vrs_config_9.xml Normal file
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@ -0,0 +1,15 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="0">
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
<Run Id="impl_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
<Parent Id="synth_1"/>
</Run>
<Parameters>
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
</Parameters>
<ProductInfo Name="vivado"/>
</Runs>

2
synth/filter_vivado.runs/impl_1/.init_design.begin.rst
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@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="veronikaplevacova" Host="" Pid="19329">
<Process Command=".planAhead." Owner="veronikaplevacova" Host="" Pid="50397">
</Process>
</ProcessHandle>

2
synth/filter_vivado.runs/impl_1/.opt_design.begin.rst
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@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="veronikaplevacova" Host="" Pid="19329">
<Process Command=".planAhead." Owner="veronikaplevacova" Host="" Pid="50397">
</Process>
</ProcessHandle>

2
synth/filter_vivado.runs/impl_1/.phys_opt_design.begin.rst
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@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="veronikaplevacova" Host="" Pid="19329">
<Process Command=".planAhead." Owner="veronikaplevacova" Host="" Pid="50397">
</Process>
</ProcessHandle>

2
synth/filter_vivado.runs/impl_1/.place_design.begin.rst
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@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="veronikaplevacova" Host="" Pid="19329">
<Process Command=".planAhead." Owner="veronikaplevacova" Host="" Pid="50397">
</Process>
</ProcessHandle>

2
synth/filter_vivado.runs/impl_1/.route_design.begin.rst
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@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command=".planAhead." Owner="veronikaplevacova" Host="" Pid="19329">
<Process Command=".planAhead." Owner="veronikaplevacova" Host="" Pid="50397">
</Process>
</ProcessHandle>

22
synth/filter_vivado.runs/impl_1/.vivado.begin.rst
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@ -1,5 +1,25 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="19271" HostCore="4" HostMemory="3812172">
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="29770" HostCore="4" HostMemory="3812172">
</Process>
</ProcessHandle>
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="35112" HostCore="4" HostMemory="3812172">
</Process>
</ProcessHandle>
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="39451" HostCore="4" HostMemory="3812172">
</Process>
</ProcessHandle>
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="44480" HostCore="4" HostMemory="3812172">
</Process>
</ProcessHandle>
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="50339" HostCore="4" HostMemory="3812172">
</Process>
</ProcessHandle>

2
synth/filter_vivado.runs/impl_1/clockInfo.txt
View File

@ -1,6 +1,6 @@
-------------------------------------
| Tool Version : Vivado v.2023.2
| Date : Sun Dec 3 18:52:50 2023
| Date : Sun Dec 3 21:17:35 2023
| Host : veronika-swiftsf11433
| Design : design_1
| Device : xc7k160t-ffv676-1--

7
synth/filter_vivado.runs/impl_1/filter.tcl
View File

@ -115,8 +115,6 @@ proc step_failed { step } {
OPTRACE "impl_1" END { }
}
set_msg_config -id {Synth 8-256} -limit 10000
set_msg_config -id {Synth 8-638} -limit 10000
OPTRACE "impl_1" START { ROLLUP_1 }
OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
@ -125,8 +123,6 @@ set ACTIVE_STEP init_design
set rc [catch {
create_msg_db init_design.pb
set_param chipscope.maxJobs 1
set_param checkpoint.writeSynthRtdsInDcp 1
set_param synth.incrementalSynthesisCache /tmp/.Xil_veronikaplevacova/Vivado-18297-veronika-swiftsf11433/incrSyn
set_param runs.launchOptions { -jobs 2 }
OPTRACE "create in-memory project" START { }
create_project -in_memory -part xc7k160tffv676-1
@ -148,7 +144,7 @@ OPTRACE "read constraints: implementation_pre" START { }
OPTRACE "read constraints: implementation_pre" END { }
OPTRACE "add files" END { }
OPTRACE "link_design" START { }
link_design -top filter -part xc7k160tffv676-1 -mode out_of_context
link_design -top filter -part xc7k160tffv676-1
OPTRACE "link_design" END { }
OPTRACE "gray box cells" START { }
OPTRACE "gray box cells" END { }
@ -181,6 +177,7 @@ OPTRACE "read constraints: opt_design_post" START { }
OPTRACE "read constraints: opt_design_post" END { }
OPTRACE "opt_design reports" START { REPORT }
create_report "impl_1_opt_report_drc_0" "report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx"
create_report "impl_1_opt_report_timing_summary_0" "report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_opted.rpt -pb filter_timing_summary_opted.pb -rpx filter_timing_summary_opted.rpx"
OPTRACE "opt_design reports" END { }
OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT }
write_checkpoint -force filter_opt.dcp

1314
synth/filter_vivado.runs/impl_1/filter.vdi
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2
synth/filter_vivado.runs/impl_1/filter_bus_skew_routed.rpt
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@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date : Sun Dec 3 18:58:41 2023
| Date : Sun Dec 3 21:20:44 2023
| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux
| Command : report_bus_skew -warn_on_violation -file filter_bus_skew_routed.rpt -pb filter_bus_skew_routed.pb -rpx filter_bus_skew_routed.rpx
| Design : filter

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2
synth/filter_vivado.runs/impl_1/filter_clock_utilization_routed.rpt
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@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date : Sun Dec 3 18:58:41 2023
| Date : Sun Dec 3 21:20:44 2023
| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux
| Command : report_clock_utilization -file filter_clock_utilization_routed.rpt
| Design : filter

12
synth/filter_vivado.runs/impl_1/filter_control_sets_placed.rpt
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@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date : Sun Dec 3 18:54:00 2023
| Date : Sun Dec 3 21:18:40 2023
| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux
| Command : report_control_sets -verbose -file filter_control_sets_placed.rpt
| Design : filter
@ -27,7 +27,7 @@ Table of Contents
| Minimum number of control sets | 2 |
| Addition due to synthesis replication | 0 |
| Addition due to physical synthesis replication | 0 |
| Unused register locations in slices containing registers | 5 |
| Unused register locations in slices containing registers | 9 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions
@ -58,9 +58,9 @@ Table of Contents
+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No | No | No | 559 | 206 |
| No | No | No | 4835 | 1097 |
| No | No | Yes | 0 | 0 |
| No | Yes | No | 4 | 2 |
| No | Yes | No | 4 | 3 |
| Yes | No | No | 0 | 0 |
| Yes | No | Yes | 0 | 0 |
| Yes | Yes | No | 0 | 0 |
@ -73,8 +73,8 @@ Table of Contents
+--------------+---------------+------------------+------------------+----------------+--------------+
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
+--------------+---------------+------------------+------------------+----------------+--------------+
| CLK | | RESET | 2 | 4 | 2.00 |
| CLK | | | 206 | 559 | 2.71 |
| CLK | | RESET | 3 | 4 | 1.33 |
| CLK | | | 1098 | 4996 | 4.55 |
+--------------+---------------+------------------+------------------+----------------+--------------+

2
synth/filter_vivado.runs/impl_1/filter_drc_opted.rpt
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@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date : Sun Dec 3 18:52:45 2023
| Date : Sun Dec 3 21:17:27 2023
| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux
| Command : report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx
| Design : filter

2
synth/filter_vivado.runs/impl_1/filter_drc_routed.rpt
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@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date : Sun Dec 3 18:58:32 2023
| Date : Sun Dec 3 21:20:35 2023
| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux
| Command : report_drc -file filter_drc_routed.rpt -pb filter_drc_routed.pb -rpx filter_drc_routed.rpx
| Design : filter

2
synth/filter_vivado.runs/impl_1/filter_io_placed.rpt
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@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date : Sun Dec 3 18:53:59 2023
| Date : Sun Dec 3 21:18:40 2023
| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux
| Command : report_io -file filter_io_placed.rpt
| Design : filter

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71
synth/filter_vivado.runs/impl_1/filter_power_routed.rpt
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@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date : Sun Dec 3 18:58:40 2023
| Date : Sun Dec 3 21:20:43 2023
| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux
| Command : report_power -file filter_power_routed.rpt -pb filter_power_summary_routed.pb -rpx filter_power_routed.rpx
| Design : filter
@ -30,14 +30,14 @@ Table of Contents
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 0.790 |
| Total On-Chip Power (W) | 0.689 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 0.675 |
| Dynamic (W) | 0.575 |
| Device Static (W) | 0.114 |
| Effective TJA (C/W) | 1.9 |
| Max Ambient (C) | 83.5 |
| Junction Temperature (C) | 26.5 |
| Max Ambient (C) | 83.7 |
| Junction Temperature (C) | 26.3 |
| Confidence Level | Medium |
| Setting File | --- |
| Simulation Activity File | --- |
@ -49,20 +49,21 @@ Table of Contents
1.1 On-Chip Components
----------------------
+----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Clocks | 0.024 | 3 | --- | --- |
| Slice Logic | 0.175 | 5524 | --- | --- |
| LUT as Logic | 0.163 | 3508 | 101400 | 3.46 |
| CARRY4 | 0.012 | 681 | 25350 | 2.69 |
| Register | <0.001 | 597 | 202800 | 0.29 |
| Others | 0.000 | 34 | --- | --- |
| Signals | 0.270 | 5168 | --- | --- |
| Block RAM | 0.206 | 34 | 325 | 10.46 |
| Static Power | 0.114 | | | |
| Total | 0.790 | | | |
+----------------+-----------+----------+-----------+-----------------+
+-------------------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+-------------------------+-----------+----------+-----------+-----------------+
| Clocks | 0.096 | 3 | --- | --- |
| Slice Logic | 0.127 | 10142 | --- | --- |
| LUT as Logic | 0.101 | 3625 | 101400 | 3.57 |
| CARRY4 | 0.013 | 745 | 25350 | 2.94 |
| Register | 0.012 | 4839 | 202800 | 2.39 |
| LUT as Shift Register | <0.001 | 82 | 35000 | 0.23 |
| Others | 0.000 | 34 | --- | --- |
| Signals | 0.147 | 7074 | --- | --- |
| Block RAM | 0.206 | 34 | 325 | 10.46 |
| Static Power | 0.114 | | | |
| Total | 0.689 | | | |
+-------------------------+-----------+----------+-----------+-----------------+
1.2 Power Supply Summary
@ -71,7 +72,7 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint | 1.000 | 0.703 | 0.660 | 0.043 | NA | Unspecified | NA |
| Vccint | 1.000 | 0.602 | 0.559 | 0.043 | NA | Unspecified | NA |
| Vccaux | 1.800 | 0.018 | 0.000 | 0.018 | NA | Unspecified | NA |
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
@ -141,23 +142,23 @@ Table of Contents
+-------------------------------+-----------+
| Name | Power (W) |
+-------------------------------+-----------+
| filter | 0.675 |
| hash_generate[0].hash | 0.100 |
| final | 0.023 |
| mix_pipeline[0].mix | 0.076 |
| hash_generate[1].hash | 0.105 |
| final | 0.023 |
| mix_pipeline[0].mix | 0.081 |
| hash_generate[2].hash | 0.101 |
| final | 0.022 |
| mix_pipeline[0].mix | 0.079 |
| hash_generate[3].hash | 0.102 |
| final | 0.024 |
| mix_pipeline[0].mix | 0.072 |
| filter | 0.575 |
| hash_generate[0].hash | 0.083 |
| final | 0.033 |
| mix_pipeline[0].mix | 0.050 |
| hash_generate[1].hash | 0.083 |
| final | 0.034 |
| mix_pipeline[0].mix | 0.048 |
| hash_generate[2].hash | 0.078 |
| final | 0.031 |
| mix_pipeline[0].mix | 0.047 |
| hash_generate[3].hash | 0.079 |
| final | 0.031 |
| mix_pipeline[0].mix | 0.046 |
| storage_generate[0].storage | 0.057 |
| storage_generate[1].storage | 0.059 |
| storage_generate[1].storage | 0.058 |
| storage_generate[2].storage | 0.057 |
| storage_generate[3].storage | 0.057 |
| storage_generate[3].storage | 0.056 |
+-------------------------------+-----------+

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synth/filter_vivado.runs/impl_1/filter_reports.tcl
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@ -1,129 +0,0 @@
#
# Report generation script generated by Vivado
#
proc create_report { reportName command } {
set status "."
append status $reportName ".fail"
if { [file exists $status] } {
eval file delete [glob $status]
}
send_msg_id runtcl-4 info "Executing : $command"
set retval [eval catch { $command } msg]
if { $retval != 0 } {
set fp [open $status w]
close $fp
send_msg_id runtcl-5 warning "$msg"
}
}
namespace eval ::optrace {
variable script "/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_reports.tcl"
variable category "vivado_impl"
}
# Try to connect to running dispatch if we haven't done so already.
# This code assumes that the Tcl interpreter is not using threads,
# since the ::dispatch::connected variable isn't mutex protected.
if {![info exists ::dispatch::connected]} {
namespace eval ::dispatch {
variable connected false
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
set result "true"
if {[catch {
if {[lsearch -exact [package names] DispatchTcl] < 0} {
set result [load librdi_cd_clienttcl[info sharedlibextension]]
}
if {$result eq "false"} {
puts "WARNING: Could not load dispatch client library"
}
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
if { $connect_id eq "" } {
puts "WARNING: Could not initialize dispatch client"
} else {
puts "INFO: Dispatch client connection id - $connect_id"
set connected true
}
} catch_res]} {
puts "WARNING: failed to connect to dispatch server - $catch_res"
}
}
}
}
if {$::dispatch::connected} {
# Remove the dummy proc if it exists.
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
rename ::OPTRACE ""
}
proc ::OPTRACE { task action {tags {} } } {
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
}
# dispatch is generic. We specifically want to attach logging.
::vitis_log::connect_client
} else {
# Add dummy proc if it doesn't exist.
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
# Do nothing
}
}
}
proc start_step { step } {
set stopFile ".stop.rst"
if {[file isfile .stop.rst]} {
puts ""
puts "*** Halting run - EA reset detected ***"
puts ""
puts ""
return -code error
}
set beginFile ".$step.begin.rst"
set platform "$::tcl_platform(platform)"
set user "$::tcl_platform(user)"
set pid [pid]
set host ""
if { [string equal $platform unix] } {
if { [info exist ::env(HOSTNAME)] } {
set host $::env(HOSTNAME)
} elseif { [info exist ::env(HOST)] } {
set host $::env(HOST)
}
} else {
if { [info exist ::env(COMPUTERNAME)] } {
set host $::env(COMPUTERNAME)
}
}
set ch [open $beginFile w]
puts $ch "<?xml version=\"1.0\"?>"
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
puts $ch " </Process>"
puts $ch "</ProcessHandle>"
close $ch
}
proc end_step { step } {
set endFile ".$step.end.rst"
set ch [open $endFile w]
close $ch
}
proc step_failed { step } {
set endFile ".$step.error.rst"
set ch [open $endFile w]
close $ch
OPTRACE "impl_1" END { }
}
set_msg_config -id {Synth 8-256} -limit 10000
set_msg_config -id {Synth 8-638} -limit 10000
if {$argv == "opt_design"} {
set retval [open_checkpoint filter_opt.dcp]
if { $retval == "checkpoint_filter_opt" } {
create_report "impl_1_opt_report_timing_summary_0" "report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_opted.rpt -pb filter_timing_summary_opted.pb -rpx filter_timing_summary_opted.rpx"
close_design
}
}

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synth/filter_vivado.runs/impl_1/filter_route_status.rpt
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@ -1,12 +1,12 @@
Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 8803 :
# of nets not needing routing.......... : 3633 :
# of internally routed nets........ : 3197 :
# of logical nets.......................... : 13669 :
# of nets not needing routing.......... : 6593 :
# of internally routed nets........ : 6157 :
# of implicitly routed ports....... : 436 :
# of routable nets..................... : 5170 :
# of fully routed nets............. : 5170 :
# of routable nets..................... : 7076 :
# of fully routed nets............. : 7076 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

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@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date : Sun Dec 3 18:54:00 2023
| Date : Sun Dec 3 21:18:40 2023
| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux
| Command : report_utilization -file filter_utilization_placed.rpt -pb filter_utilization_placed.pb
| Design : filter
@ -29,18 +29,20 @@ Table of Contents
1. Slice Logic
--------------
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
| Slice LUTs | 3503 | 0 | 0 | 101400 | 3.45 |
| LUT as Logic | 3503 | 0 | 0 | 101400 | 3.45 |
| LUT as Memory | 0 | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 563 | 0 | 0 | 202800 | 0.28 |
| Register as Flip Flop | 563 | 0 | 0 | 202800 | 0.28 |
| Register as Latch | 0 | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 50700 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 25350 | 0.00 |
+-------------------------+------+-------+------------+-----------+-------+
+----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+------+-------+------------+-----------+-------+
| Slice LUTs | 3706 | 0 | 0 | 101400 | 3.65 |
| LUT as Logic | 3624 | 0 | 0 | 101400 | 3.57 |
| LUT as Memory | 82 | 0 | 0 | 35000 | 0.23 |
| LUT as Distributed RAM | 0 | 0 | | | |
| LUT as Shift Register | 82 | 0 | | | |
| Slice Registers | 4839 | 0 | 0 | 202800 | 2.39 |
| Register as Flip Flop | 4839 | 0 | 0 | 202800 | 2.39 |
| Register as Latch | 0 | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 50700 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 25350 | 0.00 |
+----------------------------+------+-------+------------+-----------+-------+
* Warning! LUT value is adjusted to account for LUT combining.
@ -59,7 +61,7 @@ Table of Contents
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 563 | Yes | Reset | - |
| 4839 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@ -69,21 +71,24 @@ Table of Contents
+--------------------------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+--------------------------------------------+------+-------+------------+-----------+-------+
| Slice | 1066 | 0 | 0 | 25350 | 4.21 |
| SLICEL | 659 | 0 | | | |
| SLICEM | 407 | 0 | | | |
| LUT as Logic | 3503 | 0 | 0 | 101400 | 3.45 |
| Slice | 1259 | 0 | 0 | 25350 | 4.97 |
| SLICEL | 823 | 0 | | | |
| SLICEM | 436 | 0 | | | |
| LUT as Logic | 3624 | 0 | 0 | 101400 | 3.57 |
| using O5 output only | 0 | | | | |
| using O6 output only | 2799 | | | | |
| using O5 and O6 | 704 | | | | |
| LUT as Memory | 0 | 0 | 0 | 35000 | 0.00 |
| using O6 output only | 2886 | | | | |
| using O5 and O6 | 738 | | | | |
| LUT as Memory | 82 | 0 | 0 | 35000 | 0.23 |
| LUT as Distributed RAM | 0 | 0 | | | |
| LUT as Shift Register | 0 | 0 | | | |
| Slice Registers | 563 | 0 | 0 | 202800 | 0.28 |
| Register driven from within the Slice | 19 | | | | |
| Register driven from outside the Slice | 544 | | | | |
| LUT in front of the register is unused | 298 | | | | |
| LUT in front of the register is used | 246 | | | | |
| LUT as Shift Register | 82 | 0 | | | |
| using O5 output only | 1 | | | | |
| using O6 output only | 2 | | | | |
| using O5 and O6 | 79 | | | | |
| Slice Registers | 4839 | 0 | 0 | 202800 | 2.39 |
| Register driven from within the Slice | 2898 | | | | |
| Register driven from outside the Slice | 1941 | | | | |
| LUT in front of the register is unused | 862 | | | | |
| LUT in front of the register is used | 1079 | | | | |
| Unique Control Sets | 2 | | 0 | 25350 | <0.01 |
+--------------------------------------------+------+-------+------------+-----------+-------+
* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
@ -181,16 +186,16 @@ Table of Contents
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| LUT5 | 995 | LUT |
| LUT6 | 950 | LUT |
| LUT3 | 900 | LUT |
| LUT2 | 874 | LUT |
| CARRY4 | 681 | CarryLogic |
| FDRE | 563 | Flop & Latch |
| LUT4 | 260 | LUT |
| LUT1 | 228 | LUT |
| FDRE | 4839 | Flop & Latch |
| LUT2 | 3166 | LUT |
| LUT3 | 764 | LUT |
| CARRY4 | 745 | CarryLogic |
| LUT1 | 227 | LUT |
| LUT6 | 201 | LUT |
| SRL16E | 161 | Distributed Memory |
| RAMB36E1 | 32 | Block Memory |
| RAMB18E1 | 4 | Block Memory |
| LUT4 | 4 | LUT |
+----------+------+---------------------+

14
synth/filter_vivado.runs/impl_1/gen_run.xml
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@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="impl_1" LaunchPart="xc7k160tffv676-1" LaunchTime="1701625891">
<GenRun Id="impl_1" LaunchPart="xc7k160tffv676-1" LaunchTime="1701634451">
<File Type="ROUTE-RQS-RPT" Name="route_report_qor_suggestions_0.rpt"/>
<File Type="POSTROUTE-PHYSOPT-RQS" Name="filter_postroute_physopted.rqs"/>
<File Type="ROUTE-RQS" Name="filter_routed.rqs"/>
@ -25,12 +25,12 @@
<File Type="BG-BIN" Name="filter.bin"/>
<File Type="POSTROUTE-PHYSOPT-RQS-RPT" Name="postroute_physopt_report_qor_suggestions_0.rpt"/>
<File Type="BG-BIT" Name="filter.bit"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="filter_bus_skew_postroute_physopted.rpx"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="filter_bus_skew_postroute_physopted.pb"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="filter_bus_skew_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="filter_timing_summary_postroute_physopted.rpx"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="filter_timing_summary_postroute_physopted.pb"/>
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="filter_timing_summary_postroute_physopted.rpt"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="filter_bus_skew_postroute_physopted_1.rpx"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="filter_bus_skew_postroute_physopted_1.pb"/>
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="filter_bus_skew_postroute_physopted_1.rpt"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="filter_timing_summary_postroute_physopted_1.rpx"/>
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="filter_timing_summary_postroute_physopted_1.pb"/>
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="filter_timing_summary_postroute_physopted_1.rpt"/>
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="filter_postroute_physopt_bb.dcp"/>
<File Type="POSTROUTE-PHYSOPT-DCP" Name="filter_postroute_physopt.dcp"/>
<File Type="BG-DRC" Name="filter.drc"/>

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synth/filter_vivado.runs/impl_1/init_design.pb
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synth/filter_vivado.runs/impl_1/opt_design.pb
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41
synth/filter_vivado.runs/impl_1/opt_design_reports.log
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@ -1,41 +0,0 @@
*** Running vivado
with args -m64 -nolog -nojournal -notrace -mode batch -product Vivado -source filter_reports.tcl -tclargs opt_design
****** Vivado v2023.2 (64-bit)
**** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
**** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
**** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
source filter_reports.tcl -notrace
Command: open_checkpoint filter_opt.dcp
Starting open_checkpoint Task
Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1242.316 ; gain = 0.000 ; free physical = 206 ; free virtual = 6416
INFO: [Device 21-403] Loading part xc7k160tffv676-1
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1629.965 ; gain = 0.000 ; free physical = 208 ; free virtual = 7125
INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Read ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1706.652 ; gain = 1.000 ; free physical = 224 ; free virtual = 7060
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.262 ; gain = 0.000 ; free physical = 124 ; free virtual = 6613
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
INFO: [Project 1-604] Checkpoint was created with Vivado v2023.2 (64-bit) build 4029153
open_checkpoint: Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 2311.297 ; gain = 1068.980 ; free physical = 119 ; free virtual = 6616
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_opted.rpt -pb filter_timing_summary_opted.pb -rpx filter_timing_summary_opted.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 19:06:34 2023...

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synth/filter_vivado.runs/impl_1/phys_opt_design.pb
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synth/filter_vivado.runs/impl_1/place_design.pb
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synth/filter_vivado.runs/impl_1/route_design.pb
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12
synth/filter_vivado.runs/impl_1/route_design_reports.bat
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@ -1,12 +0,0 @@
@echo off
rem Vivado (TM)
rem route_design_reports.bat: a Vivado-generated Script
rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
set HD_SDIR=%~dp0
cd /d "%HD_SDIR%"
set PATH=%SYSTEMROOT%\system32;%PATH%
cscript /nologo /E:JScript "%HD_SDIR%\route_design_reports.js" %*

41
synth/filter_vivado.runs/impl_1/route_design_reports.js
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@ -1,41 +0,0 @@
//
// Vivado(TM)
// route_design_reports.js: a Vivado-generated reports generation script for WSH 5.1/5.6
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
//
echo "This script was generated under a different operating system."
echo "Please update the PATH variable below, before executing this script"
exit
var WshShell = new ActiveXObject( "WScript.Shell" );
var ProcEnv = WshShell.Environment( "Process" );
var PathVal = ProcEnv("PATH");
if ( PathVal.length == 0 ) {
PathVal = "/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2023.2/bin;";
} else {
PathVal = "/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2023.2/bin;" + PathVal;
}
ProcEnv("PATH") = PathVal;
var RDScrFP = WScript.ScriptFullName;
var RDScrN = WScript.ScriptName;
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
var ISEJScriptLib = RDScrDir + "/ISEWrapReports.js";
eval( EAInclude(ISEJScriptLib) );
ISEStep( "vivado",
" -m64 -nolog -nojournal -notrace -mode batch -product Vivado -source filter_reports.tcl -tclargs route_design" );
function EAInclude( EAInclFilename ) {
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
var EAIFContents = EAInclFile.ReadAll();
EAInclFile.Close();
return EAIFContents;
}

40
synth/filter_vivado.runs/impl_1/route_design_reports.sh
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@ -1,40 +0,0 @@
#!/bin/sh
#
# Vivado(TM)
# route_design_reports.sh: a Vivado-generated reports generation script for UNIX
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
#
if [ -z "$PATH" ]; then
PATH=/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2023.2/bin
else
PATH=/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2023.2/bin:$PATH
fi
export PATH
if [ -z "$LD_LIBRARY_PATH" ]; then
LD_LIBRARY_PATH=
else
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
fi
export LD_LIBRARY_PATH
HD_PWD='/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1'
cd "$HD_PWD"
HD_LOG=route_design_reports.log
/bin/touch $HD_LOG
ISEStep="./ISEWrapReports.sh"
EAStep()
{
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
if [ $? -ne 0 ]
then
exit
fi
}
EAStep vivado -m64 -nolog -nojournal -notrace -mode batch -product Vivado -source filter_reports.tcl -tclargs route_design

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synth/filter_vivado.runs/impl_1/runme.log
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6
synth/filter_vivado.runs/impl_1/vivado.jou
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@ -3,12 +3,12 @@
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Sun Dec 3 18:51:36 2023
# Process ID: 19329
# Start of session at: Sun Dec 3 21:16:13 2023
# Process ID: 50397
# Current directory: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1
# Command line: vivado -log filter.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source filter.tcl -notrace
# Log file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter.vdi
# Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/vivado.jou
# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2785.745 MHz, CPU Physical cores: 4, Host memory: 3903 MB
# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2785.806 MHz, CPU Physical cores: 4, Host memory: 3903 MB
#-----------------------------------------------------------
source filter.tcl -notrace

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synth/filter_vivado.runs/impl_1/vivado.pb
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2
synth/filter_vivado.runs/synth_1/.vivado.begin.rst
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@ -1,5 +1,5 @@
<?xml version="1.0"?>
<ProcessHandle Version="1" Minor="0">
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="18691" HostCore="4" HostMemory="3812172">
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="50035" HostCore="4" HostMemory="3812172">
</Process>
</ProcessHandle>

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synth/filter_vivado.runs/synth_1/filter.dcp
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1
synth/filter_vivado.runs/synth_1/filter.tcl
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@ -70,6 +70,7 @@ proc create_report { reportName command } {
}
}
OPTRACE "synth_1" START { ROLLUP_AUTO }
set_param chipscope.maxJobs 1
OPTRACE "Creating in-memory project" START { }
create_project -in_memory -part xc7k160tffv676-1

130
synth/filter_vivado.runs/synth_1/filter.vds
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@ -3,16 +3,16 @@
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Sun Dec 3 18:47:59 2023
# Process ID: 18749
# Start of session at: Sun Dec 3 21:14:16 2023
# Process ID: 50094
# Current directory: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1
# Command line: vivado -log filter.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source filter.tcl
# Log file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/filter.vds
# Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/vivado.jou
# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 3075.336 MHz, CPU Physical cores: 4, Host memory: 3903 MB
# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2783.625 MHz, CPU Physical cores: 4, Host memory: 3903 MB
#-----------------------------------------------------------
source filter.tcl -notrace
create_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1275.312 ; gain = 39.836 ; free physical = 248 ; free virtual = 8095
create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1291.613 ; gain = 39.836 ; free physical = 147 ; free virtual = 4464
Command: synth_design -top filter -part xc7k160tffv676-1 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t'
@ -20,9 +20,9 @@ INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160
INFO: [Device 21-403] Loading part xc7k160tffv676-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 18803
INFO: [Synth 8-7075] Helper process launched with PID 50143
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2039.840 ; gain = 404.684 ; free physical = 155 ; free virtual = 6867
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2055.203 ; gain = 403.746 ; free physical = 123 ; free virtual = 3529
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'filter' [/home/veronikaplevacova/Plocha/PCS2/filter.vhd:17]
INFO: [Synth 8-638] synthesizing module 'jenkins_hash' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40]
@ -53,23 +53,21 @@ INFO: [Synth 8-638] synthesizing module 'block_memory' [/home/veronikaplevacova/
Parameter OUTPUT_REGISTER bound to: 0 - type: bool
INFO: [Synth 8-256] done synthesizing module 'block_memory' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'filter' (0#1) [/home/veronikaplevacova/Plocha/PCS2/filter.vhd:17]
WARNING: [Synth 8-7129] Port CLK in module jenkins_final is either unconnected or has no load
WARNING: [Synth 8-7129] Port RESET in module jenkins_final is either unconnected or has no load
WARNING: [Synth 8-7129] Port CLK in module jenkins_mix is either unconnected or has no load
WARNING: [Synth 8-7129] Port RESET in module jenkins_mix is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2119.777 ; gain = 484.621 ; free physical = 119 ; free virtual = 6746
Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2138.141 ; gain = 486.684 ; free physical = 152 ; free virtual = 3299
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2137.590 ; gain = 502.434 ; free physical = 119 ; free virtual = 6727
Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2155.953 ; gain = 504.496 ; free physical = 133 ; free virtual = 3292
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2137.590 ; gain = 502.434 ; free physical = 119 ; free virtual = 6727
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2155.953 ; gain = 504.496 ; free physical = 133 ; free virtual = 3292
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2137.590 ; gain = 0.000 ; free physical = 94 ; free virtual = 6678
Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2155.953 ; gain = 0.000 ; free physical = 129 ; free virtual = 3282
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
@ -79,47 +77,47 @@ WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative
Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2252.324 ; gain = 0.000 ; free physical = 115 ; free virtual = 6314
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2269.719 ; gain = 0.000 ; free physical = 117 ; free virtual = 3243
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.93 . Memory (MB): peak = 2252.359 ; gain = 0.000 ; free physical = 108 ; free virtual = 6278
Constraint Validation Runtime : Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2269.754 ; gain = 0.000 ; free physical = 131 ; free virtual = 3246
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 106 ; free virtual = 5475
Finished Constraint Validation : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 185 ; free virtual = 3230
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k160tffv676-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 162 ; free virtual = 5460
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 185 ; free virtual = 3230
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 125 ; free virtual = 5450
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 185 ; free virtual = 3231
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 120 ; free virtual = 5337
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 180 ; free virtual = 3229
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 40
3 Input 32 Bit Adders := 52
4 Input 32 Bit Adders := 8
2 Input 32 Bit Adders := 24
+---XORs :
2 Input 32 Bit XORs := 52
+---Registers :
145 Bit Registers := 5
128 Bit Registers := 3
128 Bit Registers := 55
32 Bit Registers := 156
16 Bit Registers := 1
11 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 8
1 Bit Registers := 60
+---RAMs :
290K Bit (2048 X 145 bit) RAMs := 4
+---Muxes :
@ -141,12 +139,10 @@ Finished Part Resource Summary
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-7129] Port CLK in module jenkins_final is either unconnected or has no load
WARNING: [Synth 8-7129] Port RESET in module jenkins_final is either unconnected or has no load
WARNING: [Synth 8-7129] Port CLK in module jenkins_mix is either unconnected or has no load
WARNING: [Synth 8-7129] Port RESET in module jenkins_mix is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:47 ; elapsed = 00:00:59 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 131 ; free virtual = 5310
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 178 ; free virtual = 3189
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
@ -170,13 +166,13 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:56 ; elapsed = 00:01:09 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 175 ; free virtual = 5367
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 121 ; free virtual = 3182
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:01:03 ; elapsed = 00:01:17 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 243 ; free virtual = 5327
Finished Timing Optimization : Time (s): cpu = 00:00:48 ; elapsed = 00:00:50 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 193 ; free virtual = 3161
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
@ -235,7 +231,7 @@ INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/mem
INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:01:07 ; elapsed = 00:01:21 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 381 ; free virtual = 5319
Finished Technology Mapping : Time (s): cpu = 00:00:52 ; elapsed = 00:00:55 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 184 ; free virtual = 3158
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
@ -253,37 +249,55 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:01:16 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189
Finished IO Insertion : Time (s): cpu = 00:01:01 ; elapsed = 00:01:04 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:01:16 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189
Finished Renaming Generated Instances : Time (s): cpu = 00:01:01 ; elapsed = 00:01:04 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:17 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:02 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:01:17 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189
Finished Renaming Generated Ports : Time (s): cpu = 00:01:02 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:01:17 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189
Finished Handling Custom Attributes : Time (s): cpu = 00:01:03 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:01:17 ; elapsed = 00:01:34 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189
Finished Renaming Generated Nets : Time (s): cpu = 00:01:03 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Static Shift Register Report:
+------------+--------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
+------------+--------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|filter | hash_generate[0].hash/final/s_reg[7][valid] | 13 | 1 | NO | NO | NO | 1 | 0 |
|filter | memory_key_reg[127] | 8 | 32 | NO | NO | YES | 32 | 0 |
|filter | memory_key_reg[95] | 14 | 89 | NO | NO | YES | 89 | 0 |
|filter | memory_key_reg[38] | 13 | 7 | NO | NO | YES | 7 | 0 |
|filter | hash_generate[0].hash/mix_pipeline[0].mix/s_reg[6][key][100] | 7 | 32 | NO | YES | YES | 32 | 0 |
+------------+--------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@ -299,41 +313,41 @@ Report Cell Usage:
+------+---------+------+
| |Cell |Count |
+------+---------+------+
|1 |CARRY4 | 681|
|2 |LUT1 | 228|
|3 |LUT2 | 874|
|4 |LUT3 | 900|
|5 |LUT4 | 260|
|6 |LUT5 | 995|
|7 |LUT6 | 950|
|8 |RAMB18E1 | 4|
|9 |RAMB36E1 | 32|
|10 |FDRE | 563|
|1 |CARRY4 | 745|
|2 |LUT1 | 227|
|3 |LUT2 | 3166|
|4 |LUT3 | 764|
|5 |LUT4 | 4|
|6 |LUT6 | 201|
|7 |RAMB18E1 | 4|
|8 |RAMB36E1 | 32|
|9 |SRL16E | 161|
|10 |FDRE | 4794|
+------+---------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:01:17 ; elapsed = 00:01:34 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 164 ; free virtual = 5187
Finished Writing Synthesis Report : Time (s): cpu = 00:01:03 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 5 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:01:11 ; elapsed = 00:01:26 . Memory (MB): peak = 2252.359 ; gain = 502.434 ; free physical = 148 ; free virtual = 5185
Synthesis Optimization Complete : Time (s): cpu = 00:01:17 ; elapsed = 00:01:34 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 145 ; free virtual = 5184
Synthesis finished with 0 errors, 0 critical warnings and 3 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:57 ; elapsed = 00:01:00 . Memory (MB): peak = 2269.754 ; gain = 504.496 ; free physical = 134 ; free virtual = 3152
Synthesis Optimization Complete : Time (s): cpu = 00:01:03 ; elapsed = 00:01:06 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 134 ; free virtual = 3152
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2252.359 ; gain = 0.000 ; free physical = 115 ; free virtual = 5167
INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement
Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2269.754 ; gain = 0.000 ; free physical = 384 ; free virtual = 3430
INFO: [Netlist 29-17] Analyzing 781 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2252.359 ; gain = 0.000 ; free physical = 313 ; free virtual = 5535
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2269.754 ; gain = 0.000 ; free physical = 311 ; free virtual = 3423
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete | Checksum: d74e1ad3
Synth Design complete | Checksum: 806ce973
INFO: [Common 17-83] Releasing license: Synthesis
66 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered.
66 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:01:33 ; elapsed = 00:01:44 . Memory (MB): peak = 2252.359 ; gain = 977.047 ; free physical = 232 ; free virtual = 5481
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1724.537; main = 1326.676; forked = 397.861
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3235.051; main = 2252.328; forked = 982.723
Write ShapeDB Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2276.336 ; gain = 0.000 ; free physical = 226 ; free virtual = 5482
synth_design: Time (s): cpu = 00:01:18 ; elapsed = 00:01:16 . Memory (MB): peak = 2269.754 ; gain = 978.141 ; free physical = 301 ; free virtual = 3421
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1616.477; main = 1400.213; forked = 417.991
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3233.605; main = 2269.723; forked = 963.883
Write ShapeDB Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2269.754 ; gain = 0.000 ; free physical = 297 ; free virtual = 3420
INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/filter.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file filter_utilization_synth.rpt -pb filter_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 18:50:06 2023...
INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 21:15:58 2023...

BIN
synth/filter_vivado.runs/synth_1/filter_utilization_synth.pb
View File

Binary file not shown.

46
synth/filter_vivado.runs/synth_1/filter_utilization_synth.rpt
View File

@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date : Sun Dec 3 18:50:06 2023
| Date : Sun Dec 3 21:15:58 2023
| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux
| Command : report_utilization -file filter_utilization_synth.rpt -pb filter_utilization_synth.pb
| Design : filter
@ -28,18 +28,20 @@ Table of Contents
1. Slice Logic
--------------
+-------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+------+-------+------------+-----------+-------+
| Slice LUTs* | 3498 | 0 | 0 | 101400 | 3.45 |
| LUT as Logic | 3498 | 0 | 0 | 101400 | 3.45 |
| LUT as Memory | 0 | 0 | 0 | 35000 | 0.00 |
| Slice Registers | 563 | 0 | 0 | 202800 | 0.28 |
| Register as Flip Flop | 563 | 0 | 0 | 202800 | 0.28 |
| Register as Latch | 0 | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 50700 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 25350 | 0.00 |
+-------------------------+------+-------+------------+-----------+-------+
+----------------------------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+----------------------------+------+-------+------------+-----------+-------+
| Slice LUTs* | 3787 | 0 | 0 | 101400 | 3.73 |
| LUT as Logic | 3626 | 0 | 0 | 101400 | 3.58 |
| LUT as Memory | 161 | 0 | 0 | 35000 | 0.46 |
| LUT as Distributed RAM | 0 | 0 | | | |
| LUT as Shift Register | 161 | 0 | | | |
| Slice Registers | 4794 | 0 | 0 | 202800 | 2.36 |
| Register as Flip Flop | 4794 | 0 | 0 | 202800 | 2.36 |
| Register as Latch | 0 | 0 | 0 | 202800 | 0.00 |
| F7 Muxes | 0 | 0 | 0 | 50700 | 0.00 |
| F8 Muxes | 0 | 0 | 0 | 25350 | 0.00 |
+----------------------------+------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
Warning! LUT value is adjusted to account for LUT combining.
@ -59,7 +61,7 @@ Warning! LUT value is adjusted to account for LUT combining.
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 563 | Yes | Reset | - |
| 4794 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@ -155,16 +157,16 @@ Warning! LUT value is adjusted to account for LUT combining.
+----------+------+---------------------+
| Ref Name | Used | Functional Category |
+----------+------+---------------------+
| LUT5 | 995 | LUT |
| LUT6 | 950 | LUT |
| LUT3 | 900 | LUT |
| LUT2 | 874 | LUT |
| CARRY4 | 681 | CarryLogic |
| FDRE | 563 | Flop & Latch |
| LUT4 | 260 | LUT |
| LUT1 | 228 | LUT |
| FDRE | 4794 | Flop & Latch |
| LUT2 | 3166 | LUT |
| LUT3 | 764 | LUT |
| CARRY4 | 745 | CarryLogic |
| LUT1 | 227 | LUT |
| LUT6 | 201 | LUT |
| SRL16E | 161 | Distributed Memory |
| RAMB36E1 | 32 | Block Memory |
| RAMB18E1 | 4 | Block Memory |
| LUT4 | 4 | LUT |
+----------+------+---------------------+

2
synth/filter_vivado.runs/synth_1/gen_run.xml
View File

@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
<GenRun Id="synth_1" LaunchPart="xc7k160tffv676-1" LaunchTime="1701625674">
<GenRun Id="synth_1" LaunchPart="xc7k160tffv676-1" LaunchTime="1701634451">
<File Type="VDS-TIMINGSUMMARY" Name="filter_timing_summary_synth.rpt"/>
<File Type="RDS-DCP" Name="filter.dcp"/>
<File Type="RDS-UTIL-PB" Name="filter_utilization_synth.pb"/>

31
synth/filter_vivado.runs/synth_1/project.wdf
View File

@ -1,31 +0,0 @@
version:1
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124
synth/filter_vivado.runs/synth_1/runme.log
View File

@ -11,7 +11,7 @@
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
source filter.tcl -notrace
create_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1275.312 ; gain = 39.836 ; free physical = 248 ; free virtual = 8095
create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1291.613 ; gain = 39.836 ; free physical = 147 ; free virtual = 4464
Command: synth_design -top filter -part xc7k160tffv676-1 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t'
@ -19,9 +19,9 @@ INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160
INFO: [Device 21-403] Loading part xc7k160tffv676-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 18803
INFO: [Synth 8-7075] Helper process launched with PID 50143
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2039.840 ; gain = 404.684 ; free physical = 155 ; free virtual = 6867
Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2055.203 ; gain = 403.746 ; free physical = 123 ; free virtual = 3529
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'filter' [/home/veronikaplevacova/Plocha/PCS2/filter.vhd:17]
INFO: [Synth 8-638] synthesizing module 'jenkins_hash' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40]
@ -52,23 +52,21 @@ INFO: [Synth 8-638] synthesizing module 'block_memory' [/home/veronikaplevacova/
Parameter OUTPUT_REGISTER bound to: 0 - type: bool
INFO: [Synth 8-256] done synthesizing module 'block_memory' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'filter' (0#1) [/home/veronikaplevacova/Plocha/PCS2/filter.vhd:17]
WARNING: [Synth 8-7129] Port CLK in module jenkins_final is either unconnected or has no load
WARNING: [Synth 8-7129] Port RESET in module jenkins_final is either unconnected or has no load
WARNING: [Synth 8-7129] Port CLK in module jenkins_mix is either unconnected or has no load
WARNING: [Synth 8-7129] Port RESET in module jenkins_mix is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2119.777 ; gain = 484.621 ; free physical = 119 ; free virtual = 6746
Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2138.141 ; gain = 486.684 ; free physical = 152 ; free virtual = 3299
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2137.590 ; gain = 502.434 ; free physical = 119 ; free virtual = 6727
Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2155.953 ; gain = 504.496 ; free physical = 133 ; free virtual = 3292
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2137.590 ; gain = 502.434 ; free physical = 119 ; free virtual = 6727
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2155.953 ; gain = 504.496 ; free physical = 133 ; free virtual = 3292
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2137.590 ; gain = 0.000 ; free physical = 94 ; free virtual = 6678
Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2155.953 ; gain = 0.000 ; free physical = 129 ; free virtual = 3282
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
@ -78,47 +76,47 @@ WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative
Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2252.324 ; gain = 0.000 ; free physical = 115 ; free virtual = 6314
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2269.719 ; gain = 0.000 ; free physical = 117 ; free virtual = 3243
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.93 . Memory (MB): peak = 2252.359 ; gain = 0.000 ; free physical = 108 ; free virtual = 6278
Constraint Validation Runtime : Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2269.754 ; gain = 0.000 ; free physical = 131 ; free virtual = 3246
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 106 ; free virtual = 5475
Finished Constraint Validation : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 185 ; free virtual = 3230
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7k160tffv676-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 162 ; free virtual = 5460
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 185 ; free virtual = 3230
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 125 ; free virtual = 5450
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 185 ; free virtual = 3231
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 120 ; free virtual = 5337
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 180 ; free virtual = 3229
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
2 Input 32 Bit Adders := 40
3 Input 32 Bit Adders := 52
4 Input 32 Bit Adders := 8
2 Input 32 Bit Adders := 24
+---XORs :
2 Input 32 Bit XORs := 52
+---Registers :
145 Bit Registers := 5
128 Bit Registers := 3
128 Bit Registers := 55
32 Bit Registers := 156
16 Bit Registers := 1
11 Bit Registers := 1
2 Bit Registers := 1
1 Bit Registers := 8
1 Bit Registers := 60
+---RAMs :
290K Bit (2048 X 145 bit) RAMs := 4
+---Muxes :
@ -140,12 +138,10 @@ Finished Part Resource Summary
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-7129] Port CLK in module jenkins_final is either unconnected or has no load
WARNING: [Synth 8-7129] Port RESET in module jenkins_final is either unconnected or has no load
WARNING: [Synth 8-7129] Port CLK in module jenkins_mix is either unconnected or has no load
WARNING: [Synth 8-7129] Port RESET in module jenkins_mix is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:47 ; elapsed = 00:00:59 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 131 ; free virtual = 5310
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 178 ; free virtual = 3189
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
@ -169,13 +165,13 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:56 ; elapsed = 00:01:09 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 175 ; free virtual = 5367
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 121 ; free virtual = 3182
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:01:03 ; elapsed = 00:01:17 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 243 ; free virtual = 5327
Finished Timing Optimization : Time (s): cpu = 00:00:48 ; elapsed = 00:00:50 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 193 ; free virtual = 3161
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
@ -234,7 +230,7 @@ INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/mem
INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:01:07 ; elapsed = 00:01:21 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 381 ; free virtual = 5319
Finished Technology Mapping : Time (s): cpu = 00:00:52 ; elapsed = 00:00:55 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 184 ; free virtual = 3158
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
@ -252,37 +248,55 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:01:16 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189
Finished IO Insertion : Time (s): cpu = 00:01:01 ; elapsed = 00:01:04 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:01:16 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189
Finished Renaming Generated Instances : Time (s): cpu = 00:01:01 ; elapsed = 00:01:04 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:17 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:02 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:01:17 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189
Finished Renaming Generated Ports : Time (s): cpu = 00:01:02 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:01:17 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189
Finished Handling Custom Attributes : Time (s): cpu = 00:01:03 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:01:17 ; elapsed = 00:01:34 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189
Finished Renaming Generated Nets : Time (s): cpu = 00:01:03 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
Static Shift Register Report:
+------------+--------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E |
+------------+--------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
|filter | hash_generate[0].hash/final/s_reg[7][valid] | 13 | 1 | NO | NO | NO | 1 | 0 |
|filter | memory_key_reg[127] | 8 | 32 | NO | NO | YES | 32 | 0 |
|filter | memory_key_reg[95] | 14 | 89 | NO | NO | YES | 89 | 0 |
|filter | memory_key_reg[38] | 13 | 7 | NO | NO | YES | 7 | 0 |
|filter | hash_generate[0].hash/mix_pipeline[0].mix/s_reg[6][key][100] | 7 | 32 | NO | YES | YES | 32 | 0 |
+------------+--------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@ -298,41 +312,41 @@ Report Cell Usage:
+------+---------+------+
| |Cell |Count |
+------+---------+------+
|1 |CARRY4 | 681|
|2 |LUT1 | 228|
|3 |LUT2 | 874|
|4 |LUT3 | 900|
|5 |LUT4 | 260|
|6 |LUT5 | 995|
|7 |LUT6 | 950|
|8 |RAMB18E1 | 4|
|9 |RAMB36E1 | 32|
|10 |FDRE | 563|
|1 |CARRY4 | 745|
|2 |LUT1 | 227|
|3 |LUT2 | 3166|
|4 |LUT3 | 764|
|5 |LUT4 | 4|
|6 |LUT6 | 201|
|7 |RAMB18E1 | 4|
|8 |RAMB36E1 | 32|
|9 |SRL16E | 161|
|10 |FDRE | 4794|
+------+---------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:01:17 ; elapsed = 00:01:34 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 164 ; free virtual = 5187
Finished Writing Synthesis Report : Time (s): cpu = 00:01:03 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 5 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:01:11 ; elapsed = 00:01:26 . Memory (MB): peak = 2252.359 ; gain = 502.434 ; free physical = 148 ; free virtual = 5185
Synthesis Optimization Complete : Time (s): cpu = 00:01:17 ; elapsed = 00:01:34 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 145 ; free virtual = 5184
Synthesis finished with 0 errors, 0 critical warnings and 3 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:57 ; elapsed = 00:01:00 . Memory (MB): peak = 2269.754 ; gain = 504.496 ; free physical = 134 ; free virtual = 3152
Synthesis Optimization Complete : Time (s): cpu = 00:01:03 ; elapsed = 00:01:06 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 134 ; free virtual = 3152
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2252.359 ; gain = 0.000 ; free physical = 115 ; free virtual = 5167
INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement
Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2269.754 ; gain = 0.000 ; free physical = 384 ; free virtual = 3430
INFO: [Netlist 29-17] Analyzing 781 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2252.359 ; gain = 0.000 ; free physical = 313 ; free virtual = 5535
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2269.754 ; gain = 0.000 ; free physical = 311 ; free virtual = 3423
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete | Checksum: d74e1ad3
Synth Design complete | Checksum: 806ce973
INFO: [Common 17-83] Releasing license: Synthesis
66 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered.
66 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:01:33 ; elapsed = 00:01:44 . Memory (MB): peak = 2252.359 ; gain = 977.047 ; free physical = 232 ; free virtual = 5481
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1724.537; main = 1326.676; forked = 397.861
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3235.051; main = 2252.328; forked = 982.723
Write ShapeDB Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2276.336 ; gain = 0.000 ; free physical = 226 ; free virtual = 5482
synth_design: Time (s): cpu = 00:01:18 ; elapsed = 00:01:16 . Memory (MB): peak = 2269.754 ; gain = 978.141 ; free physical = 301 ; free virtual = 3421
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1616.477; main = 1400.213; forked = 417.991
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3233.605; main = 2269.723; forked = 963.883
Write ShapeDB Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2269.754 ; gain = 0.000 ; free physical = 297 ; free virtual = 3420
INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/filter.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file filter_utilization_synth.rpt -pb filter_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 18:50:06 2023...
INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 21:15:58 2023...

6
synth/filter_vivado.runs/synth_1/vivado.jou
View File

@ -3,12 +3,12 @@
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Sun Dec 3 18:47:59 2023
# Process ID: 18749
# Start of session at: Sun Dec 3 21:14:16 2023
# Process ID: 50094
# Current directory: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1
# Command line: vivado -log filter.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source filter.tcl
# Log file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/filter.vds
# Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/vivado.jou
# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 3075.336 MHz, CPU Physical cores: 4, Host memory: 3903 MB
# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2783.625 MHz, CPU Physical cores: 4, Host memory: 3903 MB
#-----------------------------------------------------------
source filter.tcl -notrace

BIN
synth/filter_vivado.runs/synth_1/vivado.pb
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Binary file not shown.

20
synth/filter_vivado.xpr
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@ -223,7 +223,7 @@
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023" CtrlBit="true">
<ReportConfig DisplayName="Timing Summary - Design Initialization" Name="impl_1_init_report_timing_summary_0" Spec="report_timing_summary" RunStep="init_design" ReportFile="filter_timing_summary_init.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfig DisplayName="Timing Summary - Design Initialization" Name="impl_1_init_report_timing_summary_0" Spec="report_timing_summary" RunStep="init_design" ReportFile="filter_timing_summary_init_1.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
@ -240,7 +240,7 @@
<ReportConfigOutputOption Name="pb" Type="string" Value="filter_timing_summary_opted.pb"/>
<ReportConfigOutputOption Name="rpx" Type="string" Value="filter_timing_summary_opted.rpx"/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Power Opt Design" Name="impl_1_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="power_opt_design" ReportFile="filter_timing_summary_pwropted.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfig DisplayName="Timing Summary - Power Opt Design" Name="impl_1_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="power_opt_design" ReportFile="filter_timing_summary_pwropted_1.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
@ -256,25 +256,25 @@
<ReportConfig DisplayName="Control Sets - Place Design" Name="impl_1_place_report_control_sets_0" Spec="report_control_sets" RunStep="place_design" ReportFile="filter_control_sets_placed.rpt" Version="1" Minor="0">
<ReportConfigOption Name="verbose" Type="" Value="true"/>
</ReportConfig>
<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_place_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="filter_incremental_reuse_pre_placed.rpt.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_place_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="filter_incremental_reuse_pre_placed.rpt_1.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_place_report_incremental_reuse_1" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="filter_incremental_reuse_placed.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_place_report_incremental_reuse_1" Spec="report_incremental_reuse" RunStep="place_design" ReportFile="filter_incremental_reuse_placed_1.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Place Design" Name="impl_1_place_report_timing_summary_0" Spec="report_timing_summary" RunStep="place_design" ReportFile="filter_timing_summary_placed.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfig DisplayName="Timing Summary - Place Design" Name="impl_1_place_report_timing_summary_0" Spec="report_timing_summary" RunStep="place_design" ReportFile="filter_timing_summary_placed_1.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Post-Place Power Opt Design" Name="impl_1_post_place_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_place_power_opt_design" ReportFile="filter_timing_summary_postplace_pwropted.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfig DisplayName="Timing Summary - Post-Place Power Opt Design" Name="impl_1_post_place_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_place_power_opt_design" ReportFile="filter_timing_summary_postplace_pwropted_1.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Post-Place Phys Opt Design" Name="impl_1_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="phys_opt_design" ReportFile="filter_timing_summary_physopted.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfig DisplayName="Timing Summary - Post-Place Phys Opt Design" Name="impl_1_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="phys_opt_design" ReportFile="filter_timing_summary_physopted_1.rpt" Version="1" Minor="0" IsDisabled="true">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
@ -319,19 +319,19 @@
<ReportConfig DisplayName="implementation_log" Name="impl_1_route_implementation_log_0" Spec="" RunStep="route_design" ReportFile="filter.vdi">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
<ReportConfig DisplayName="Timing Summary - Post-Route Phys Opt Design" Name="impl_1_post_route_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_route_phys_opt_design" ReportFile="filter_timing_summary_postroute_physopted.rpt" Version="1" Minor="0">
<ReportConfig DisplayName="Timing Summary - Post-Route Phys Opt Design" Name="impl_1_post_route_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_route_phys_opt_design" ReportFile="filter_timing_summary_postroute_physopted_1.rpt" Version="1" Minor="0">
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="Bus Skew - Post-Route Phys Opt Design" Name="impl_1_post_route_phys_opt_report_bus_skew_0" Spec="report_bus_skew" RunStep="post_route_phys_opt_design" ReportFile="filter_bus_skew_postroute_physopted.rpt" Version="1" Minor="1">
<ReportConfig DisplayName="Bus Skew - Post-Route Phys Opt Design" Name="impl_1_post_route_phys_opt_report_bus_skew_0" Spec="report_bus_skew" RunStep="post_route_phys_opt_design" ReportFile="filter_bus_skew_postroute_physopted_1.rpt" Version="1" Minor="1">
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
</ReportConfig>
<ReportConfig DisplayName="implementation_log" Name="impl_1_bitstream_implementation_log_0" Spec="" RunStep="write_bitstream" ReportFile="filter.vdi">
<ReportConfig DisplayName="implementation_log" Name="impl_1_bitstream_implementation_log_0" Spec="" RunStep="write_bitstream">
<ReportConfigOption Name="dummy_option" Type="string"/>
</ReportConfig>
</ReportStrategy>

50
vivado.jou Normal file
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@ -0,0 +1,50 @@
#-----------------------------------------------------------
# Vivado v2023.2 (64-bit)
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Sun Dec 3 19:35:56 2023
# Process ID: 27830
# Current directory: /home/veronikaplevacova/Plocha/PCS2
# Command line: vivado
# Log file: /home/veronikaplevacova/Plocha/PCS2/vivado.log
# Journal file: /home/veronikaplevacova/Plocha/PCS2/vivado.jou
# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2785.863 MHz, CPU Physical cores: 4, Host memory: 3903 MB
#-----------------------------------------------------------
start_gui
open_project /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.xpr
update_compile_order -fileset sources_1
open_run impl_1
reset_run synth_1
launch_runs synth_1 -jobs 2
wait_on_run synth_1
launch_runs impl_1 -jobs 2
wait_on_run impl_1
reset_run synth_1
launch_runs impl_1 -jobs 2
wait_on_run impl_1
refresh_design
open_run synth_1 -name synth_1
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
current_design impl_1
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
reset_run synth_1
launch_runs impl_1 -jobs 2
wait_on_run impl_1
current_design synth_1
refresh_design
current_design impl_1
current_design synth_1
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
reset_run synth_1
launch_runs impl_1 -jobs 2
wait_on_run impl_1
reset_run synth_1
launch_runs impl_1 -jobs 2
wait_on_run impl_1
report_power -name {power_1}
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_2
reset_run synth_1
launch_runs impl_1 -jobs 2
wait_on_run impl_1
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_3

342
vivado.log Normal file
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@ -0,0 +1,342 @@
#-----------------------------------------------------------
# Vivado v2023.2 (64-bit)
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Sun Dec 3 19:35:56 2023
# Process ID: 27830
# Current directory: /home/veronikaplevacova/Plocha/PCS2
# Command line: vivado
# Log file: /home/veronikaplevacova/Plocha/PCS2/vivado.log
# Journal file: /home/veronikaplevacova/Plocha/PCS2/vivado.jou
# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2785.863 MHz, CPU Physical cores: 4, Host memory: 3903 MB
#-----------------------------------------------------------
start_gui
open_project /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.xpr
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.4 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.4/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.5 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.5/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.1/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.2 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.1/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/production/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.2 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.1/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.2 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.1/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc702:part0:1.4 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc702/1.4/board.xml as part xc7z020clg484-1 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu104:part0:1.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu104/1.1/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu106:part0:2.4 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu106/2.4/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu106:part0:2.5 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu106/2.5/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu106:part0:2.6 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu106/2.6/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available
WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available
INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.gen/sources_1'.
Scanning sources...
Finished scanning sources
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2023.2/data/ip'.
open_project: Time (s): cpu = 00:00:33 ; elapsed = 00:00:18 . Memory (MB): peak = 7745.375 ; gain = 351.125 ; free physical = 110 ; free virtual = 9678
update_compile_order -fileset sources_1
open_run impl_1
INFO: [Device 21-403] Loading part xc7k160tffv676-1
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 8166.188 ; gain = 0.000 ; free physical = 131 ; free virtual = 9488
INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Read ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 8235.938 ; gain = 0.000 ; free physical = 110 ; free virtual = 9407
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
INFO: [Designutils 20-5722] Start Reading Physical Databases.
Reading placement.
Read Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 8819.555 ; gain = 0.000 ; free physical = 133 ; free virtual = 8851
Reading placer database...
Read Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 8819.555 ; gain = 0.000 ; free physical = 132 ; free virtual = 8851
Read PlaceDB: Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.39 . Memory (MB): peak = 8819.555 ; gain = 0.000 ; free physical = 232 ; free virtual = 8852
Read PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 8819.555 ; gain = 0.000 ; free physical = 232 ; free virtual = 8852
Reading routing.
Read RouteStorage: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.26 . Memory (MB): peak = 8829.555 ; gain = 10.000 ; free physical = 230 ; free virtual = 8851
Read Physdb Files: Time (s): cpu = 00:00:00.71 ; elapsed = 00:00:00.69 . Memory (MB): peak = 8829.555 ; gain = 10.000 ; free physical = 230 ; free virtual = 8851
Restored from archive | CPU: 0.720000 secs | Memory: 7.179550 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00.71 ; elapsed = 00:00:00.69 . Memory (MB): peak = 8829.555 ; gain = 10.000 ; free physical = 230 ; free virtual = 8851
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 8829.555 ; gain = 0.000 ; free physical = 224 ; free virtual = 8849
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
open_run: Time (s): cpu = 00:00:38 ; elapsed = 00:00:27 . Memory (MB): peak = 9065.062 ; gain = 1229.688 ; free physical = 219 ; free virtual = 8715
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
reset_run synth_1
launch_runs synth_1 -jobs 2
WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead.
[Sun Dec 3 19:45:29 2023] Launched synth_1...
Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/runme.log
launch_runs impl_1 -jobs 2
[Sun Dec 3 19:47:42 2023] Launched impl_1...
Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/runme.log
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
reset_run synth_1
launch_runs impl_1 -jobs 2
[Sun Dec 3 20:03:31 2023] Launched synth_1...
Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/runme.log
[Sun Dec 3 20:03:31 2023] Launched impl_1...
Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/runme.log
refresh_design
Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.06 . Memory (MB): peak = 9231.645 ; gain = 0.000 ; free physical = 1096 ; free virtual = 7869
INFO: [Netlist 29-17] Analyzing 781 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Read ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 9231.645 ; gain = 0.000 ; free physical = 1068 ; free virtual = 7860
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
INFO: [Designutils 20-5722] Start Reading Physical Databases.
Reading placement.
Read Netlist Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 9231.645 ; gain = 0.000 ; free physical = 1012 ; free virtual = 7830
Reading placer database...
Read Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 9231.645 ; gain = 0.000 ; free physical = 1012 ; free virtual = 7830
Read PlaceDB: Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.45 . Memory (MB): peak = 9231.645 ; gain = 0.000 ; free physical = 1009 ; free virtual = 7827
Read PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9231.645 ; gain = 0.000 ; free physical = 1009 ; free virtual = 7827
Reading routing.
Read RouteStorage: Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.38 . Memory (MB): peak = 9231.645 ; gain = 0.000 ; free physical = 983 ; free virtual = 7801
Read Physdb Files: Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.87 . Memory (MB): peak = 9231.645 ; gain = 0.000 ; free physical = 983 ; free virtual = 7801
Restored from archive | CPU: 0.860000 secs | Memory: 7.690048 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.87 . Memory (MB): peak = 9231.645 ; gain = 0.000 ; free physical = 983 ; free virtual = 7801
refresh_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 9259.844 ; gain = 28.199 ; free physical = 832 ; free virtual = 7777
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
open_run synth_1 -name synth_1
Design is defaulting to impl run constrset: constrs_1
Design is defaulting to synth run part: xc7k160tffv676-1
Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 9262.000 ; gain = 0.000 ; free physical = 721 ; free virtual = 7688
INFO: [Netlist 29-17] Analyzing 781 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc]
WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13]
Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9262.000 ; gain = 0.000 ; free physical = 652 ; free virtual = 7618
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13]
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
current_design impl_1
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
reset_run synth_1
launch_runs impl_1 -jobs 2
WARNING: [Project 1-478] Design 'synth_1' is stale and will not be used when launching 'impl_1'
[Sun Dec 3 20:21:41 2023] Launched synth_1...
Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/runme.log
[Sun Dec 3 20:21:42 2023] Launched impl_1...
Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/runme.log
current_design synth_1
refresh_design
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 9646.148 ; gain = 0.000 ; free physical = 1181 ; free virtual = 7483
INFO: [Netlist 29-17] Analyzing 781 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc]
WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13]
Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
refresh_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 9646.148 ; gain = 5.934 ; free physical = 1046 ; free virtual = 7480
current_design impl_1
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
current_design synth_1
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13]
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
reset_run synth_1
launch_runs impl_1 -jobs 2
WARNING: [Project 1-478] Design 'synth_1' is stale and will not be used when launching 'impl_1'
[Sun Dec 3 20:41:40 2023] Launched synth_1...
Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/runme.log
[Sun Dec 3 20:41:40 2023] Launched impl_1...
Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/runme.log
reset_run synth_1
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
launch_runs impl_1 -jobs 2
WARNING: [Project 1-478] Design 'synth_1' is stale and will not be used when launching 'impl_1'
[Sun Dec 3 20:44:09 2023] Launched synth_1...
Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/runme.log
[Sun Dec 3 20:44:09 2023] Launched impl_1...
Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/runme.log
report_power -name {power_1}
Command: report_power -name power_1
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_2
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:]
WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:]
reset_run synth_1
launch_runs impl_1 -jobs 2
WARNING: [Project 1-478] Design 'synth_1' is stale and will not be used when launching 'impl_1'
[Sun Dec 3 21:14:11 2023] Launched synth_1...
Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/runme.log
[Sun Dec 3 21:14:12 2023] Launched impl_1...
Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/runme.log
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_3
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
exit
INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 21:22:03 2023...