diff --git a/Makefile b/Makefile index f7e41b0..0bd085a 100644 --- a/Makefile +++ b/Makefile @@ -1,3 +1,6 @@ +run: + /tools/Xilinx/Vivado/2023.2/bin/vivado + build: cd synth && \ /tools/Xilinx/Vivado/2023.2/bin/vivado -mode batch -source filter.tcl diff --git a/comp/block_memory.vhd b/comp/block_memory.vhd index 4615264..ae98d6c 100644 --- a/comp/block_memory.vhd +++ b/comp/block_memory.vhd @@ -48,6 +48,9 @@ architecture behavioral of block_memory is signal memory : memory_type; signal memory_data : std_logic_vector(ITEM_WIDTH-1 downto 0); signal memory_data_valid : std_logic; + + attribute ramstyle : string; + attribute ramstyle of memory : signal is "M20K"; begin diff --git a/comp/jenkins_final.vhd b/comp/jenkins_final.vhd index bf5ff3f..51783c5 100644 --- a/comp/jenkins_final.vhd +++ b/comp/jenkins_final.vhd @@ -69,54 +69,88 @@ begin s(0).valid <= INPUT_VALID; -- Stage 1: c ^= b; c -= rot(b,14); - s(1).a <= s(0).a; - s(1).b <= s(0).b; - s(1).c <= (s(0).c xor s(0).b) - rot(s(0).b, 14); - s(1).key <= s(0).key; - s(1).valid <= s(0).valid; + stage1_p : process ( clk ) is + begin + if rising_edge ( clk ) then + s(1).a <= s(0).a; + s(1).b <= s(0).b; + s(1).c <= (s(0).c xor s(0).b) - rot(s(0).b, 14); + s(1).key <= s(0).key; + s(1).valid <= s(0).valid; + end if; + end process; -- Stage 2: a ^= c; a -= rot(c,11); - s(2).a <= (s(1).a xor s(1).c) - rot(s(1).c, 11); - s(2).b <= s(1).b; - s(2).c <= s(1).c; - s(2).key <= s(1).key; - s(2).valid <= s(1).valid; - + stage2_p : process ( clk ) is + begin + if rising_edge ( clk ) then + s(2).a <= (s(1).a xor s(1).c) - rot(s(1).c, 11); + s(2).b <= s(1).b; + s(2).c <= s(1).c; + s(2).key <= s(1).key; + s(2).valid <= s(1).valid; + end if; + end process; -- Stage 3: b ^= a; b -= rot(a,25); - s(3).a <= s(2).a; - s(3).b <= (s(2).b xor s(2).a) - rot(s(2).a, 25); - s(3).c <= s(2).c; - s(3).key <= s(2).key; - s(3).valid <= s(2).valid; + stage3_p : process ( clk ) is + begin + if rising_edge ( clk ) then + s(3).a <= s(2).a; + s(3).b <= (s(2).b xor s(2).a) - rot(s(2).a, 25); + s(3).c <= s(2).c; + s(3).key <= s(2).key; + s(3).valid <= s(2).valid; + end if; + end process; -- Stage 4: c ^= b; c -= rot(b,16); - s(4).a <= s(3).a; - s(4).b <= s(3).b; - s(4).c <= (s(3).c xor s(3).b) - rot(s(3).b, 16); - s(4).key <= s(3).key; - s(4).valid <= s(3).valid; + stage4_p : process ( clk ) is + begin + if rising_edge ( clk ) then + s(4).a <= s(3).a; + s(4).b <= s(3).b; + s(4).c <= (s(3).c xor s(3).b) - rot(s(3).b, 16); + s(4).key <= s(3).key; + s(4).valid <= s(3).valid; + end if; + end process; -- Stage 5: a ^= c; a -= rot(c,4); - s(5).a <= (s(4).a xor s(4).c) - rot(s(4).c, 4); - s(5).b <= s(4).b; - s(5).c <= s(4).c; - s(5).key <= s(4).key; - s(5).valid <= s(4).valid; + stage5_p : process ( clk ) is + begin + if rising_edge ( clk ) then + s(5).a <= (s(4).a xor s(4).c) - rot(s(4).c, 4); + s(5).b <= s(4).b; + s(5).c <= s(4).c; + s(5).key <= s(4).key; + s(5).valid <= s(4).valid; + end if; + end process; -- Stage 6: b ^= a; b -= rot(a,14); - s(6).a <= s(5).a; - s(6).b <= (s(5).b xor s(5).a) - rot(s(5).a, 14); - s(6).c <= s(5).c; - s(6).key <= s(5).key; - s(6).valid <= s(5).valid; + stage6_p : process ( clk ) is + begin + if rising_edge ( clk ) then + s(6).a <= s(5).a; + s(6).b <= (s(5).b xor s(5).a) - rot(s(5).a, 14); + s(6).c <= s(5).c; + s(6).key <= s(5).key; + s(6).valid <= s(5).valid; + end if; + end process; -- Stage 7: c ^= b; c -= rot(b,24); - s(7).a <= s(6).a; - s(7).b <= s(6).b; - s(7).c <= (s(6).c xor s(6).b) - rot(s(6).b, 24); - s(7).key <= s(6).key; - s(7).valid <= s(6).valid; + stage7_p : process ( clk ) is + begin + if rising_edge ( clk ) then + s(7).a <= s(6).a; + s(7).b <= s(6).b; + s(7).c <= (s(6).c xor s(6).b) - rot(s(6).b, 24); + s(7).key <= s(6).key; + s(7).valid <= s(6).valid; + end if; + end process; -- Output connections OUTPUT_A <= s(STAGES).a; diff --git a/comp/jenkins_mix.vhd b/comp/jenkins_mix.vhd index da272af..6b5df9f 100644 --- a/comp/jenkins_mix.vhd +++ b/comp/jenkins_mix.vhd @@ -68,47 +68,78 @@ begin s(0).key <= INPUT_KEY; s(0).valid <= INPUT_VALID; + -- Stage 1: a -= c; a ^= rot(c, 4); c += b; - s(1).a <= (s(0).a - s(0).c) xor rot(s(0).c, 4); - s(1).b <= s(0).b; - s(1).c <= s(0).c + s(0).b; - s(1).key <= s(0).key; - s(1).valid <= s(0).valid; + stage1_p : process ( clk ) is + begin + if rising_edge ( clk ) then + s(1).a <= (s(0).a - s(0).c) xor rot(s(0).c, 4); + s(1).b <= s(0).b; + s(1).c <= s(0).c + s(0).b; + s(1).key <= s(0).key; + s(1).valid <= s(0).valid; + end if; + end process; -- Stage 2: b -= a; b ^= rot(a, 6); a += c; - s(2).a <= s(1).a + s(1).c; - s(2).b <= (s(1).b - s(1).a) xor rot(s(1).a, 6); - s(2).c <= s(1).c; - s(2).key <= s(1).key; - s(2).valid <= s(1).valid; + stage2_p : process ( clk ) is + begin + if rising_edge ( clk ) then + s(2).a <= s(1).a + s(1).c; + s(2).b <= (s(1).b - s(1).a) xor rot(s(1).a, 6); + s(2).c <= s(1).c; + s(2).key <= s(1).key; + s(2).valid <= s(1).valid; + end if; + end process; -- Stage 3: c -= b; c ^= rot(b, 8); b += a; - s(3).a <= s(2).a; - s(3).b <= s(2).b + s(2).a; - s(3).c <= (s(2).c - s(2).b) xor rot(s(2).b, 8); - s(3).key <= s(2).key; - s(3).valid <= s(2).valid; + stage3_p : process ( clk ) is + begin + if rising_edge ( clk ) then + s(3).a <= s(2).a; + s(3).b <= s(2).b + s(2).a; + s(3).c <= (s(2).c - s(2).b) xor rot(s(2).b, 8); + s(3).key <= s(2).key; + s(3).valid <= s(2).valid; + end if; + end process; -- Stage 4: a -= c; a ^= rot(c,16); c += b; - s(4).a <= (s(3).a - s(3).c) xor rot(s(3).c, 16); - s(4).b <= s(3).b; - s(4).c <= s(3).c + s(3).b; - s(4).key <= s(3).key; - s(4).valid <= s(3).valid; + stage4_p : process ( clk ) is + begin + if rising_edge ( clk ) then + s(4).a <= (s(3).a - s(3).c) xor rot(s(3).c, 16); + s(4).b <= s(3).b; + s(4).c <= s(3).c + s(3).b; + s(4).key <= s(3).key; + s(4).valid <= s(3).valid; + end if; + end process; -- Stage 5: b -= a; b ^= rot(a,19); a += c; - s(5).a <= s(4).a + s(4).c; - s(5).b <= (s(4).b - s(4).a) xor rot(s(4).a, 19); - s(5).c <= s(4).c; - s(5).key <= s(4).key; - s(5).valid <= s(4).valid; - + stage5_p : process ( clk ) is + begin + if rising_edge ( clk ) then + s(5).a <= s(4).a + s(4).c; + s(5).b <= (s(4).b - s(4).a) xor rot(s(4).a, 19); + s(5).c <= s(4).c; + s(5).key <= s(4).key; + s(5).valid <= s(4).valid; + end if; + end process; + -- Stage 6: c -= b; c ^= rot(b, 4); b += a; - s(6).a <= s(5).a; - s(6).b <= s(5).b + s(5).a; - s(6).c <= (s(5).c - s(5).b) xor rot(s(5).b, 4); - s(6).key <= s(5).key; - s(6).valid <= s(5).valid; + stage6_p : process ( clk ) is + begin + if rising_edge ( clk ) then + s(6).a <= s(5).a; + s(6).b <= s(5).b + s(5).a; + s(6).c <= (s(5).c - s(5).b) xor rot(s(5).b, 4); + s(6).key <= s(5).key; + s(6).valid <= s(5).valid; + end if; + end process; -- Output connections OUTPUT_A <= s(STAGES).a; diff --git a/synth/filter_vivado.cache/wt/project.wpc b/synth/filter_vivado.cache/wt/project.wpc index e3a38cb..e62d4b7 100644 --- a/synth/filter_vivado.cache/wt/project.wpc +++ b/synth/filter_vivado.cache/wt/project.wpc @@ -1,4 +1,4 @@ version:1 6d6f64655f636f756e7465727c42617463684d6f6465:1 -6d6f64655f636f756e7465727c4755494d6f6465:1 +6d6f64655f636f756e7465727c4755494d6f6465:2 eof: diff --git a/synth/filter_vivado.cache/wt/synthesis.wdf b/synth/filter_vivado.cache/wt/synthesis.wdf index 6cc8ac4..6737eb1 100644 --- a/synth/filter_vivado.cache/wt/synthesis.wdf +++ b/synth/filter_vivado.cache/wt/synthesis.wdf @@ -45,7 +45,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a323273:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323235322e3335394d42:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3937312e3130394d42:00:00 -eof:55709678 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a303873:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323236392e3735344d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3937342e3137324d42:00:00 +eof:920102437 diff --git a/synth/filter_vivado.cache/wt/webtalk_pa.xml b/synth/filter_vivado.cache/wt/webtalk_pa.xml index cf5b2c4..c1cd68b 100644 --- a/synth/filter_vivado.cache/wt/webtalk_pa.xml +++ b/synth/filter_vivado.cache/wt/webtalk_pa.xml @@ -3,10 +3,10 @@ - +
- +
diff --git a/synth/filter_vivado.runs/.jobs/vrs_config_10.xml b/synth/filter_vivado.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000..7bc15ab --- /dev/null +++ b/synth/filter_vivado.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/synth/filter_vivado.runs/.jobs/vrs_config_4.xml b/synth/filter_vivado.runs/.jobs/vrs_config_4.xml new file mode 100644 index 0000000..e8978b9 --- /dev/null +++ b/synth/filter_vivado.runs/.jobs/vrs_config_4.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/synth/filter_vivado.runs/.jobs/vrs_config_5.xml b/synth/filter_vivado.runs/.jobs/vrs_config_5.xml new file mode 100644 index 0000000..5aaf564 --- /dev/null +++ b/synth/filter_vivado.runs/.jobs/vrs_config_5.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/synth/filter_vivado.runs/.jobs/vrs_config_6.xml b/synth/filter_vivado.runs/.jobs/vrs_config_6.xml new file mode 100644 index 0000000..7bc15ab --- /dev/null +++ b/synth/filter_vivado.runs/.jobs/vrs_config_6.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/synth/filter_vivado.runs/.jobs/vrs_config_7.xml b/synth/filter_vivado.runs/.jobs/vrs_config_7.xml new file mode 100644 index 0000000..7bc15ab --- /dev/null +++ b/synth/filter_vivado.runs/.jobs/vrs_config_7.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/synth/filter_vivado.runs/.jobs/vrs_config_8.xml b/synth/filter_vivado.runs/.jobs/vrs_config_8.xml new file mode 100644 index 0000000..7bc15ab --- /dev/null +++ b/synth/filter_vivado.runs/.jobs/vrs_config_8.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/synth/filter_vivado.runs/.jobs/vrs_config_9.xml b/synth/filter_vivado.runs/.jobs/vrs_config_9.xml new file mode 100644 index 0000000..7bc15ab --- /dev/null +++ b/synth/filter_vivado.runs/.jobs/vrs_config_9.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + + + diff --git a/synth/filter_vivado.runs/impl_1/.init_design.begin.rst b/synth/filter_vivado.runs/impl_1/.init_design.begin.rst index bfc0a2a..49614e7 100644 --- a/synth/filter_vivado.runs/impl_1/.init_design.begin.rst +++ b/synth/filter_vivado.runs/impl_1/.init_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/synth/filter_vivado.runs/impl_1/.opt_design.begin.rst b/synth/filter_vivado.runs/impl_1/.opt_design.begin.rst index bfc0a2a..49614e7 100644 --- a/synth/filter_vivado.runs/impl_1/.opt_design.begin.rst +++ b/synth/filter_vivado.runs/impl_1/.opt_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/synth/filter_vivado.runs/impl_1/.phys_opt_design.begin.rst b/synth/filter_vivado.runs/impl_1/.phys_opt_design.begin.rst index bfc0a2a..49614e7 100644 --- a/synth/filter_vivado.runs/impl_1/.phys_opt_design.begin.rst +++ b/synth/filter_vivado.runs/impl_1/.phys_opt_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/synth/filter_vivado.runs/impl_1/.place_design.begin.rst b/synth/filter_vivado.runs/impl_1/.place_design.begin.rst index bfc0a2a..49614e7 100644 --- a/synth/filter_vivado.runs/impl_1/.place_design.begin.rst +++ b/synth/filter_vivado.runs/impl_1/.place_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/synth/filter_vivado.runs/impl_1/.route_design.begin.rst b/synth/filter_vivado.runs/impl_1/.route_design.begin.rst index bfc0a2a..49614e7 100644 --- a/synth/filter_vivado.runs/impl_1/.route_design.begin.rst +++ b/synth/filter_vivado.runs/impl_1/.route_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/synth/filter_vivado.runs/impl_1/.vivado.begin.rst b/synth/filter_vivado.runs/impl_1/.vivado.begin.rst index f4c6d0f..606668e 100644 --- a/synth/filter_vivado.runs/impl_1/.vivado.begin.rst +++ b/synth/filter_vivado.runs/impl_1/.vivado.begin.rst @@ -1,5 +1,25 @@ - + + + + + + + + + + + + + + + + + + + + + diff --git a/synth/filter_vivado.runs/impl_1/clockInfo.txt b/synth/filter_vivado.runs/impl_1/clockInfo.txt index f348b00..c667fb8 100644 --- a/synth/filter_vivado.runs/impl_1/clockInfo.txt +++ b/synth/filter_vivado.runs/impl_1/clockInfo.txt @@ -1,6 +1,6 @@ ------------------------------------- | Tool Version : Vivado v.2023.2 -| Date : Sun Dec 3 18:52:50 2023 +| Date : Sun Dec 3 21:17:35 2023 | Host : veronika-swiftsf11433 | Design : design_1 | Device : xc7k160t-ffv676-1-- diff --git a/synth/filter_vivado.runs/impl_1/filter.tcl b/synth/filter_vivado.runs/impl_1/filter.tcl index 697b993..2f30b49 100644 --- a/synth/filter_vivado.runs/impl_1/filter.tcl +++ b/synth/filter_vivado.runs/impl_1/filter.tcl @@ -115,8 +115,6 @@ proc step_failed { step } { OPTRACE "impl_1" END { } } -set_msg_config -id {Synth 8-256} -limit 10000 -set_msg_config -id {Synth 8-638} -limit 10000 OPTRACE "impl_1" START { ROLLUP_1 } OPTRACE "Phase: Init Design" START { ROLLUP_AUTO } @@ -125,8 +123,6 @@ set ACTIVE_STEP init_design set rc [catch { create_msg_db init_design.pb set_param chipscope.maxJobs 1 - set_param checkpoint.writeSynthRtdsInDcp 1 - set_param synth.incrementalSynthesisCache /tmp/.Xil_veronikaplevacova/Vivado-18297-veronika-swiftsf11433/incrSyn set_param runs.launchOptions { -jobs 2 } OPTRACE "create in-memory project" START { } create_project -in_memory -part xc7k160tffv676-1 @@ -148,7 +144,7 @@ OPTRACE "read constraints: implementation_pre" START { } OPTRACE "read constraints: implementation_pre" END { } OPTRACE "add files" END { } OPTRACE "link_design" START { } - link_design -top filter -part xc7k160tffv676-1 -mode out_of_context + link_design -top filter -part xc7k160tffv676-1 OPTRACE "link_design" END { } OPTRACE "gray box cells" START { } OPTRACE "gray box cells" END { } @@ -181,6 +177,7 @@ OPTRACE "read constraints: opt_design_post" START { } OPTRACE "read constraints: opt_design_post" END { } OPTRACE "opt_design reports" START { REPORT } create_report "impl_1_opt_report_drc_0" "report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx" + create_report "impl_1_opt_report_timing_summary_0" "report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_opted.rpt -pb filter_timing_summary_opted.pb -rpx filter_timing_summary_opted.rpx" OPTRACE "opt_design reports" END { } OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT } write_checkpoint -force filter_opt.dcp diff --git a/synth/filter_vivado.runs/impl_1/filter.vdi b/synth/filter_vivado.runs/impl_1/filter.vdi index 5a1e705..d8fa3db 100644 --- a/synth/filter_vivado.runs/impl_1/filter.vdi +++ b/synth/filter_vivado.runs/impl_1/filter.vdi @@ -3,22 +3,22 @@ # SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Sun Dec 3 18:51:36 2023 -# Process ID: 19329 +# Start of session at: Sun Dec 3 21:16:13 2023 +# Process ID: 50397 # Current directory: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1 # Command line: vivado -log filter.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source filter.tcl -notrace # Log file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter.vdi # Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/vivado.jou -# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2785.745 MHz, CPU Physical cores: 4, Host memory: 3903 MB +# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2785.806 MHz, CPU Physical cores: 4, Host memory: 3903 MB #----------------------------------------------------------- source filter.tcl -notrace -create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.508 ; gain = 0.023 ; free physical = 106 ; free virtual = 6598 -Command: link_design -top filter -part xc7k160tffv676-1 -mode out_of_context +create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1271.086 ; gain = 13.898 ; free physical = 453 ; free virtual = 4400 +Command: link_design -top filter -part xc7k160tffv676-1 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7k160tffv676-1 -Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1630.383 ; gain = 0.000 ; free physical = 131 ; free virtual = 6415 -INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement +Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1630.898 ; gain = 0.000 ; free physical = 245 ; free virtual = 4101 +INFO: [Netlist 29-17] Analyzing 781 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2023.2 INFO: [Project 1-570] Preparing netlist for logic optimization @@ -26,13 +26,13 @@ Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1767.770 ; gain = 0.000 ; free physical = 122 ; free virtual = 6282 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1749.242 ; gain = 0.000 ; free physical = 141 ; free virtual = 4005 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 7 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully -link_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1773.742 ; gain = 465.234 ; free physical = 114 ; free virtual = 6277 +link_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1752.246 ; gain = 481.160 ; free physical = 201 ; free virtual = 4001 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' @@ -43,111 +43,111 @@ INFO: [DRC 23-27] Running DRC with 4 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1824.535 ; gain = 50.793 ; free physical = 205 ; free virtual = 6272 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1801.070 ; gain = 48.824 ; free physical = 184 ; free virtual = 3988 Starting Cache Timing Information Task WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 10236edc4 +Ending Cache Timing Information Task | Checksum: b84391e5 -Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2345.418 ; gain = 520.883 ; free physical = 117 ; free virtual = 5807 +Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2321.945 ; gain = 520.875 ; free physical = 131 ; free virtual = 3537 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup -Phase 1.1 Core Generation And Design Setup | Checksum: 10236edc4 +Phase 1.1 Core Generation And Design Setup | Checksum: b84391e5 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 146 ; free virtual = 5487 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2627.750 ; gain = 0.000 ; free physical = 138 ; free virtual = 3239 Phase 1.2 Setup Constraints And Sort Netlist -Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 10236edc4 +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: b84391e5 -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 145 ; free virtual = 5487 -Phase 1 Initialization | Checksum: 10236edc4 +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2627.750 ; gain = 0.000 ; free physical = 139 ; free virtual = 3239 +Phase 1 Initialization | Checksum: b84391e5 -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 145 ; free virtual = 5487 +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2627.750 ; gain = 0.000 ; free physical = 139 ; free virtual = 3239 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update -Phase 2.1 Timer Update | Checksum: 10236edc4 +Phase 2.1 Timer Update | Checksum: b84391e5 -Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 138 ; free virtual = 5486 +Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2627.750 ; gain = 0.000 ; free physical = 144 ; free virtual = 3235 Phase 2.2 Timing Data Collection -Phase 2.2 Timing Data Collection | Checksum: 10236edc4 +Phase 2.2 Timing Data Collection | Checksum: b84391e5 -Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 137 ; free virtual = 5486 -Phase 2 Timer Update And Timing Data Collection | Checksum: 10236edc4 +Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2627.750 ; gain = 0.000 ; free physical = 139 ; free virtual = 3233 +Phase 2 Timer Update And Timing Data Collection | Checksum: b84391e5 -Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 137 ; free virtual = 5486 +Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2627.750 ; gain = 0.000 ; free physical = 139 ; free virtual = 3233 Phase 3 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 3 Retarget | Checksum: 10c3daf90 +Phase 3 Retarget | Checksum: 9b15171f -Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 134 ; free virtual = 5484 -Retarget | Checksum: 10c3daf90 +Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.61 . Memory (MB): peak = 2627.750 ; gain = 0.000 ; free physical = 122 ; free virtual = 3229 +Retarget | Checksum: 9b15171f INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 4 Constant propagation | Checksum: 9bde81ac +Phase 4 Constant propagation | Checksum: 11aad8966 -Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 132 ; free virtual = 5484 -Constant propagation | Checksum: 9bde81ac +Time (s): cpu = 00:00:00.87 ; elapsed = 00:00:00.73 . Memory (MB): peak = 2627.750 ; gain = 0.000 ; free physical = 130 ; free virtual = 3228 +Constant propagation | Checksum: 11aad8966 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep -Phase 5 Sweep | Checksum: f9b192b3 +Phase 5 Sweep | Checksum: 90bb4c32 -Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 115 ; free virtual = 5482 -Sweep | Checksum: f9b192b3 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.96 . Memory (MB): peak = 2627.750 ; gain = 0.000 ; free physical = 133 ; free virtual = 3226 +Sweep | Checksum: 90bb4c32 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells Phase 6 BUFG optimization -Phase 6 BUFG optimization | Checksum: f9b192b3 +Phase 6 BUFG optimization | Checksum: 90bb4c32 -Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.66 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 115 ; free virtual = 5482 -BUFG optimization | Checksum: f9b192b3 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2659.766 ; gain = 32.016 ; free physical = 133 ; free virtual = 3226 +BUFG optimization | Checksum: 90bb4c32 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs -Phase 7 Shift Register Optimization | Checksum: f9b192b3 +Phase 7 Shift Register Optimization | Checksum: 90bb4c32 -Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 115 ; free virtual = 5482 -Shift Register Optimization | Checksum: f9b192b3 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2659.766 ; gain = 32.016 ; free physical = 133 ; free virtual = 3226 +Shift Register Optimization | Checksum: 90bb4c32 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist -Phase 8 Post Processing Netlist | Checksum: f9b192b3 +Phase 8 Post Processing Netlist | Checksum: 90bb4c32 -Time (s): cpu = 00:00:00.84 ; elapsed = 00:00:00.69 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 115 ; free virtual = 5482 -Post Processing Netlist | Checksum: f9b192b3 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2659.766 ; gain = 32.016 ; free physical = 133 ; free virtual = 3226 +Post Processing Netlist | Checksum: 90bb4c32 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes -Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: d19459d4 +Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 7c6f4f97 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 112 ; free virtual = 5479 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2659.766 ; gain = 32.016 ; free physical = 129 ; free virtual = 3224 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task -Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2679.301 ; gain = 0.000 ; free physical = 111 ; free virtual = 5479 -Phase 9.2 Verifying Netlist Connectivity | Checksum: d19459d4 +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2659.766 ; gain = 0.000 ; free physical = 129 ; free virtual = 3224 +Phase 9.2 Verifying Netlist Connectivity | Checksum: 7c6f4f97 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 111 ; free virtual = 5479 -Phase 9 Finalization | Checksum: d19459d4 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2659.766 ; gain = 32.016 ; free physical = 129 ; free virtual = 3224 +Phase 9 Finalization | Checksum: 7c6f4f97 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 111 ; free virtual = 5479 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2659.766 ; gain = 32.016 ; free physical = 129 ; free virtual = 3224 Opt_design Change Summary ========================= @@ -164,11 +164,11 @@ Opt_design Change Summary ------------------------------------------------------------------------------------------------------------------------- -Ending Logic Optimization Task | Checksum: d19459d4 +Ending Logic Optimization Task | Checksum: 7c6f4f97 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 109 ; free virtual = 5479 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2659.766 ; gain = 32.016 ; free physical = 124 ; free virtual = 3223 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 -Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2679.301 ; gain = 0.000 ; free physical = 105 ; free virtual = 5477 +Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2659.766 ; gain = 0.000 ; free physical = 122 ; free virtual = 3223 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. @@ -185,27 +185,27 @@ Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 36 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 72 -Ending PowerOpt Patch Enables Task | Checksum: d19459d4 +Ending PowerOpt Patch Enables Task | Checksum: 7c6f4f97 -Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 192 ; free virtual = 5341 -Ending Power Optimization Task | Checksum: d19459d4 +Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 253 ; free virtual = 3103 +Ending Power Optimization Task | Checksum: 7c6f4f97 -Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 2817.184 ; gain = 137.883 ; free physical = 172 ; free virtual = 5341 +Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 2799.641 ; gain = 139.875 ; free physical = 247 ; free virtual = 3101 Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: d19459d4 +Ending Final Cleanup Task | Checksum: 7c6f4f97 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 172 ; free virtual = 5341 +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 247 ; free virtual = 3101 Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 171 ; free virtual = 5343 -Ending Netlist Obfuscation Task | Checksum: d19459d4 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 246 ; free virtual = 3101 +Ending Netlist Obfuscation Task | Checksum: 7c6f4f97 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 171 ; free virtual = 5343 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 246 ; free virtual = 3101 INFO: [Common 17-83] Releasing license: Implementation 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully -opt_design: Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2817.184 ; gain = 1043.441 ; free physical = 171 ; free virtual = 5343 +opt_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:41 . Memory (MB): peak = 2799.641 ; gain = 1047.395 ; free physical = 244 ; free virtual = 3100 INFO: [runtcl-4] Executing : report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx Command: report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx INFO: [IP_Flow 19-234] Refreshing IP repositories @@ -214,10 +214,15 @@ INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2023.2 INFO: [DRC 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_drc_opted.rpt. report_drc completed successfully +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_opted.rpt -pb filter_timing_summary_opted.pb -rpx filter_timing_summary_opted.rpx WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs +WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew +Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 111 ; free virtual = 5315 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 190 ; free virtual = 3050 INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_opt.dcp' has been generated. Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' @@ -237,58 +242,58 @@ Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 142 ; free virtual = 5289 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3583ee0c +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 127 ; free virtual = 3034 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3c0b3cc1 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 142 ; free virtual = 5289 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 142 ; free virtual = 5289 +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 127 ; free virtual = 3034 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 127 ; free virtual = 3034 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3d558abc +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 8ad34538 -Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 132 ; free virtual = 5293 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 168 ; free virtual = 3029 Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 8cce5483 +Phase 1.3 Build Placer Netlist Model | Checksum: b07d1e41 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 111 ; free virtual = 5288 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 143 ; free virtual = 3025 Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 8cce5483 +Phase 1.4 Constrain Clocks/Macros | Checksum: b07d1e41 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 111 ; free virtual = 5288 -Phase 1 Placer Initialization | Checksum: 8cce5483 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 143 ; free virtual = 3025 +Phase 1 Placer Initialization | Checksum: b07d1e41 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 111 ; free virtual = 5288 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 138 ; free virtual = 3024 Phase 2 Global Placement Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 47fa083f +Phase 2.1 Floorplanning | Checksum: 9cf052e5 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 109 ; free virtual = 5287 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 128 ; free virtual = 3026 Phase 2.2 Update Timing before SLR Path Opt -Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1275ad596 +Phase 2.2 Update Timing before SLR Path Opt | Checksum: c73f8a70 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 109 ; free virtual = 5286 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 127 ; free virtual = 3026 Phase 2.3 Post-Processing in Floorplanning -Phase 2.3 Post-Processing in Floorplanning | Checksum: 1275ad596 +Phase 2.3 Post-Processing in Floorplanning | Checksum: c73f8a70 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 109 ; free virtual = 5287 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 127 ; free virtual = 3026 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis -Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1457cd503 +Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 19a874187 -Time (s): cpu = 00:00:43 ; elapsed = 00:00:17 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 169 ; free virtual = 5289 +Time (s): cpu = 00:00:27 ; elapsed = 00:00:12 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 197 ; free virtual = 3029 Phase 2.4.2 Physical Synthesis In Placer -INFO: [Physopt 32-1035] Found 10 LUTNM shape to break, 4 LUT instances to create LUTNM shape -INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 10, total 10, new lutff created 0 -INFO: [Physopt 32-1138] End 1 Pass. Optimized 12 nets or LUTs. Breaked 10 LUTs, combined 2 existing LUTs and moved 0 existing LUT +INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 4 LUT instances to create LUTNM shape +INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 +INFO: [Physopt 32-1138] End 1 Pass. Optimized 2 nets or LUTs. Breaked 0 LUT, combined 2 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell @@ -296,9 +301,9 @@ INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization. -INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-1402] Pass 1: Identified 40 candidate cells for Shift Register optimization. +INFO: [Physopt 32-775] End 1 Pass. Optimized 23 nets or cells. Created 45 new cells, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 168 ; free virtual = 3029 INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design @@ -307,7 +312,7 @@ INFO: [Physopt 32-846] No candidate cells for URAM register optimization found i INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 144 ; free virtual = 5284 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 168 ; free virtual = 3029 Summary of Physical Synthesis Optimizations ============================================ @@ -316,78 +321,78 @@ Summary of Physical Synthesis Optimizations ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- -| LUT Combining | 10 | 2 | 12 | 0 | 1 | 00:00:00 | +| LUT Combining | 0 | 2 | 2 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Shift Register | 45 | 0 | 23 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 10 | 2 | 12 | 0 | 9 | 00:00:00 | +| Total | 45 | 2 | 25 | 0 | 9 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- -Phase 2.4.2 Physical Synthesis In Placer | Checksum: 19c5c57a6 +Phase 2.4.2 Physical Synthesis In Placer | Checksum: 20b107fd7 -Time (s): cpu = 00:00:45 ; elapsed = 00:00:18 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 144 ; free virtual = 5284 -Phase 2.4 Global Placement Core | Checksum: 1b40ef446 +Time (s): cpu = 00:00:29 ; elapsed = 00:00:13 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 164 ; free virtual = 3027 +Phase 2.4 Global Placement Core | Checksum: 1f000dffd -Time (s): cpu = 00:00:47 ; elapsed = 00:00:18 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 143 ; free virtual = 5284 -Phase 2 Global Placement | Checksum: 1b40ef446 +Time (s): cpu = 00:00:31 ; elapsed = 00:00:14 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 163 ; free virtual = 3026 +Phase 2 Global Placement | Checksum: 1f000dffd -Time (s): cpu = 00:00:47 ; elapsed = 00:00:19 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 143 ; free virtual = 5284 +Time (s): cpu = 00:00:31 ; elapsed = 00:00:14 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 162 ; free virtual = 3027 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 11f4d2582 +Phase 3.1 Commit Multi Column Macros | Checksum: 1ec652ec9 -Time (s): cpu = 00:00:48 ; elapsed = 00:00:19 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 142 ; free virtual = 5283 +Time (s): cpu = 00:00:33 ; elapsed = 00:00:14 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 154 ; free virtual = 3025 Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 12b805f00 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 13458fbed -Time (s): cpu = 00:00:53 ; elapsed = 00:00:21 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 137 ; free virtual = 5282 +Time (s): cpu = 00:00:36 ; elapsed = 00:00:16 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 139 ; free virtual = 3023 Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 157230410 +Phase 3.3 Area Swap Optimization | Checksum: 10277a41b -Time (s): cpu = 00:00:53 ; elapsed = 00:00:22 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 136 ; free virtual = 5282 +Time (s): cpu = 00:00:36 ; elapsed = 00:00:16 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 138 ; free virtual = 3023 Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 128b350f2 +Phase 3.4 Pipeline Register Optimization | Checksum: d226fbde -Time (s): cpu = 00:00:53 ; elapsed = 00:00:22 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 136 ; free virtual = 5282 +Time (s): cpu = 00:00:36 ; elapsed = 00:00:16 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 138 ; free virtual = 3023 Phase 3.5 Fast Optimization -Phase 3.5 Fast Optimization | Checksum: 1632181f8 +Phase 3.5 Fast Optimization | Checksum: 132b21e47 -Time (s): cpu = 00:00:58 ; elapsed = 00:00:24 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 130 ; free virtual = 5276 +Time (s): cpu = 00:00:41 ; elapsed = 00:00:18 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 134 ; free virtual = 3022 Phase 3.6 Small Shape Detail Placement -Phase 3.6 Small Shape Detail Placement | Checksum: f844008a +Phase 3.6 Small Shape Detail Placement | Checksum: 18283862c -Time (s): cpu = 00:01:00 ; elapsed = 00:00:26 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5275 +Time (s): cpu = 00:00:43 ; elapsed = 00:00:20 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 118 ; free virtual = 3014 Phase 3.7 Re-assign LUT pins -Phase 3.7 Re-assign LUT pins | Checksum: 14d2456fe +Phase 3.7 Re-assign LUT pins | Checksum: 19d13be25 -Time (s): cpu = 00:01:01 ; elapsed = 00:00:26 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5273 +Time (s): cpu = 00:00:44 ; elapsed = 00:00:20 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 117 ; free virtual = 3014 Phase 3.8 Pipeline Register Optimization -Phase 3.8 Pipeline Register Optimization | Checksum: 17ad421e0 +Phase 3.8 Pipeline Register Optimization | Checksum: 16d448768 -Time (s): cpu = 00:01:01 ; elapsed = 00:00:26 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5273 +Time (s): cpu = 00:00:44 ; elapsed = 00:00:20 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 117 ; free virtual = 3014 Phase 3.9 Fast Optimization -Phase 3.9 Fast Optimization | Checksum: 17f4b35b0 +Phase 3.9 Fast Optimization | Checksum: 150dbd156 -Time (s): cpu = 00:01:06 ; elapsed = 00:00:29 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 110 ; free virtual = 5267 -Phase 3 Detail Placement | Checksum: 17f4b35b0 +Time (s): cpu = 00:00:50 ; elapsed = 00:00:23 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 113 ; free virtual = 3012 +Phase 3 Detail Placement | Checksum: 150dbd156 -Time (s): cpu = 00:01:06 ; elapsed = 00:00:29 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 110 ; free virtual = 5267 +Time (s): cpu = 00:00:50 ; elapsed = 00:00:23 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 113 ; free virtual = 3012 Phase 4 Post Placement Optimization and Clean-Up @@ -396,7 +401,7 @@ WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 1caaa20ca +Post Placement Optimization Initialization | Checksum: 151f3014f Phase 4.1.1.1 BUFG Insertion @@ -404,33 +409,33 @@ Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.908 | TNS=-6490.125 | -Phase 1 Physical Synthesis Initialization | Checksum: 179e6ab06 +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.433 | TNS=-22.659 | +Phase 1 Physical Synthesis Initialization | Checksum: 1b42db68e -Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 153 ; free virtual = 5299 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.55 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 221 ; free virtual = 3024 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. -Ending Physical Synthesis Task | Checksum: 179e6ab06 +Ending Physical Synthesis Task | Checksum: 1b42db68e -Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 151 ; free virtual = 5296 -Phase 4.1.1.1 BUFG Insertion | Checksum: 1caaa20ca +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.7 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 221 ; free virtual = 3024 +Phase 4.1.1.1 BUFG Insertion | Checksum: 151f3014f -Time (s): cpu = 00:01:11 ; elapsed = 00:00:31 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 151 ; free virtual = 5296 +Time (s): cpu = 00:00:58 ; elapsed = 00:00:27 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 221 ; free virtual = 3024 Phase 4.1.1.2 Post Placement Timing Optimization -INFO: [Place 30-746] Post Placement Timing Summary WNS=-16.162. For the most accurate timing information please run report_timing. -Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 186ecb07f +INFO: [Place 30-746] Post Placement Timing Summary WNS=-1.198. For the most accurate timing information please run report_timing. +Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: dd4b4bc1 -Time (s): cpu = 00:01:54 ; elapsed = 00:01:11 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 122 ; free virtual = 5294 +Time (s): cpu = 00:01:40 ; elapsed = 00:01:07 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 130 ; free virtual = 3003 -Time (s): cpu = 00:01:54 ; elapsed = 00:01:11 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 122 ; free virtual = 5294 -Phase 4.1 Post Commit Optimization | Checksum: 186ecb07f +Time (s): cpu = 00:01:41 ; elapsed = 00:01:07 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 130 ; free virtual = 3003 +Phase 4.1 Post Commit Optimization | Checksum: dd4b4bc1 -Time (s): cpu = 00:01:54 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 122 ; free virtual = 5295 +Time (s): cpu = 00:01:41 ; elapsed = 00:01:07 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 130 ; free virtual = 3003 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 186ecb07f +Phase 4.2 Post Placement Cleanup | Checksum: dd4b4bc1 -Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 +Time (s): cpu = 00:01:41 ; elapsed = 00:01:08 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 128 ; free virtual = 3002 Phase 4.3 Placer Reporting @@ -440,51 +445,51 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| -| North| 4x4| 8x8| +| North| 1x1| 4x4| |___________|___________________|___________________| -| South| 2x2| 4x4| +| South| 1x1| 4x4| |___________|___________________|___________________| -| East| 4x4| 8x8| +| East| 1x1| 1x1| |___________|___________________|___________________| -| West| 4x4| 4x4| +| West| 1x1| 1x1| |___________|___________________|___________________| -Phase 4.3.1 Print Estimated Congestion | Checksum: 186ecb07f +Phase 4.3.1 Print Estimated Congestion | Checksum: dd4b4bc1 -Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 -Phase 4.3 Placer Reporting | Checksum: 186ecb07f +Time (s): cpu = 00:01:41 ; elapsed = 00:01:08 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 128 ; free virtual = 3002 +Phase 4.3 Placer Reporting | Checksum: dd4b4bc1 -Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 +Time (s): cpu = 00:01:41 ; elapsed = 00:01:08 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 128 ; free virtual = 3002 Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 128 ; free virtual = 3003 -Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2313e4908 +Time (s): cpu = 00:01:41 ; elapsed = 00:01:08 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 128 ; free virtual = 3003 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 8d98dd64 -Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 -Ending Placer Task | Checksum: 1402e79b2 +Time (s): cpu = 00:01:41 ; elapsed = 00:01:08 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 128 ; free virtual = 3003 +Ending Placer Task | Checksum: 46adcee8 -Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 -75 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. +Time (s): cpu = 00:01:41 ; elapsed = 00:01:08 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 128 ; free virtual = 3003 +77 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully -place_design: Time (s): cpu = 00:01:57 ; elapsed = 00:01:13 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 +place_design: Time (s): cpu = 00:01:45 ; elapsed = 00:01:09 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 117 ; free virtual = 3001 INFO: [runtcl-4] Executing : report_io -file filter_io_placed.rpt -report_io: Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 123 ; free virtual = 5306 +report_io: Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 225 ; free virtual = 3021 INFO: [runtcl-4] Executing : report_utilization -file filter_utilization_placed.rpt -pb filter_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file filter_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 129 ; free virtual = 5308 +report_control_sets: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 207 ; free virtual = 3007 INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 133 ; free virtual = 5307 -Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 201 ; free virtual = 5303 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 201 ; free virtual = 5303 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 206 ; free virtual = 3008 +Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 198 ; free virtual = 3008 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 196 ; free virtual = 3008 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 191 ; free virtual = 5293 -Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 190 ; free virtual = 5293 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 190 ; free virtual = 5293 -Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.76 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 190 ; free virtual = 5293 +Wrote RouteStorage: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 185 ; free virtual = 3005 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 184 ; free virtual = 3005 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 184 ; free virtual = 3005 +Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 184 ; free virtual = 3005 INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_placed.dcp' has been generated. Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' @@ -494,366 +499,225 @@ Starting Initial Update Timing Task WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 168 ; free virtual = 5274 -INFO: [Vivado_Tcl 4-1435] PhysOpt_Tcl_Interface Runtime Before Starting Physical Synthesis Task | CPU: 2.64s | WALL: 1.05s -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 168 ; free virtual = 5274 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 172 ; free virtual = 2990 +INFO: [Vivado_Tcl 4-1435] PhysOpt_Tcl_Interface Runtime Before Starting Physical Synthesis Task | CPU: 3.88s | WALL: 1.78s +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 172 ; free virtual = 2990 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.162 | TNS=-6269.708 | -Phase 1 Physical Synthesis Initialization | Checksum: 1c58d1c6b +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.198 | TNS=-18.999 | +Phase 1 Physical Synthesis Initialization | Checksum: eda825fd -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.93 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 156 ; free virtual = 5268 -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.162 | TNS=-6269.708 | +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 162 ; free virtual = 2992 +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.198 | TNS=-18.999 | Phase 2 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Phase 2 DSP Register Optimization | Checksum: 1c58d1c6b +Phase 2 DSP Register Optimization | Checksum: eda825fd -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.98 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 156 ; free virtual = 5269 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 162 ; free virtual = 2992 Phase 3 Critical Path Optimization -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.162 | TNS=-6269.708 | -INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][52]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-663] Processed net in_key[8]. Re-placed instance registered_input.in_key_reg[8] -INFO: [Physopt 32-735] Processed net in_key[8]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.142 | TNS=-6267.728 | -INFO: [Physopt 32-81] Processed net in_key[72]. Replicated 2 times. -INFO: [Physopt 32-735] Processed net in_key[72]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.119 | TNS=-6265.451 | -INFO: [Physopt 32-702] Processed net in_key[72]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_4_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_24_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_26_n_6. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_29_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_59_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_98_n_6. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_106_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_101_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_109_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_95_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_103_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_104_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_190_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_350[5]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_262_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_264_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_282_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_283_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_27_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_30_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_33_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_93_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_110_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_96_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_127_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/minusOp10_out_0[9]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_286_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_479_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/minusOp12_out[25]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_577_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_571_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_573_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_99_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_276_0[3]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_429_0[29]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_279_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_434_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_535_0[24]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_725_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1046_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-710] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1046_n_0. Critical path length was reduced through logic transformation on cell hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1046_comp. -INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1100__0_n_0. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.103 | TNS=-6263.768 | -INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][34]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-663] Processed net in_key[0]. Re-placed instance registered_input.in_key_reg[0] -INFO: [Physopt 32-735] Processed net in_key[0]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.102 | TNS=-6259.511 | -INFO: [Physopt 32-81] Processed net in_key[8]. Replicated 2 times. -INFO: [Physopt 32-735] Processed net in_key[8]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.099 | TNS=-6259.214 | -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1047_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-710] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1047_n_0. Critical path length was reduced through logic transformation on cell hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1047_comp. -INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]13_out[21]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.072 | TNS=-6256.541 | -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_433_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/mix_stage[1][a][25]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_513_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_721_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][a][23]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1044_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-710] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1044_n_0. Critical path length was reduced through logic transformation on cell hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1044_comp. -INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]7_out[20]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.060 | TNS=-6253.472 | -INFO: [Physopt 32-81] Processed net in_key[2]. Replicated 3 times. -INFO: [Physopt 32-735] Processed net in_key[2]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.059 | TNS=-6252.086 | -INFO: [Physopt 32-702] Processed net storage_generate[2].storage/memory_rule[2][124]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-81] Processed net in_key[65]. Replicated 2 times. -INFO: [Physopt 32-735] Processed net in_key[65]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.046 | TNS=-6250.701 | -INFO: [Physopt 32-81] Processed net in_key[64]. Replicated 5 times. -INFO: [Physopt 32-735] Processed net in_key[64]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.045 | TNS=-6250.502 | -INFO: [Physopt 32-663] Processed net in_key[9]. Re-placed instance registered_input.in_key_reg[9] -INFO: [Physopt 32-735] Processed net in_key[9]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.045 | TNS=-6250.502 | -INFO: [Physopt 32-81] Processed net in_key[68]. Replicated 1 times. -INFO: [Physopt 32-735] Processed net in_key[68]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.045 | TNS=-6250.007 | -INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][88]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-81] Processed net in_key[1]. Replicated 3 times. -INFO: [Physopt 32-735] Processed net in_key[1]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.043 | TNS=-6248.027 | -INFO: [Physopt 32-663] Processed net in_key[5]. Re-placed instance registered_input.in_key_reg[5] -INFO: [Physopt 32-735] Processed net in_key[5]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.041 | TNS=-6247.730 | -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_431_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/minusOp4_out[27]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_741_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-710] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_741_n_0. Critical path length was reduced through logic transformation on cell hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_741_comp. -INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]13_out[25]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.040 | TNS=-6247.631 | -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1052_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-663] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]13_out[21]. Re-placed instance hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1101 -INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]13_out[21]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.040 | TNS=-6245.453 | -INFO: [Physopt 32-663] Processed net in_key[74]. Re-placed instance registered_input.in_key_reg[74] -INFO: [Physopt 32-735] Processed net in_key[74]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.038 | TNS=-6245.057 | -INFO: [Physopt 32-663] Processed net in_key[9]. Re-placed instance registered_input.in_key_reg[9] -INFO: [Physopt 32-735] Processed net in_key[9]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.038 | TNS=-6245.255 | -INFO: [Physopt 32-81] Processed net in_key[69]. Replicated 1 times. -INFO: [Physopt 32-735] Processed net in_key[69]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.036 | TNS=-6244.364 | -INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][34]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-663] Processed net in_key[66]. Re-placed instance registered_input.in_key_reg[66] -INFO: [Physopt 32-735] Processed net in_key[66]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.030 | TNS=-6243.770 | -INFO: [Physopt 32-702] Processed net in_key[66]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_26_n_6. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_98_n_7. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_350__0[5]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/minusOp10_out_0[20]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_810__0[5]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_276_0[3]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/O75[29]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_435_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/mix_stage[1][a][25]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_730_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][a][21]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.198 | TNS=-18.999 | +INFO: [Physopt 32-702] Processed net OUTPUT_KEY_FOUND. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][40]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/out_key_found13_out. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_6_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_15_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_29_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_44_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_59_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_74_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_89_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_104_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_119_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. -INFO: [Physopt 32-735] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1066_n_0. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.029 | TNS=-6243.275 | -INFO: [Physopt 32-702] Processed net storage_generate[2].storage/memory_rule[2][124]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net in_key[0]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_29_n_6. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_101_n_4. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_350__1[5]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/minusOp10_out_0[13]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_322__1_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_808__1[5]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/L8_out[17]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1144__1_0[17]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-608] Optimized 1 net. Swapped 22 pins. -INFO: [Physopt 32-735] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1151__1_n_0. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.028 | TNS=-6243.176 | -INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][88]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net in_key[7]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_16__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_29_n_6. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_85__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_101_n_4. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_191__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_350__2[4]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_93__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_238__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/minusOp10_out_1[13]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_322__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_780__1[5]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_302_0[1]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/mix_stage[1][b][31]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_428_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_534_0[28]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_724_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-663] Processed net hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[27]. Re-placed instance hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_732 -INFO: [Physopt 32-735] Processed net hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[27]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.028 | TNS=-6241.592 | -INFO: [Physopt 32-702] Processed net in_key[65]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/L8_out[25]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1144__1_0[25]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1155__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-663] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0. Re-placed instance hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1 -INFO: [Physopt 32-735] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.025 | TNS=-6240.800 | -INFO: [Physopt 32-663] Processed net in_key[10]. Re-placed instance registered_input.in_key_reg[10] -INFO: [Physopt 32-735] Processed net in_key[10]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.025 | TNS=-6240.800 | -INFO: [Physopt 32-702] Processed net in_key[71]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_302_0[0]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/O75[30]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_430_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/mix_stage[1][a][29]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_670_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][a][25]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1052_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]7_out[20]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[19]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_962_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[72]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[15]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_889__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[13]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_797__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_513_n_6. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/O76[9]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.025 | TNS=-6240.800 | -Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 137 ; free virtual = 5271 -Phase 3 Critical Path Optimization | Checksum: 17af5ebfb +INFO: [Physopt 32-735] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_135_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.188 | TNS=-18.837 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][31]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/CO[0]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_10_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_20_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_34_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_49_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_64_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_79_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_94_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_109_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_124_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_i_143_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.179 | TNS=-18.828 | +INFO: [Physopt 32-702] Processed net OUTPUT_DATA[13]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][58]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-710] Processed net storage_generate[2].storage/D[13]. Critical path length was reduced through logic transformation on cell storage_generate[2].storage/registered_output.OUTPUT_DATA[13]_i_1_comp. +INFO: [Physopt 32-735] Processed net storage_generate[3].storage/memory_reg_0_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.179 | TNS=-18.809 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][37]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_136_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.177 | TNS=-18.754 | +INFO: [Physopt 32-702] Processed net OUTPUT_DATA[10]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_reg_0_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/out_key_found1. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_25_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_39_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_54_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_69_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_84_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_99_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_114_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_132_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.164 | TNS=-18.128 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][25]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_139_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_i_154_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.144 | TNS=-18.108 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][58]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_107_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.144 | TNS=-18.108 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][46]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.136 | TNS=-18.053 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][22]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_i_155_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.136 | TNS=-18.053 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][42]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_123_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.133 | TNS=-18.027 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][46]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_i_127_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.132 | TNS=-18.017 | +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][37]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_129_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_144_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_159_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.123 | TNS=-17.883 | +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][76]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_115_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.123 | TNS=-17.789 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][73]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_91_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.121 | TNS=-17.735 | +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/memory_rule[2][22]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/memory_reg_0_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/CO[0]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.115 | TNS=-17.724 | +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][78]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_103_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.110 | TNS=-17.419 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][18]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_i_156_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.101 | TNS=-17.410 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][40]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_i_140_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.098 | TNS=-17.407 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][81]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_77_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.097 | TNS=-17.376 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][81]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_i_82_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.094 | TNS=-17.369 | +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][22]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_157_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_164_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.090 | TNS=-17.264 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][27]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_i_153_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.087 | TNS=-17.260 | +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][40]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_158_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.086 | TNS=-17.215 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][94]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_i_67_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.084 | TNS=-17.213 | +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][25]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_163_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.084 | TNS=-16.983 | +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/memory_rule[2][17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_56_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 6 pins. +INFO: [Physopt 32-735] Processed net storage_generate[1].storage/memory_reg_0_16. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.078 | TNS=-16.977 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][48]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_121_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.072 | TNS=-16.932 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_reg_0_16. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net OUTPUT_KEY_FOUND. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][46]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/out_key_found13_out. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_reg_0_16. Optimizations did not improve timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.072 | TNS=-16.932 | +Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 143 ; free virtual = 2984 +Phase 3 Critical Path Optimization | Checksum: eda825fd -Time (s): cpu = 00:00:41 ; elapsed = 00:00:21 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 131 ; free virtual = 5271 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 139 ; free virtual = 2984 Phase 4 Critical Path Optimization -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.025 | TNS=-6240.800 | -INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][34]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-81] Processed net in_key[71]. Replicated 3 times. -INFO: [Physopt 32-735] Processed net in_key[71]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.023 | TNS=-6240.602 | -INFO: [Physopt 32-81] Processed net in_key[66]. Replicated 2 times. -INFO: [Physopt 32-735] Processed net in_key[66]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.021 | TNS=-6240.404 | -INFO: [Physopt 32-81] Processed net in_key[64]_repN. Replicated 1 times. -INFO: [Physopt 32-735] Processed net in_key[64]_repN. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.020 | TNS=-6240.008 | -INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][52]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-81] Processed net in_key[9]. Replicated 3 times. -INFO: [Physopt 32-735] Processed net in_key[9]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.020 | TNS=-6239.810 | -INFO: [Physopt 32-702] Processed net storage_generate[2].storage/memory_rule[2][124]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-81] Processed net in_key[0]. Replicated 5 times. -INFO: [Physopt 32-735] Processed net in_key[0]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.018 | TNS=-6239.316 | -INFO: [Physopt 32-663] Processed net in_key[72]. Re-placed instance registered_input.in_key_reg[72] -INFO: [Physopt 32-735] Processed net in_key[72]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.017 | TNS=-6238.820 | -INFO: [Physopt 32-702] Processed net in_key[2]_repN. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_3_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_4_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_26_n_6. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_29_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_98_n_7. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_106_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_101_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_109_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_95_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_103_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_104_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_350__0[5]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_262_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_264_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_282_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_283_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_27_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_30_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_33_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_110_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/minusOp10_out_0[20]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_258_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_259_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_256_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_810__0[5]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_580_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_579_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_573_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_575_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_99_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_276_0[3]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/O75[29]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_435_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/mix_stage[1][a][25]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_515_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_730_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][a][21]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_677_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1002_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-710] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1002_n_0. Critical path length was reduced through logic transformation on cell hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1002_comp. -INFO: [Physopt 32-735] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]7_out[16]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.015 | TNS=-6237.929 | -INFO: [Physopt 32-81] Processed net in_key[65]. Replicated 1 times. -INFO: [Physopt 32-735] Processed net in_key[65]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.013 | TNS=-6237.732 | -INFO: [Physopt 32-663] Processed net in_key[78]. Re-placed instance registered_input.in_key_reg[78] -INFO: [Physopt 32-735] Processed net in_key[78]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.013 | TNS=-6237.533 | -INFO: [Physopt 32-663] Processed net in_key[13]. Re-placed instance registered_input.in_key_reg[13] -INFO: [Physopt 32-735] Processed net in_key[13]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.012 | TNS=-6236.939 | -INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][88]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net in_key[7]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_16__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_29_n_6. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_85__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_101_n_4. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_191__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_350__2[4]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_93__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_238__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/minusOp10_out_1[13]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_322__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_780__1[5]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_302_0[1]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/mix_stage[1][b][31]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_428_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_534_0[28]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_722_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[24]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_960[22]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_385__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_509_0[20]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_912_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/registered_input.in_key_reg[72]_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/minusOp12_out[17]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_858__1_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/minusOp14_out[13]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_768__1_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/plusOp_inferred__0/i__carry__1_n_7. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/O76[9]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.012 | TNS=-6236.939 | -Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 111 ; free virtual = 5273 -Phase 4 Critical Path Optimization | Checksum: 17af5ebfb +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.072 | TNS=-16.932 | +INFO: [Physopt 32-702] Processed net OUTPUT_KEY_FOUND. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][46]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/out_key_found13_out. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_6_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_15_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_29_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_44_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_59_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_74_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_89_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_104_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_reg_0_16. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net OUTPUT_KEY_FOUND. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][46]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/out_key_found13_out. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_reg_0_16. Optimizations did not improve timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.072 | TNS=-16.932 | +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 139 ; free virtual = 2983 +Phase 4 Critical Path Optimization | Checksum: eda825fd -Time (s): cpu = 00:01:03 ; elapsed = 00:00:32 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 111 ; free virtual = 5273 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 111 ; free virtual = 5274 -INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-16.012 | TNS=-6236.939 | +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 139 ; free virtual = 2983 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 139 ; free virtual = 2983 +INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-1.072 | TNS=-16.932 | Summary of Physical Synthesis Optimizations ============================================ @@ -863,30 +727,30 @@ Summary of Physical Synthesis Optimizations | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------- | DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Critical Path | 0.150 | 32.769 | 34 | 0 | 35 | 0 | 2 | 00:00:31 | -| Total | 0.150 | 32.769 | 34 | 0 | 35 | 0 | 3 | 00:00:31 | +| Critical Path | 0.126 | 2.067 | 0 | 0 | 27 | 0 | 2 | 00:00:05 | +| Total | 0.126 | 2.067 | 0 | 0 | 27 | 0 | 3 | 00:00:05 | ------------------------------------------------------------------------------------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 111 ; free virtual = 5274 -Ending Physical Synthesis Task | Checksum: 27673438e +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 139 ; free virtual = 2983 +Ending Physical Synthesis Task | Checksum: a12a07e7 -Time (s): cpu = 00:01:03 ; elapsed = 00:00:32 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 110 ; free virtual = 5273 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 139 ; free virtual = 2983 INFO: [Common 17-83] Releasing license: Implementation -415 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. +276 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully -phys_opt_design: Time (s): cpu = 00:01:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 110 ; free virtual = 5273 +phys_opt_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 139 ; free virtual = 2983 INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 109 ; free virtual = 5273 -Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.71 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 5257 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 5257 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 134 ; free virtual = 2984 +Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.73 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 120 ; free virtual = 2976 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 120 ; free virtual = 2976 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 5257 -Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 5257 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 188 ; free virtual = 5257 -Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.76 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 188 ; free virtual = 5257 +Wrote RouteStorage: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 120 ; free virtual = 2976 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 119 ; free virtual = 2977 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 119 ; free virtual = 2977 +Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.8 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 119 ; free virtual = 2977 INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_physopt.dcp' has been generated. Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' @@ -904,133 +768,133 @@ Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs Phase 1 Build RT Design -Checksum: PlaceDB: a88baaee ConstDB: 0 ShapeSum: d8eec616 RouteDB: 0 +Checksum: PlaceDB: 578213a9 ConstDB: 0 ShapeSum: 2223e39e RouteDB: 0 WARNING: [Route 35-197] Clock port "CLK" does not have an associated HD.CLK_SRC. Without this constraint, timing analysis may not be accurate and upstream checks cannot be done to ensure correct clock placement. -WARNING: [Route 35-198] Port "CONFIG_KEY[117]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[117]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[120]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[120]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "RESET" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "RESET". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_VALID" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_VALID". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[102]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[102]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[98]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[98]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[100]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[100]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "CONFIG_KEY[94]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[94]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[32]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[32]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[28]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[28]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[106]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[106]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[107]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[107]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[104]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[104]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[113]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[113]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[108]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[108]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[105]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[105]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[124]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[124]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[125]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[125]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[126]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[126]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[127]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[127]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[120]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[120]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[121]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[121]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[122]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[122]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[123]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[123]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[116]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[116]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[118]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[118]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[117]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[117]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[119]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[119]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[112]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[112]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[114]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[114]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[91]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[91]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[115]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[115]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[96]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[96]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[101]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[101]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[93]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[93]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[99]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[99]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[92]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[92]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[103]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[103]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[63]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[63]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[127]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[127]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[95]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[95]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[97]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[97]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[118]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[118]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[112]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[112]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[122]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[122]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[120]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[120]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[124]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[124]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[60]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[60]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[31]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[31]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[30]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[30]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[57]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[57]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[52]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[52]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[94]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[94]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[62]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[62]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[61]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[61]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[56]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[56]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "CONFIG_KEY[116]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[116]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "CONFIG_KEY[114]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[114]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[108]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[108]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[102]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[102]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[100]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[100]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[98]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[98]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[96]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[96]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[30]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[30]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[86]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[86]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[84]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[84]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[122]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[122]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[118]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[118]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[106]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[106]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[70]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[70]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[121]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[121]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[103]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[103]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[57]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[57]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[35]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[35]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[66]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[66]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[60]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[60]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[33]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[33]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[25]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[25]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[119]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[119]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[111]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[111]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[104]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[104]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[125]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[125]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[64]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[64]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[105]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[105]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[90]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[90]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[89]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[89]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[124]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[124]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[110]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[110]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[76]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[76]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[34]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[34]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[50]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[50]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[20]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[20]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[88]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[88]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[44]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[44]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[48]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[48]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[72]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[72]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[54]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[54]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[21]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[21]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[46]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[46]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[42]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[42]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[91]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[91]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[36]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[36]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[26]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[26]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[24]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[24]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[113]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[113]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[82]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[82]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[22]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[22]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[40]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[40]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_DATA[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_DATA[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_DATA[13]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[13]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_DATA[12]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[12]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[77]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[77]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[62]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[62]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[52]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[52]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_DATA[8]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[8]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[69]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[69]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[47]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[47]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_WRITE" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_WRITE". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "RESET" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "RESET". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_ADDRESS_TABLE[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_TABLE[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_ADDRESS_TABLE[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_TABLE[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[78]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[78]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[75]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[75]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[74]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[74]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[68]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[68]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[123]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[123]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "CONFIG_KEY[126]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[126]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_DATA[14]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[14]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_DATA[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[53]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[53]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[73]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[73]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[16]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[16]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_DATA[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[43]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[43]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[41]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[41]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_DATA[11]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[11]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_EMPTY" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_EMPTY". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[38]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[38]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[19]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[19]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[37]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[37]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[97]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[97]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[29]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[29]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_ADDRESS_ITEM[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_ITEM[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_ADDRESS_ITEM[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_ITEM[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_ADDRESS_ITEM[9]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_ITEM[9]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[55]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[55]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[31]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[31]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_ADDRESS_ITEM[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_ITEM[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[125]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[125]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[59]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[59]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[58]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[58]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[121]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[121]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[110]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[110]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[119]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[119]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[117]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[117]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[109]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[109]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[55]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[55]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[95]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[95]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[29]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[29]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[28]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[28]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[27]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[27]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[53]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[53]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[88]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[88]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[93]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[93]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[91]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[91]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[108]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[108]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[109]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[109]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[110]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[110]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[111]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[111]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[104]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[104]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[105]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[105]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[106]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[106]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[107]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[107]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[115]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[115]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[113]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[113]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[111]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[111]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[70]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[70]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[68]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[68]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[60]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[60]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[58]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[58]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[66]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[66]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[64]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[64]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[86]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[86]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[72]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[72]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[69]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[69]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[65]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[65]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[62]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[62]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[92]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[92]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[89]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[89]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[87]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[87]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[71]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[71]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[100]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[100]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. INFO: [Common 17-14] Message 'Route 35-198' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Constraints 18-8777] Unable to split tiles. All required files are not available. -Post Restoration Checksum: NetGraph: f5668f66 | NumContArr: ae2b9928 | Constraints: c2a8fa9d | Timing: c2a8fa9d -Phase 1 Build RT Design | Checksum: 328e41dc8 +Post Restoration Checksum: NetGraph: f8c3490f | NumContArr: f1ba4717 | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 36fcf8560 -Time (s): cpu = 00:00:52 ; elapsed = 00:00:35 . Memory (MB): peak = 2949.961 ; gain = 113.758 ; free physical = 97 ; free virtual = 5070 +Time (s): cpu = 00:00:54 ; elapsed = 00:00:37 . Memory (MB): peak = 2959.430 ; gain = 116.758 ; free physical = 110 ; free virtual = 2852 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 328e41dc8 +Phase 2.1 Fix Topology Constraints | Checksum: 36fcf8560 -Time (s): cpu = 00:00:52 ; elapsed = 00:00:36 . Memory (MB): peak = 2949.961 ; gain = 113.758 ; free physical = 117 ; free virtual = 5073 +Time (s): cpu = 00:00:54 ; elapsed = 00:00:37 . Memory (MB): peak = 2959.430 ; gain = 116.758 ; free physical = 110 ; free virtual = 2852 Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 328e41dc8 +Phase 2.2 Pre Route Cleanup | Checksum: 36fcf8560 -Time (s): cpu = 00:00:52 ; elapsed = 00:00:36 . Memory (MB): peak = 2949.961 ; gain = 113.758 ; free physical = 119 ; free virtual = 5075 +Time (s): cpu = 00:00:54 ; elapsed = 00:00:37 . Memory (MB): peak = 2959.430 ; gain = 116.758 ; free physical = 110 ; free virtual = 2852 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing -Phase 2.3 Update Timing | Checksum: 242e0954c +Phase 2.3 Update Timing | Checksum: 25dc24139 -Time (s): cpu = 00:00:58 ; elapsed = 00:00:38 . Memory (MB): peak = 2979.195 ; gain = 142.992 ; free physical = 163 ; free virtual = 5036 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=-15.599| TNS=-6066.110| WHS=0.033 | THS=0.000 | +Time (s): cpu = 00:01:02 ; elapsed = 00:00:41 . Memory (MB): peak = 2987.664 ; gain = 144.992 ; free physical = 151 ; free virtual = 2802 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.064 | TNS=-15.944| WHS=-0.016 | THS=-0.032 | Router Utilization Summary @@ -1039,155 +903,108 @@ Router Utilization Summary Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. - Number of Failed Nets = 5168 + Number of Failed Nets = 7074 (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 5168 + Number of Unrouted Nets = 7074 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 2 Router Initialization | Checksum: 1d6088a45 +Phase 2 Router Initialization | Checksum: 20e1bf80c -Time (s): cpu = 00:01:01 ; elapsed = 00:00:40 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 151 ; free virtual = 5026 +Time (s): cpu = 00:01:07 ; elapsed = 00:00:42 . Memory (MB): peak = 2992.961 ; gain = 150.289 ; free physical = 145 ; free virtual = 2798 Phase 3 Initial Routing Phase 3.1 Global Routing -Phase 3.1 Global Routing | Checksum: 1d6088a45 +Phase 3.1 Global Routing | Checksum: 20e1bf80c -Time (s): cpu = 00:01:01 ; elapsed = 00:00:40 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 151 ; free virtual = 5026 +Time (s): cpu = 00:01:07 ; elapsed = 00:00:42 . Memory (MB): peak = 2992.961 ; gain = 150.289 ; free physical = 145 ; free virtual = 2798 Phase 3.2 Initial Net Routing -Phase 3.2 Initial Net Routing | Checksum: 2130f4a2f +Phase 3.2 Initial Net Routing | Checksum: 2312d3ca6 -Time (s): cpu = 00:01:32 ; elapsed = 00:00:51 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 231 ; free virtual = 5021 -Phase 3 Initial Routing | Checksum: 2130f4a2f +Time (s): cpu = 00:01:13 ; elapsed = 00:00:44 . Memory (MB): peak = 2992.961 ; gain = 150.289 ; free physical = 145 ; free virtual = 2797 +Phase 3 Initial Routing | Checksum: 2312d3ca6 -Time (s): cpu = 00:01:33 ; elapsed = 00:00:51 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 231 ; free virtual = 5021 +Time (s): cpu = 00:01:13 ; elapsed = 00:00:44 . Memory (MB): peak = 2992.961 ; gain = 150.289 ; free physical = 145 ; free virtual = 2797 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 4441 - Number of Nodes with overlaps = 1719 - Number of Nodes with overlaps = 1028 - Number of Nodes with overlaps = 514 - Number of Nodes with overlaps = 269 - Number of Nodes with overlaps = 127 - Number of Nodes with overlaps = 70 - Number of Nodes with overlaps = 32 - Number of Nodes with overlaps = 19 - Number of Nodes with overlaps = 5 - Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 206 + Number of Nodes with overlaps = 74 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.774| TNS=-6851.693| WHS=N/A | THS=N/A | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.252 | TNS=-31.493| WHS=N/A | THS=N/A | -Phase 4.1 Global Iteration 0 | Checksum: 225940652 +Phase 4.1 Global Iteration 0 | Checksum: 2cac37e0d -Time (s): cpu = 00:04:22 ; elapsed = 00:02:04 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 215 ; free virtual = 5156 +Time (s): cpu = 00:01:24 ; elapsed = 00:00:52 . Memory (MB): peak = 2992.961 ; gain = 150.289 ; free physical = 204 ; free virtual = 2786 Phase 4.2 Global Iteration 1 - Number of Nodes with overlaps = 231 - Number of Nodes with overlaps = 180 - Number of Nodes with overlaps = 152 - Number of Nodes with overlaps = 92 - Number of Nodes with overlaps = 84 - Number of Nodes with overlaps = 60 - Number of Nodes with overlaps = 44 - Number of Nodes with overlaps = 35 - Number of Nodes with overlaps = 37 - Number of Nodes with overlaps = 28 - Number of Nodes with overlaps = 20 - Number of Nodes with overlaps = 13 - Number of Nodes with overlaps = 9 - Number of Nodes with overlaps = 7 - Number of Nodes with overlaps = 5 - Number of Nodes with overlaps = 4 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.494| TNS=-6783.227| WHS=N/A | THS=N/A | - -Phase 4.2 Global Iteration 1 | Checksum: 2cd491a74 - -Time (s): cpu = 00:05:31 ; elapsed = 00:02:59 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 325 ; free virtual = 5054 - -Phase 4.3 Global Iteration 2 - Number of Nodes with overlaps = 141 - Number of Nodes with overlaps = 144 - Number of Nodes with overlaps = 120 - Number of Nodes with overlaps = 105 - Number of Nodes with overlaps = 121 - Number of Nodes with overlaps = 78 - Number of Nodes with overlaps = 57 - Number of Nodes with overlaps = 48 - Number of Nodes with overlaps = 27 + Number of Nodes with overlaps = 95 + Number of Nodes with overlaps = 43 Number of Nodes with overlaps = 17 - Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 9 - Number of Nodes with overlaps = 10 - Number of Nodes with overlaps = 6 - Number of Nodes with overlaps = 4 - Number of Nodes with overlaps = 4 - Number of Nodes with overlaps = 3 - Number of Nodes with overlaps = 1 - Number of Nodes with overlaps = 1 - Number of Nodes with overlaps = 1 - Number of Nodes with overlaps = 1 - Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 5 + Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.465| TNS=-6794.564| WHS=N/A | THS=N/A | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.255 | TNS=-31.100| WHS=N/A | THS=N/A | -Phase 4.3 Global Iteration 2 | Checksum: 18900c83b +Phase 4.2 Global Iteration 1 | Checksum: 2687e85da -Time (s): cpu = 00:06:35 ; elapsed = 00:03:45 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 242 ; free virtual = 5028 -Phase 4 Rip-up And Reroute | Checksum: 18900c83b +Time (s): cpu = 00:01:33 ; elapsed = 00:00:58 . Memory (MB): peak = 2992.961 ; gain = 150.289 ; free physical = 199 ; free virtual = 2783 +Phase 4 Rip-up And Reroute | Checksum: 2687e85da -Time (s): cpu = 00:06:35 ; elapsed = 00:03:45 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 242 ; free virtual = 5028 +Time (s): cpu = 00:01:33 ; elapsed = 00:00:59 . Memory (MB): peak = 2992.961 ; gain = 150.289 ; free physical = 199 ; free virtual = 2783 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing -Phase 5.1.1 Update Timing | Checksum: 18900c83b +Phase 5.1.1 Update Timing | Checksum: 2fe6ca81b -Time (s): cpu = 00:06:36 ; elapsed = 00:03:45 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 183 ; free virtual = 5022 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.465| TNS=-6794.564| WHS=N/A | THS=N/A | +Time (s): cpu = 00:01:34 ; elapsed = 00:00:59 . Memory (MB): peak = 2992.961 ; gain = 150.289 ; free physical = 199 ; free virtual = 2783 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.252 | TNS=-31.493| WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 -Phase 5.1 Delay CleanUp | Checksum: 1a7ad13b4 +Phase 5.1 Delay CleanUp | Checksum: 187ef8df4 -Time (s): cpu = 00:06:47 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 142 ; free virtual = 5020 +Time (s): cpu = 00:03:37 ; elapsed = 00:01:35 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 136 ; free virtual = 2607 Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 1a7ad13b4 +Phase 5.2 Clock Skew Optimization | Checksum: 187ef8df4 -Time (s): cpu = 00:06:47 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 142 ; free virtual = 5020 -Phase 5 Delay and Skew Optimization | Checksum: 1a7ad13b4 +Time (s): cpu = 00:03:37 ; elapsed = 00:01:35 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 136 ; free virtual = 2607 +Phase 5 Delay and Skew Optimization | Checksum: 187ef8df4 -Time (s): cpu = 00:06:47 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 142 ; free virtual = 5020 +Time (s): cpu = 00:03:37 ; elapsed = 00:01:35 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 136 ; free virtual = 2607 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 1e57763e0 +Phase 6.1.1 Update Timing | Checksum: 1ec99cbab -Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 141 ; free virtual = 5020 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.396| TNS=-6762.388| WHS=0.081 | THS=0.000 | +Time (s): cpu = 00:03:38 ; elapsed = 00:01:36 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 136 ; free virtual = 2608 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.240 | TNS=-22.556| WHS=0.038 | THS=0.000 | -Phase 6.1 Hold Fix Iter | Checksum: 1e57763e0 +Phase 6.1 Hold Fix Iter | Checksum: 23943ec6b -Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 141 ; free virtual = 5020 -Phase 6 Post Hold Fix | Checksum: 1e57763e0 +Time (s): cpu = 00:03:38 ; elapsed = 00:01:36 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 136 ; free virtual = 2608 +Phase 6 Post Hold Fix | Checksum: 23943ec6b -Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 141 ; free virtual = 5020 +Time (s): cpu = 00:03:38 ; elapsed = 00:01:36 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 136 ; free virtual = 2608 Phase 7 Route finalize Router Utilization Summary - Global Vertical Routing Utilization = 1.77316 % - Global Horizontal Routing Utilization = 2.02251 % + Global Vertical Routing Utilization = 0.939418 % + Global Horizontal Routing Utilization = 1.24595 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. @@ -1201,16 +1018,10 @@ Router Utilization Summary --GLOBAL Congestion: Utilization threshold used for congestion level computation: 0.85 Congestion Report -North Dir 1x1 Area, Max Cong = 67.5676%, No Congested Regions. -South Dir 1x1 Area, Max Cong = 80.1802%, No Congested Regions. -East Dir 2x2 Area, Max Cong = 91.5441%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): - INT_L_X32Y168 -> INT_R_X33Y169 -West Dir 1x1 Area, Max Cong = 94.1176%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): - INT_L_X28Y189 -> INT_L_X28Y189 - INT_L_X26Y188 -> INT_L_X26Y188 - INT_R_X27Y188 -> INT_R_X27Y188 - INT_L_X28Y187 -> INT_L_X28Y187 - INT_L_X14Y172 -> INT_L_X14Y172 +North Dir 1x1 Area, Max Cong = 50.4505%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 60.3604%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 63.2353%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 52.9412%, No Congested Regions. ------------------------------ Reporting congestion hotspots @@ -1225,52 +1036,52 @@ Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: East ---------------- -Congested clusters found at Level 1 -Effective congestion level: 2 Aspect Ratio: 0.5 Sparse Ratio: 0.5 +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: West ---------------- Congested clusters found at Level 0 -Effective congestion level: 1 Aspect Ratio: 0.5 Sparse Ratio: 0.5 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Phase 7 Route finalize | Checksum: 1e57763e0 +Phase 7 Route finalize | Checksum: 23943ec6b -Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 133 ; free virtual = 5020 +Time (s): cpu = 00:03:38 ; elapsed = 00:01:36 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 136 ; free virtual = 2607 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 1e57763e0 +Phase 8 Verifying routed nets | Checksum: 23943ec6b -Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 128 ; free virtual = 5019 +Time (s): cpu = 00:03:38 ; elapsed = 00:01:36 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 136 ; free virtual = 2607 Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 26293a506 +Phase 9 Depositing Routes | Checksum: 1ef2bc857 -Time (s): cpu = 00:06:50 ; elapsed = 00:03:50 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 243 ; free virtual = 5043 +Time (s): cpu = 00:03:39 ; elapsed = 00:01:37 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 128 ; free virtual = 2600 Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=-17.396| TNS=-6762.388| WHS=0.081 | THS=0.000 | +INFO: [Route 35-57] Estimated Timing Summary | WNS=-1.240 | TNS=-22.556| WHS=0.038 | THS=0.000 | WARNING: [Route 35-328] Router estimated timing not met. Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. -Phase 10 Post Router Timing | Checksum: 26293a506 +Phase 10 Post Router Timing | Checksum: 1ef2bc857 -Time (s): cpu = 00:06:51 ; elapsed = 00:03:51 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 224 ; free virtual = 5039 +Time (s): cpu = 00:03:41 ; elapsed = 00:01:37 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 127 ; free virtual = 2599 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing -Phase 11 Post-Route Event Processing | Checksum: 123c431d6 +Phase 11 Post-Route Event Processing | Checksum: 105362d16 -Time (s): cpu = 00:06:51 ; elapsed = 00:03:51 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 193 ; free virtual = 5030 -Ending Routing Task | Checksum: 123c431d6 +Time (s): cpu = 00:03:41 ; elapsed = 00:01:38 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 125 ; free virtual = 2599 +Ending Routing Task | Checksum: 105362d16 -Time (s): cpu = 00:06:51 ; elapsed = 00:03:51 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 193 ; free virtual = 5030 +Time (s): cpu = 00:03:41 ; elapsed = 00:01:38 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 125 ; free virtual = 2599 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation -435 Infos, 109 Warnings, 0 Critical Warnings and 0 Errors encountered. +295 Infos, 110 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:06:55 ; elapsed = 00:03:53 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 137 ; free virtual = 5047 +route_design: Time (s): cpu = 00:03:46 ; elapsed = 00:01:40 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 109 ; free virtual = 2596 INFO: [runtcl-4] Executing : report_drc -file filter_drc_routed.rpt -pb filter_drc_routed.pb -rpx filter_drc_routed.rpx Command: report_drc -file filter_drc_routed.rpt -pb filter_drc_routed.pb -rpx filter_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. @@ -1286,6 +1097,7 @@ Resolution: Set the HD.CLK_SRC property of the out-of-context port to the locati INFO: [DRC 23-133] Running Methodology with 4 threads INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.rpt. report_methodology completed successfully +report_methodology: Time (s): cpu = 00:00:12 ; elapsed = 00:00:05 . Memory (MB): peak = 3209.988 ; gain = 0.000 ; free physical = 197 ; free virtual = 2603 INFO: [runtcl-4] Executing : report_power -file filter_power_routed.rpt -pb filter_power_summary_routed.pb -rpx filter_power_routed.rpx Command: report_power -file filter_power_routed.rpt -pb filter_power_summary_routed.pb -rpx filter_power_routed.rpx WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] @@ -1293,7 +1105,7 @@ INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation -445 Infos, 112 Warnings, 0 Critical Warnings and 0 Errors encountered. +305 Infos, 113 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully INFO: [runtcl-4] Executing : report_route_status -file filter_route_status.rpt -pb filter_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_routed.rpt -pb filter_timing_summary_routed.pb -rpx filter_timing_summary_routed.rpx -warn_on_violation @@ -1307,15 +1119,15 @@ INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file filter_bus INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 154 ; free virtual = 4924 -Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.94 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 198 ; free virtual = 4894 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 199 ; free virtual = 4893 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3209.988 ; gain = 0.000 ; free physical = 129 ; free virtual = 2580 +Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.77 . Memory (MB): peak = 3209.988 ; gain = 0.000 ; free physical = 119 ; free virtual = 2577 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3209.988 ; gain = 0.000 ; free physical = 119 ; free virtual = 2577 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.36 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 183 ; free virtual = 4881 -Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 183 ; free virtual = 4881 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 182 ; free virtual = 4881 -Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 182 ; free virtual = 4881 +Wrote RouteStorage: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3209.988 ; gain = 0.000 ; free physical = 118 ; free virtual = 2577 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3209.988 ; gain = 0.000 ; free physical = 117 ; free virtual = 2577 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3209.988 ; gain = 0.000 ; free physical = 117 ; free virtual = 2577 +Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.96 . Memory (MB): peak = 3209.988 ; gain = 0.000 ; free physical = 117 ; free virtual = 2577 INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_routed.dcp' has been generated. -INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 18:58:43 2023... +INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 21:20:46 2023... diff --git a/synth/filter_vivado.runs/impl_1/filter_bus_skew_routed.rpt b/synth/filter_vivado.runs/impl_1/filter_bus_skew_routed.rpt index 6c51a8f..a4387d1 100644 --- a/synth/filter_vivado.runs/impl_1/filter_bus_skew_routed.rpt +++ b/synth/filter_vivado.runs/impl_1/filter_bus_skew_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 -| Date : Sun Dec 3 18:58:41 2023 +| Date : Sun Dec 3 21:20:44 2023 | Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux | Command : report_bus_skew -warn_on_violation -file filter_bus_skew_routed.rpt -pb filter_bus_skew_routed.pb -rpx filter_bus_skew_routed.rpx | Design : filter diff --git a/synth/filter_vivado.runs/impl_1/filter_bus_skew_routed.rpx b/synth/filter_vivado.runs/impl_1/filter_bus_skew_routed.rpx index dbdfc84..fd19eaa 100644 Binary files a/synth/filter_vivado.runs/impl_1/filter_bus_skew_routed.rpx and b/synth/filter_vivado.runs/impl_1/filter_bus_skew_routed.rpx differ diff --git a/synth/filter_vivado.runs/impl_1/filter_clock_utilization_routed.rpt b/synth/filter_vivado.runs/impl_1/filter_clock_utilization_routed.rpt index 57d06e7..8e6dfd3 100644 --- a/synth/filter_vivado.runs/impl_1/filter_clock_utilization_routed.rpt +++ b/synth/filter_vivado.runs/impl_1/filter_clock_utilization_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 -| Date : Sun Dec 3 18:58:41 2023 +| Date : Sun Dec 3 21:20:44 2023 | Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux | Command : report_clock_utilization -file filter_clock_utilization_routed.rpt | Design : filter diff --git a/synth/filter_vivado.runs/impl_1/filter_control_sets_placed.rpt b/synth/filter_vivado.runs/impl_1/filter_control_sets_placed.rpt index e88ee81..fed7246 100644 --- a/synth/filter_vivado.runs/impl_1/filter_control_sets_placed.rpt +++ b/synth/filter_vivado.runs/impl_1/filter_control_sets_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 -| Date : Sun Dec 3 18:54:00 2023 +| Date : Sun Dec 3 21:18:40 2023 | Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux | Command : report_control_sets -verbose -file filter_control_sets_placed.rpt | Design : filter @@ -27,7 +27,7 @@ Table of Contents | Minimum number of control sets | 2 | | Addition due to synthesis replication | 0 | | Addition due to physical synthesis replication | 0 | -| Unused register locations in slices containing registers | 5 | +| Unused register locations in slices containing registers | 9 | +----------------------------------------------------------+-------+ * Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers ** Run report_qor_suggestions for automated merging and remapping suggestions @@ -58,9 +58,9 @@ Table of Contents +--------------+-----------------------+------------------------+-----------------+--------------+ | Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | +--------------+-----------------------+------------------------+-----------------+--------------+ -| No | No | No | 559 | 206 | +| No | No | No | 4835 | 1097 | | No | No | Yes | 0 | 0 | -| No | Yes | No | 4 | 2 | +| No | Yes | No | 4 | 3 | | Yes | No | No | 0 | 0 | | Yes | No | Yes | 0 | 0 | | Yes | Yes | No | 0 | 0 | @@ -73,8 +73,8 @@ Table of Contents +--------------+---------------+------------------+------------------+----------------+--------------+ | Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice | +--------------+---------------+------------------+------------------+----------------+--------------+ -| CLK | | RESET | 2 | 4 | 2.00 | -| CLK | | | 206 | 559 | 2.71 | +| CLK | | RESET | 3 | 4 | 1.33 | +| CLK | | | 1098 | 4996 | 4.55 | +--------------+---------------+------------------+------------------+----------------+--------------+ diff --git a/synth/filter_vivado.runs/impl_1/filter_drc_opted.rpt b/synth/filter_vivado.runs/impl_1/filter_drc_opted.rpt index 907b2c3..ad0ff4d 100644 --- a/synth/filter_vivado.runs/impl_1/filter_drc_opted.rpt +++ b/synth/filter_vivado.runs/impl_1/filter_drc_opted.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 -| Date : Sun Dec 3 18:52:45 2023 +| Date : Sun Dec 3 21:17:27 2023 | Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux | Command : report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx | Design : filter diff --git a/synth/filter_vivado.runs/impl_1/filter_drc_routed.rpt b/synth/filter_vivado.runs/impl_1/filter_drc_routed.rpt index 4b93a7c..9b726be 100644 --- a/synth/filter_vivado.runs/impl_1/filter_drc_routed.rpt +++ b/synth/filter_vivado.runs/impl_1/filter_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 -| Date : Sun Dec 3 18:58:32 2023 +| Date : Sun Dec 3 21:20:35 2023 | Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux | Command : report_drc -file filter_drc_routed.rpt -pb filter_drc_routed.pb -rpx filter_drc_routed.rpx | Design : filter diff --git a/synth/filter_vivado.runs/impl_1/filter_io_placed.rpt b/synth/filter_vivado.runs/impl_1/filter_io_placed.rpt index 7bf6f97..a16373c 100644 --- a/synth/filter_vivado.runs/impl_1/filter_io_placed.rpt +++ b/synth/filter_vivado.runs/impl_1/filter_io_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 -| Date : Sun Dec 3 18:53:59 2023 +| Date : Sun Dec 3 21:18:40 2023 | Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux | Command : report_io -file filter_io_placed.rpt | Design : filter diff --git a/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.pb b/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.pb index d81c0b8..beaf05e 100644 Binary files a/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.pb and b/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.pb differ diff --git a/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.rpt b/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.rpt index 831db44..0adeb17 100644 --- a/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.rpt +++ b/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 -| Date : Sun Dec 3 18:58:37 2023 +| Date : Sun Dec 3 21:20:40 2023 | Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux | Command : report_methodology -file filter_methodology_drc_routed.rpt -pb filter_methodology_drc_routed.pb -rpx filter_methodology_drc_routed.rpx | Design : filter @@ -23,11 +23,11 @@ Table of Contents Floorplan: design_1 Design limits: Max violations: - Violations found: 856 + Violations found: 443 +-----------+----------+------------------------------------------+------------+ | Rule | Severity | Description | Violations | +-----------+----------+------------------------------------------+------------+ -| TIMING-16 | Warning | Large setup violation | 420 | +| TIMING-16 | Warning | Large setup violation | 7 | | XDCH-2 | Warning | Same min and max delay values on IO port | 436 | +-----------+----------+------------------------------------------+------------+ @@ -35,2102 +35,37 @@ Table of Contents ----------------- TIMING-16#1 Warning Large setup violation -There is a large setup violation of -1.008 ns between registered_config.cfg_item_reg[5]/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRARDADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +There is a large setup violation of -1.024 ns between storage_generate[1].storage/memory_reg_2/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[8]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture Related violations: TIMING-16#2 Warning Large setup violation -There is a large setup violation of -1.058 ns between registered_config.cfg_item_reg[8]/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRARDADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +There is a large setup violation of -1.030 ns between storage_generate[3].storage/memory_reg_3/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[10]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture Related violations: TIMING-16#3 Warning Large setup violation -There is a large setup violation of -1.090 ns between registered_config.cfg_item_reg[3]/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRARDADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +There is a large setup violation of -1.045 ns between storage_generate[2].storage/memory_reg_0/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[12]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture Related violations: TIMING-16#4 Warning Large setup violation -There is a large setup violation of -1.093 ns between registered_config.cfg_item_reg[3]/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRARDADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +There is a large setup violation of -1.047 ns between storage_generate[3].storage/memory_reg_3/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[15]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture Related violations: TIMING-16#5 Warning Large setup violation -There is a large setup violation of -1.098 ns between registered_config.cfg_item_reg[6]/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRARDADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +There is a large setup violation of -1.051 ns between storage_generate[3].storage/memory_reg_3/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[11]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture Related violations: TIMING-16#6 Warning Large setup violation -There is a large setup violation of -1.391 ns between registered_config.cfg_item_reg[3]/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRARDADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +There is a large setup violation of -1.144 ns between storage_generate[1].storage/memory_reg_2/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[1]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture Related violations: TIMING-16#7 Warning Large setup violation -There is a large setup violation of -1.689 ns between registered_config.cfg_item_reg[3]/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRARDADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#8 Warning -Large setup violation -There is a large setup violation of -16.019 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#9 Warning -Large setup violation -There is a large setup violation of -16.078 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#10 Warning -Large setup violation -There is a large setup violation of -16.094 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#11 Warning -Large setup violation -There is a large setup violation of -16.121 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#12 Warning -Large setup violation -There is a large setup violation of -16.136 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#13 Warning -Large setup violation -There is a large setup violation of -16.158 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#14 Warning -Large setup violation -There is a large setup violation of -16.198 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#15 Warning -Large setup violation -There is a large setup violation of -16.239 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[3] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#16 Warning -Large setup violation -There is a large setup violation of -16.254 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#17 Warning -Large setup violation -There is a large setup violation of -16.258 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#18 Warning -Large setup violation -There is a large setup violation of -16.275 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[3] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#19 Warning -Large setup violation -There is a large setup violation of -16.281 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#20 Warning -Large setup violation -There is a large setup violation of -16.288 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#21 Warning -Large setup violation -There is a large setup violation of -16.299 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#22 Warning -Large setup violation -There is a large setup violation of -16.302 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#23 Warning -Large setup violation -There is a large setup violation of -16.316 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#24 Warning -Large setup violation -There is a large setup violation of -16.322 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#25 Warning -Large setup violation -There is a large setup violation of -16.332 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#26 Warning -Large setup violation -There is a large setup violation of -16.338 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#27 Warning -Large setup violation -There is a large setup violation of -16.358 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#28 Warning -Large setup violation -There is a large setup violation of -16.372 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#29 Warning -Large setup violation -There is a large setup violation of -16.385 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#30 Warning -Large setup violation -There is a large setup violation of -16.388 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#31 Warning -Large setup violation -There is a large setup violation of -16.411 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#32 Warning -Large setup violation -There is a large setup violation of -16.412 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#33 Warning -Large setup violation -There is a large setup violation of -16.413 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#34 Warning -Large setup violation -There is a large setup violation of -16.414 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#35 Warning -Large setup violation -There is a large setup violation of -16.419 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#36 Warning -Large setup violation -There is a large setup violation of -16.429 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#37 Warning -Large setup violation -There is a large setup violation of -16.447 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#38 Warning -Large setup violation -There is a large setup violation of -16.451 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#39 Warning -Large setup violation -There is a large setup violation of -16.463 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#40 Warning -Large setup violation -There is a large setup violation of -16.466 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#41 Warning -Large setup violation -There is a large setup violation of -16.468 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#42 Warning -Large setup violation -There is a large setup violation of -16.470 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#43 Warning -Large setup violation -There is a large setup violation of -16.475 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#44 Warning -Large setup violation -There is a large setup violation of -16.478 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#45 Warning -Large setup violation -There is a large setup violation of -16.485 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#46 Warning -Large setup violation -There is a large setup violation of -16.487 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#47 Warning -Large setup violation -There is a large setup violation of -16.488 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#48 Warning -Large setup violation -There is a large setup violation of -16.491 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#49 Warning -Large setup violation -There is a large setup violation of -16.492 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#50 Warning -Large setup violation -There is a large setup violation of -16.501 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#51 Warning -Large setup violation -There is a large setup violation of -16.503 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#52 Warning -Large setup violation -There is a large setup violation of -16.507 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#53 Warning -Large setup violation -There is a large setup violation of -16.511 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#54 Warning -Large setup violation -There is a large setup violation of -16.513 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#55 Warning -Large setup violation -There is a large setup violation of -16.527 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#56 Warning -Large setup violation -There is a large setup violation of -16.528 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#57 Warning -Large setup violation -There is a large setup violation of -16.528 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#58 Warning -Large setup violation -There is a large setup violation of -16.528 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#59 Warning -Large setup violation -There is a large setup violation of -16.533 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#60 Warning -Large setup violation -There is a large setup violation of -16.535 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#61 Warning -Large setup violation -There is a large setup violation of -16.536 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#62 Warning -Large setup violation -There is a large setup violation of -16.544 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#63 Warning -Large setup violation -There is a large setup violation of -16.544 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#64 Warning -Large setup violation -There is a large setup violation of -16.548 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#65 Warning -Large setup violation -There is a large setup violation of -16.550 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#66 Warning -Large setup violation -There is a large setup violation of -16.551 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#67 Warning -Large setup violation -There is a large setup violation of -16.558 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#68 Warning -Large setup violation -There is a large setup violation of -16.558 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#69 Warning -Large setup violation -There is a large setup violation of -16.561 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#70 Warning -Large setup violation -There is a large setup violation of -16.563 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#71 Warning -Large setup violation -There is a large setup violation of -16.564 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#72 Warning -Large setup violation -There is a large setup violation of -16.564 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#73 Warning -Large setup violation -There is a large setup violation of -16.566 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#74 Warning -Large setup violation -There is a large setup violation of -16.570 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#75 Warning -Large setup violation -There is a large setup violation of -16.572 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#76 Warning -Large setup violation -There is a large setup violation of -16.578 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#77 Warning -Large setup violation -There is a large setup violation of -16.580 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#78 Warning -Large setup violation -There is a large setup violation of -16.582 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#79 Warning -Large setup violation -There is a large setup violation of -16.597 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#80 Warning -Large setup violation -There is a large setup violation of -16.597 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#81 Warning -Large setup violation -There is a large setup violation of -16.604 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#82 Warning -Large setup violation -There is a large setup violation of -16.606 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#83 Warning -Large setup violation -There is a large setup violation of -16.607 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#84 Warning -Large setup violation -There is a large setup violation of -16.610 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#85 Warning -Large setup violation -There is a large setup violation of -16.614 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#86 Warning -Large setup violation -There is a large setup violation of -16.618 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#87 Warning -Large setup violation -There is a large setup violation of -16.619 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_2/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#88 Warning -Large setup violation -There is a large setup violation of -16.619 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#89 Warning -Large setup violation -There is a large setup violation of -16.621 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#90 Warning -Large setup violation -There is a large setup violation of -16.622 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#91 Warning -Large setup violation -There is a large setup violation of -16.624 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#92 Warning -Large setup violation -There is a large setup violation of -16.624 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#93 Warning -Large setup violation -There is a large setup violation of -16.632 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#94 Warning -Large setup violation -There is a large setup violation of -16.632 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#95 Warning -Large setup violation -There is a large setup violation of -16.633 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#96 Warning -Large setup violation -There is a large setup violation of -16.636 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#97 Warning -Large setup violation -There is a large setup violation of -16.638 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#98 Warning -Large setup violation -There is a large setup violation of -16.643 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#99 Warning -Large setup violation -There is a large setup violation of -16.643 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#100 Warning -Large setup violation -There is a large setup violation of -16.645 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_3/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#101 Warning -Large setup violation -There is a large setup violation of -16.648 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_6/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#102 Warning -Large setup violation -There is a large setup violation of -16.653 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#103 Warning -Large setup violation -There is a large setup violation of -16.659 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#104 Warning -Large setup violation -There is a large setup violation of -16.663 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#105 Warning -Large setup violation -There is a large setup violation of -16.665 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#106 Warning -Large setup violation -There is a large setup violation of -16.666 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#107 Warning -Large setup violation -There is a large setup violation of -16.668 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#108 Warning -Large setup violation -There is a large setup violation of -16.675 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#109 Warning -Large setup violation -There is a large setup violation of -16.677 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#110 Warning -Large setup violation -There is a large setup violation of -16.678 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[3] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#111 Warning -Large setup violation -There is a large setup violation of -16.679 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#112 Warning -Large setup violation -There is a large setup violation of -16.679 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#113 Warning -Large setup violation -There is a large setup violation of -16.680 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#114 Warning -Large setup violation -There is a large setup violation of -16.680 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#115 Warning -Large setup violation -There is a large setup violation of -16.682 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#116 Warning -Large setup violation -There is a large setup violation of -16.682 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#117 Warning -Large setup violation -There is a large setup violation of -16.685 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#118 Warning -Large setup violation -There is a large setup violation of -16.685 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#119 Warning -Large setup violation -There is a large setup violation of -16.686 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_5/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#120 Warning -Large setup violation -There is a large setup violation of -16.688 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#121 Warning -Large setup violation -There is a large setup violation of -16.689 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#122 Warning -Large setup violation -There is a large setup violation of -16.691 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#123 Warning -Large setup violation -There is a large setup violation of -16.693 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#124 Warning -Large setup violation -There is a large setup violation of -16.697 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#125 Warning -Large setup violation -There is a large setup violation of -16.698 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#126 Warning -Large setup violation -There is a large setup violation of -16.700 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#127 Warning -Large setup violation -There is a large setup violation of -16.702 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#128 Warning -Large setup violation -There is a large setup violation of -16.705 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[3] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#129 Warning -Large setup violation -There is a large setup violation of -16.707 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#130 Warning -Large setup violation -There is a large setup violation of -16.708 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#131 Warning -Large setup violation -There is a large setup violation of -16.713 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#132 Warning -Large setup violation -There is a large setup violation of -16.714 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#133 Warning -Large setup violation -There is a large setup violation of -16.715 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#134 Warning -Large setup violation -There is a large setup violation of -16.716 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#135 Warning -Large setup violation -There is a large setup violation of -16.719 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#136 Warning -Large setup violation -There is a large setup violation of -16.720 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#137 Warning -Large setup violation -There is a large setup violation of -16.725 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#138 Warning -Large setup violation -There is a large setup violation of -16.732 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#139 Warning -Large setup violation -There is a large setup violation of -16.744 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#140 Warning -Large setup violation -There is a large setup violation of -16.747 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#141 Warning -Large setup violation -There is a large setup violation of -16.749 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#142 Warning -Large setup violation -There is a large setup violation of -16.751 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#143 Warning -Large setup violation -There is a large setup violation of -16.753 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#144 Warning -Large setup violation -There is a large setup violation of -16.757 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#145 Warning -Large setup violation -There is a large setup violation of -16.758 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#146 Warning -Large setup violation -There is a large setup violation of -16.759 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#147 Warning -Large setup violation -There is a large setup violation of -16.759 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#148 Warning -Large setup violation -There is a large setup violation of -16.760 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#149 Warning -Large setup violation -There is a large setup violation of -16.762 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#150 Warning -Large setup violation -There is a large setup violation of -16.765 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#151 Warning -Large setup violation -There is a large setup violation of -16.767 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_0/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#152 Warning -Large setup violation -There is a large setup violation of -16.767 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#153 Warning -Large setup violation -There is a large setup violation of -16.771 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#154 Warning -Large setup violation -There is a large setup violation of -16.771 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#155 Warning -Large setup violation -There is a large setup violation of -16.771 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#156 Warning -Large setup violation -There is a large setup violation of -16.774 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#157 Warning -Large setup violation -There is a large setup violation of -16.774 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#158 Warning -Large setup violation -There is a large setup violation of -16.774 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#159 Warning -Large setup violation -There is a large setup violation of -16.776 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#160 Warning -Large setup violation -There is a large setup violation of -16.777 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#161 Warning -Large setup violation -There is a large setup violation of -16.781 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#162 Warning -Large setup violation -There is a large setup violation of -16.785 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#163 Warning -Large setup violation -There is a large setup violation of -16.786 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#164 Warning -Large setup violation -There is a large setup violation of -16.787 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#165 Warning -Large setup violation -There is a large setup violation of -16.788 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#166 Warning -Large setup violation -There is a large setup violation of -16.789 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#167 Warning -Large setup violation -There is a large setup violation of -16.789 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#168 Warning -Large setup violation -There is a large setup violation of -16.790 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_7/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#169 Warning -Large setup violation -There is a large setup violation of -16.792 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#170 Warning -Large setup violation -There is a large setup violation of -16.793 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#171 Warning -Large setup violation -There is a large setup violation of -16.793 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_3/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#172 Warning -Large setup violation -There is a large setup violation of -16.795 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_1/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#173 Warning -Large setup violation -There is a large setup violation of -16.796 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#174 Warning -Large setup violation -There is a large setup violation of -16.804 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#175 Warning -Large setup violation -There is a large setup violation of -16.807 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#176 Warning -Large setup violation -There is a large setup violation of -16.807 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#177 Warning -Large setup violation -There is a large setup violation of -16.807 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#178 Warning -Large setup violation -There is a large setup violation of -16.809 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#179 Warning -Large setup violation -There is a large setup violation of -16.810 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#180 Warning -Large setup violation -There is a large setup violation of -16.811 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#181 Warning -Large setup violation -There is a large setup violation of -16.814 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#182 Warning -Large setup violation -There is a large setup violation of -16.815 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#183 Warning -Large setup violation -There is a large setup violation of -16.816 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#184 Warning -Large setup violation -There is a large setup violation of -16.818 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#185 Warning -Large setup violation -There is a large setup violation of -16.820 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#186 Warning -Large setup violation -There is a large setup violation of -16.822 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_8/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#187 Warning -Large setup violation -There is a large setup violation of -16.822 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#188 Warning -Large setup violation -There is a large setup violation of -16.824 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#189 Warning -Large setup violation -There is a large setup violation of -16.827 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_8/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#190 Warning -Large setup violation -There is a large setup violation of -16.830 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#191 Warning -Large setup violation -There is a large setup violation of -16.830 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#192 Warning -Large setup violation -There is a large setup violation of -16.833 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#193 Warning -Large setup violation -There is a large setup violation of -16.835 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#194 Warning -Large setup violation -There is a large setup violation of -16.836 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#195 Warning -Large setup violation -There is a large setup violation of -16.838 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#196 Warning -Large setup violation -There is a large setup violation of -16.842 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#197 Warning -Large setup violation -There is a large setup violation of -16.844 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#198 Warning -Large setup violation -There is a large setup violation of -16.847 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#199 Warning -Large setup violation -There is a large setup violation of -16.847 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#200 Warning -Large setup violation -There is a large setup violation of -16.847 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#201 Warning -Large setup violation -There is a large setup violation of -16.851 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#202 Warning -Large setup violation -There is a large setup violation of -16.862 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#203 Warning -Large setup violation -There is a large setup violation of -16.867 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#204 Warning -Large setup violation -There is a large setup violation of -16.869 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#205 Warning -Large setup violation -There is a large setup violation of -16.871 ns between registered_input.in_key_reg[67]/C (clocked by CLK) and storage_generate[3].storage/memory_reg_4/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#206 Warning -Large setup violation -There is a large setup violation of -16.875 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#207 Warning -Large setup violation -There is a large setup violation of -16.879 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#208 Warning -Large setup violation -There is a large setup violation of -16.881 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#209 Warning -Large setup violation -There is a large setup violation of -16.888 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#210 Warning -Large setup violation -There is a large setup violation of -16.892 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#211 Warning -Large setup violation -There is a large setup violation of -16.897 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#212 Warning -Large setup violation -There is a large setup violation of -16.898 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#213 Warning -Large setup violation -There is a large setup violation of -16.903 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#214 Warning -Large setup violation -There is a large setup violation of -16.906 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#215 Warning -Large setup violation -There is a large setup violation of -16.908 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#216 Warning -Large setup violation -There is a large setup violation of -16.915 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#217 Warning -Large setup violation -There is a large setup violation of -16.917 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#218 Warning -Large setup violation -There is a large setup violation of -16.918 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#219 Warning -Large setup violation -There is a large setup violation of -16.918 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#220 Warning -Large setup violation -There is a large setup violation of -16.920 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#221 Warning -Large setup violation -There is a large setup violation of -16.930 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#222 Warning -Large setup violation -There is a large setup violation of -16.930 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#223 Warning -Large setup violation -There is a large setup violation of -16.933 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_6/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#224 Warning -Large setup violation -There is a large setup violation of -16.935 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#225 Warning -Large setup violation -There is a large setup violation of -16.935 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#226 Warning -Large setup violation -There is a large setup violation of -16.936 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#227 Warning -Large setup violation -There is a large setup violation of -16.945 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#228 Warning -Large setup violation -There is a large setup violation of -16.946 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#229 Warning -Large setup violation -There is a large setup violation of -16.948 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#230 Warning -Large setup violation -There is a large setup violation of -16.949 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#231 Warning -Large setup violation -There is a large setup violation of -16.950 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#232 Warning -Large setup violation -There is a large setup violation of -16.951 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#233 Warning -Large setup violation -There is a large setup violation of -16.953 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#234 Warning -Large setup violation -There is a large setup violation of -16.954 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#235 Warning -Large setup violation -There is a large setup violation of -16.955 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#236 Warning -Large setup violation -There is a large setup violation of -16.956 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#237 Warning -Large setup violation -There is a large setup violation of -16.957 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#238 Warning -Large setup violation -There is a large setup violation of -16.958 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#239 Warning -Large setup violation -There is a large setup violation of -16.960 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#240 Warning -Large setup violation -There is a large setup violation of -16.964 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#241 Warning -Large setup violation -There is a large setup violation of -16.965 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#242 Warning -Large setup violation -There is a large setup violation of -16.966 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#243 Warning -Large setup violation -There is a large setup violation of -16.969 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#244 Warning -Large setup violation -There is a large setup violation of -16.969 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[4] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#245 Warning -Large setup violation -There is a large setup violation of -16.969 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#246 Warning -Large setup violation -There is a large setup violation of -16.970 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#247 Warning -Large setup violation -There is a large setup violation of -16.972 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#248 Warning -Large setup violation -There is a large setup violation of -16.973 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#249 Warning -Large setup violation -There is a large setup violation of -16.975 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#250 Warning -Large setup violation -There is a large setup violation of -16.983 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#251 Warning -Large setup violation -There is a large setup violation of -16.984 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#252 Warning -Large setup violation -There is a large setup violation of -16.985 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#253 Warning -Large setup violation -There is a large setup violation of -16.986 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#254 Warning -Large setup violation -There is a large setup violation of -16.986 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#255 Warning -Large setup violation -There is a large setup violation of -16.986 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#256 Warning -Large setup violation -There is a large setup violation of -16.988 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#257 Warning -Large setup violation -There is a large setup violation of -16.989 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#258 Warning -Large setup violation -There is a large setup violation of -16.994 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#259 Warning -Large setup violation -There is a large setup violation of -16.996 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#260 Warning -Large setup violation -There is a large setup violation of -16.996 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#261 Warning -Large setup violation -There is a large setup violation of -17.002 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#262 Warning -Large setup violation -There is a large setup violation of -17.008 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#263 Warning -Large setup violation -There is a large setup violation of -17.009 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#264 Warning -Large setup violation -There is a large setup violation of -17.014 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#265 Warning -Large setup violation -There is a large setup violation of -17.014 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#266 Warning -Large setup violation -There is a large setup violation of -17.014 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#267 Warning -Large setup violation -There is a large setup violation of -17.015 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#268 Warning -Large setup violation -There is a large setup violation of -17.016 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#269 Warning -Large setup violation -There is a large setup violation of -17.017 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#270 Warning -Large setup violation -There is a large setup violation of -17.017 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#271 Warning -Large setup violation -There is a large setup violation of -17.017 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#272 Warning -Large setup violation -There is a large setup violation of -17.022 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#273 Warning -Large setup violation -There is a large setup violation of -17.023 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#274 Warning -Large setup violation -There is a large setup violation of -17.025 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#275 Warning -Large setup violation -There is a large setup violation of -17.033 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_4/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#276 Warning -Large setup violation -There is a large setup violation of -17.033 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#277 Warning -Large setup violation -There is a large setup violation of -17.034 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#278 Warning -Large setup violation -There is a large setup violation of -17.035 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#279 Warning -Large setup violation -There is a large setup violation of -17.044 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#280 Warning -Large setup violation -There is a large setup violation of -17.054 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#281 Warning -Large setup violation -There is a large setup violation of -17.056 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#282 Warning -Large setup violation -There is a large setup violation of -17.058 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#283 Warning -Large setup violation -There is a large setup violation of -17.060 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#284 Warning -Large setup violation -There is a large setup violation of -17.060 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_1/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#285 Warning -Large setup violation -There is a large setup violation of -17.061 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#286 Warning -Large setup violation -There is a large setup violation of -17.062 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#287 Warning -Large setup violation -There is a large setup violation of -17.063 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#288 Warning -Large setup violation -There is a large setup violation of -17.063 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#289 Warning -Large setup violation -There is a large setup violation of -17.065 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#290 Warning -Large setup violation -There is a large setup violation of -17.067 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#291 Warning -Large setup violation -There is a large setup violation of -17.068 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#292 Warning -Large setup violation -There is a large setup violation of -17.070 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#293 Warning -Large setup violation -There is a large setup violation of -17.074 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#294 Warning -Large setup violation -There is a large setup violation of -17.076 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#295 Warning -Large setup violation -There is a large setup violation of -17.076 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#296 Warning -Large setup violation -There is a large setup violation of -17.076 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#297 Warning -Large setup violation -There is a large setup violation of -17.078 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#298 Warning -Large setup violation -There is a large setup violation of -17.078 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#299 Warning -Large setup violation -There is a large setup violation of -17.079 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#300 Warning -Large setup violation -There is a large setup violation of -17.081 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#301 Warning -Large setup violation -There is a large setup violation of -17.081 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#302 Warning -Large setup violation -There is a large setup violation of -17.082 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#303 Warning -Large setup violation -There is a large setup violation of -17.083 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#304 Warning -Large setup violation -There is a large setup violation of -17.083 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[5] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#305 Warning -Large setup violation -There is a large setup violation of -17.083 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#306 Warning -Large setup violation -There is a large setup violation of -17.087 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#307 Warning -Large setup violation -There is a large setup violation of -17.089 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#308 Warning -Large setup violation -There is a large setup violation of -17.091 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#309 Warning -Large setup violation -There is a large setup violation of -17.093 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#310 Warning -Large setup violation -There is a large setup violation of -17.094 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#311 Warning -Large setup violation -There is a large setup violation of -17.094 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#312 Warning -Large setup violation -There is a large setup violation of -17.095 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#313 Warning -Large setup violation -There is a large setup violation of -17.097 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#314 Warning -Large setup violation -There is a large setup violation of -17.097 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#315 Warning -Large setup violation -There is a large setup violation of -17.099 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#316 Warning -Large setup violation -There is a large setup violation of -17.105 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#317 Warning -Large setup violation -There is a large setup violation of -17.107 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#318 Warning -Large setup violation -There is a large setup violation of -17.108 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#319 Warning -Large setup violation -There is a large setup violation of -17.110 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#320 Warning -Large setup violation -There is a large setup violation of -17.110 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#321 Warning -Large setup violation -There is a large setup violation of -17.111 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#322 Warning -Large setup violation -There is a large setup violation of -17.112 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#323 Warning -Large setup violation -There is a large setup violation of -17.114 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#324 Warning -Large setup violation -There is a large setup violation of -17.118 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#325 Warning -Large setup violation -There is a large setup violation of -17.123 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#326 Warning -Large setup violation -There is a large setup violation of -17.123 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_5/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#327 Warning -Large setup violation -There is a large setup violation of -17.124 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_4/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#328 Warning -Large setup violation -There is a large setup violation of -17.128 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_7/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#329 Warning -Large setup violation -There is a large setup violation of -17.131 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#330 Warning -Large setup violation -There is a large setup violation of -17.131 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#331 Warning -Large setup violation -There is a large setup violation of -17.132 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#332 Warning -Large setup violation -There is a large setup violation of -17.134 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#333 Warning -Large setup violation -There is a large setup violation of -17.136 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#334 Warning -Large setup violation -There is a large setup violation of -17.136 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#335 Warning -Large setup violation -There is a large setup violation of -17.144 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#336 Warning -Large setup violation -There is a large setup violation of -17.148 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#337 Warning -Large setup violation -There is a large setup violation of -17.149 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#338 Warning -Large setup violation -There is a large setup violation of -17.149 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#339 Warning -Large setup violation -There is a large setup violation of -17.150 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#340 Warning -Large setup violation -There is a large setup violation of -17.152 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#341 Warning -Large setup violation -There is a large setup violation of -17.152 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#342 Warning -Large setup violation -There is a large setup violation of -17.153 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#343 Warning -Large setup violation -There is a large setup violation of -17.155 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#344 Warning -Large setup violation -There is a large setup violation of -17.158 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#345 Warning -Large setup violation -There is a large setup violation of -17.158 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#346 Warning -Large setup violation -There is a large setup violation of -17.159 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#347 Warning -Large setup violation -There is a large setup violation of -17.162 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#348 Warning -Large setup violation -There is a large setup violation of -17.162 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#349 Warning -Large setup violation -There is a large setup violation of -17.163 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_5/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#350 Warning -Large setup violation -There is a large setup violation of -17.164 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_2/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#351 Warning -Large setup violation -There is a large setup violation of -17.165 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#352 Warning -Large setup violation -There is a large setup violation of -17.166 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#353 Warning -Large setup violation -There is a large setup violation of -17.170 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#354 Warning -Large setup violation -There is a large setup violation of -17.173 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#355 Warning -Large setup violation -There is a large setup violation of -17.176 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#356 Warning -Large setup violation -There is a large setup violation of -17.178 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[6] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#357 Warning -Large setup violation -There is a large setup violation of -17.183 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#358 Warning -Large setup violation -There is a large setup violation of -17.186 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#359 Warning -Large setup violation -There is a large setup violation of -17.186 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#360 Warning -Large setup violation -There is a large setup violation of -17.187 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#361 Warning -Large setup violation -There is a large setup violation of -17.190 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#362 Warning -Large setup violation -There is a large setup violation of -17.192 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#363 Warning -Large setup violation -There is a large setup violation of -17.199 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#364 Warning -Large setup violation -There is a large setup violation of -17.202 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#365 Warning -Large setup violation -There is a large setup violation of -17.203 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#366 Warning -Large setup violation -There is a large setup violation of -17.208 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#367 Warning -Large setup violation -There is a large setup violation of -17.211 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#368 Warning -Large setup violation -There is a large setup violation of -17.212 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#369 Warning -Large setup violation -There is a large setup violation of -17.213 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#370 Warning -Large setup violation -There is a large setup violation of -17.213 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_8/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#371 Warning -Large setup violation -There is a large setup violation of -17.214 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#372 Warning -Large setup violation -There is a large setup violation of -17.214 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#373 Warning -Large setup violation -There is a large setup violation of -17.214 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#374 Warning -Large setup violation -There is a large setup violation of -17.215 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_3/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#375 Warning -Large setup violation -There is a large setup violation of -17.216 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_6/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#376 Warning -Large setup violation -There is a large setup violation of -17.218 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#377 Warning -Large setup violation -There is a large setup violation of -17.219 ns between registered_input.in_key_reg[7]/C (clocked by CLK) and storage_generate[0].storage/memory_reg_0/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#378 Warning -Large setup violation -There is a large setup violation of -17.226 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[7] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#379 Warning -Large setup violation -There is a large setup violation of -17.226 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#380 Warning -Large setup violation -There is a large setup violation of -17.228 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#381 Warning -Large setup violation -There is a large setup violation of -17.233 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#382 Warning -Large setup violation -There is a large setup violation of -17.235 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#383 Warning -Large setup violation -There is a large setup violation of -17.241 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#384 Warning -Large setup violation -There is a large setup violation of -17.245 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#385 Warning -Large setup violation -There is a large setup violation of -17.250 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#386 Warning -Large setup violation -There is a large setup violation of -17.258 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#387 Warning -Large setup violation -There is a large setup violation of -17.265 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#388 Warning -Large setup violation -There is a large setup violation of -17.273 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#389 Warning -Large setup violation -There is a large setup violation of -17.282 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[12] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#390 Warning -Large setup violation -There is a large setup violation of -17.283 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[8] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#391 Warning -Large setup violation -There is a large setup violation of -17.288 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#392 Warning -Large setup violation -There is a large setup violation of -17.290 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#393 Warning -Large setup violation -There is a large setup violation of -17.291 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#394 Warning -Large setup violation -There is a large setup violation of -17.298 ns between registered_input.in_key_reg[65]/C (clocked by CLK) and storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#395 Warning -Large setup violation -There is a large setup violation of -17.309 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#396 Warning -Large setup violation -There is a large setup violation of -17.310 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[10] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#397 Warning -Large setup violation -There is a large setup violation of -17.330 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#398 Warning -Large setup violation -There is a large setup violation of -17.331 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#399 Warning -Large setup violation -There is a large setup violation of -17.335 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#400 Warning -Large setup violation -There is a large setup violation of -17.342 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[14] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#401 Warning -Large setup violation -There is a large setup violation of -17.363 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[9] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#402 Warning -Large setup violation -There is a large setup violation of -17.364 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[11] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#403 Warning -Large setup violation -There is a large setup violation of -17.396 ns between registered_input.in_key_reg[64]_replica_5/C (clocked by CLK) and storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[13] (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#404 Warning -Large setup violation -There is a large setup violation of -2.635 ns between storage_generate[3].storage/memory_reg_4/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_KEY_FOUND_reg/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#405 Warning -Large setup violation -There is a large setup violation of -3.138 ns between storage_generate[2].storage/memory_reg_2/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[4]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#406 Warning -Large setup violation -There is a large setup violation of -3.260 ns between storage_generate[2].storage/memory_reg_2/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[10]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#407 Warning -Large setup violation -There is a large setup violation of -3.277 ns between storage_generate[2].storage/memory_reg_2/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[12]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#408 Warning -Large setup violation -There is a large setup violation of -3.324 ns between storage_generate[1].storage/memory_reg_1/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[3]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#409 Warning -Large setup violation -There is a large setup violation of -3.340 ns between storage_generate[2].storage/memory_reg_2/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[7]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#410 Warning -Large setup violation -There is a large setup violation of -3.352 ns between storage_generate[1].storage/memory_reg_1/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[15]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#411 Warning -Large setup violation -There is a large setup violation of -3.354 ns between storage_generate[1].storage/memory_reg_1/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[13]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#412 Warning -Large setup violation -There is a large setup violation of -3.511 ns between storage_generate[1].storage/memory_reg_1/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[1]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#413 Warning -Large setup violation -There is a large setup violation of -3.513 ns between storage_generate[1].storage/memory_reg_1/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[5]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#414 Warning -Large setup violation -There is a large setup violation of -3.520 ns between storage_generate[2].storage/memory_reg_2/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[9]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#415 Warning -Large setup violation -There is a large setup violation of -3.533 ns between storage_generate[1].storage/memory_reg_1/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[11]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#416 Warning -Large setup violation -There is a large setup violation of -3.554 ns between storage_generate[1].storage/memory_reg_1/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[0]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#417 Warning -Large setup violation -There is a large setup violation of -3.592 ns between storage_generate[2].storage/memory_reg_2/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[8]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#418 Warning -Large setup violation -There is a large setup violation of -3.609 ns between storage_generate[2].storage/memory_reg_2/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[14]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#419 Warning -Large setup violation -There is a large setup violation of -3.810 ns between storage_generate[1].storage/memory_reg_1/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[2]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture -Related violations: - -TIMING-16#420 Warning -Large setup violation -There is a large setup violation of -3.961 ns between storage_generate[1].storage/memory_reg_1/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_DATA_reg[6]/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture +There is a large setup violation of -1.240 ns between storage_generate[2].storage/memory_reg_0/CLKBWRCLK (clocked by CLK) and registered_output.OUTPUT_KEY_FOUND_reg/D (clocked by CLK). Large setup violations at the end of those stages might be difficult to fix during the post-placement implementation flow and could be the result of non-optimal XDC constraints or non-optimal design architecture Related violations: XDCH-2#1 Warning diff --git a/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.rpx b/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.rpx index c0a455d..ce4a586 100644 Binary files a/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.rpx and b/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.rpx differ diff --git a/synth/filter_vivado.runs/impl_1/filter_opt.dcp b/synth/filter_vivado.runs/impl_1/filter_opt.dcp index 1e8c71e..d7d4c8a 100644 Binary files a/synth/filter_vivado.runs/impl_1/filter_opt.dcp and b/synth/filter_vivado.runs/impl_1/filter_opt.dcp differ diff --git a/synth/filter_vivado.runs/impl_1/filter_physopt.dcp b/synth/filter_vivado.runs/impl_1/filter_physopt.dcp index aefe4f3..d62d08a 100644 Binary files a/synth/filter_vivado.runs/impl_1/filter_physopt.dcp and b/synth/filter_vivado.runs/impl_1/filter_physopt.dcp differ diff --git a/synth/filter_vivado.runs/impl_1/filter_placed.dcp b/synth/filter_vivado.runs/impl_1/filter_placed.dcp index a6f4539..44668ce 100644 Binary files a/synth/filter_vivado.runs/impl_1/filter_placed.dcp and b/synth/filter_vivado.runs/impl_1/filter_placed.dcp differ diff --git a/synth/filter_vivado.runs/impl_1/filter_power_routed.rpt b/synth/filter_vivado.runs/impl_1/filter_power_routed.rpt index 5b6ccba..6283102 100644 --- a/synth/filter_vivado.runs/impl_1/filter_power_routed.rpt +++ b/synth/filter_vivado.runs/impl_1/filter_power_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 -| Date : Sun Dec 3 18:58:40 2023 +| Date : Sun Dec 3 21:20:43 2023 | Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux | Command : report_power -file filter_power_routed.rpt -pb filter_power_summary_routed.pb -rpx filter_power_routed.rpx | Design : filter @@ -30,14 +30,14 @@ Table of Contents ---------- +--------------------------+--------------+ -| Total On-Chip Power (W) | 0.790 | +| Total On-Chip Power (W) | 0.689 | | Design Power Budget (W) | Unspecified* | | Power Budget Margin (W) | NA | -| Dynamic (W) | 0.675 | +| Dynamic (W) | 0.575 | | Device Static (W) | 0.114 | | Effective TJA (C/W) | 1.9 | -| Max Ambient (C) | 83.5 | -| Junction Temperature (C) | 26.5 | +| Max Ambient (C) | 83.7 | +| Junction Temperature (C) | 26.3 | | Confidence Level | Medium | | Setting File | --- | | Simulation Activity File | --- | @@ -49,20 +49,21 @@ Table of Contents 1.1 On-Chip Components ---------------------- -+----------------+-----------+----------+-----------+-----------------+ -| On-Chip | Power (W) | Used | Available | Utilization (%) | -+----------------+-----------+----------+-----------+-----------------+ -| Clocks | 0.024 | 3 | --- | --- | -| Slice Logic | 0.175 | 5524 | --- | --- | -| LUT as Logic | 0.163 | 3508 | 101400 | 3.46 | -| CARRY4 | 0.012 | 681 | 25350 | 2.69 | -| Register | <0.001 | 597 | 202800 | 0.29 | -| Others | 0.000 | 34 | --- | --- | -| Signals | 0.270 | 5168 | --- | --- | -| Block RAM | 0.206 | 34 | 325 | 10.46 | -| Static Power | 0.114 | | | | -| Total | 0.790 | | | | -+----------------+-----------+----------+-----------+-----------------+ ++-------------------------+-----------+----------+-----------+-----------------+ +| On-Chip | Power (W) | Used | Available | Utilization (%) | ++-------------------------+-----------+----------+-----------+-----------------+ +| Clocks | 0.096 | 3 | --- | --- | +| Slice Logic | 0.127 | 10142 | --- | --- | +| LUT as Logic | 0.101 | 3625 | 101400 | 3.57 | +| CARRY4 | 0.013 | 745 | 25350 | 2.94 | +| Register | 0.012 | 4839 | 202800 | 2.39 | +| LUT as Shift Register | <0.001 | 82 | 35000 | 0.23 | +| Others | 0.000 | 34 | --- | --- | +| Signals | 0.147 | 7074 | --- | --- | +| Block RAM | 0.206 | 34 | 325 | 10.46 | +| Static Power | 0.114 | | | | +| Total | 0.689 | | | | ++-------------------------+-----------+----------+-----------+-----------------+ 1.2 Power Supply Summary @@ -71,7 +72,7 @@ Table of Contents +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ | Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) | +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+ -| Vccint | 1.000 | 0.703 | 0.660 | 0.043 | NA | Unspecified | NA | +| Vccint | 1.000 | 0.602 | 0.559 | 0.043 | NA | Unspecified | NA | | Vccaux | 1.800 | 0.018 | 0.000 | 0.018 | NA | Unspecified | NA | | Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | | Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA | @@ -141,23 +142,23 @@ Table of Contents +-------------------------------+-----------+ | Name | Power (W) | +-------------------------------+-----------+ -| filter | 0.675 | -| hash_generate[0].hash | 0.100 | -| final | 0.023 | -| mix_pipeline[0].mix | 0.076 | -| hash_generate[1].hash | 0.105 | -| final | 0.023 | -| mix_pipeline[0].mix | 0.081 | -| hash_generate[2].hash | 0.101 | -| final | 0.022 | -| mix_pipeline[0].mix | 0.079 | -| hash_generate[3].hash | 0.102 | -| final | 0.024 | -| mix_pipeline[0].mix | 0.072 | +| filter | 0.575 | +| hash_generate[0].hash | 0.083 | +| final | 0.033 | +| mix_pipeline[0].mix | 0.050 | +| hash_generate[1].hash | 0.083 | +| final | 0.034 | +| mix_pipeline[0].mix | 0.048 | +| hash_generate[2].hash | 0.078 | +| final | 0.031 | +| mix_pipeline[0].mix | 0.047 | +| hash_generate[3].hash | 0.079 | +| final | 0.031 | +| mix_pipeline[0].mix | 0.046 | | storage_generate[0].storage | 0.057 | -| storage_generate[1].storage | 0.059 | +| storage_generate[1].storage | 0.058 | | storage_generate[2].storage | 0.057 | -| storage_generate[3].storage | 0.057 | +| storage_generate[3].storage | 0.056 | +-------------------------------+-----------+ diff --git a/synth/filter_vivado.runs/impl_1/filter_power_routed.rpx b/synth/filter_vivado.runs/impl_1/filter_power_routed.rpx index d388c7c..3ed3267 100644 Binary files a/synth/filter_vivado.runs/impl_1/filter_power_routed.rpx and b/synth/filter_vivado.runs/impl_1/filter_power_routed.rpx differ diff --git a/synth/filter_vivado.runs/impl_1/filter_power_summary_routed.pb b/synth/filter_vivado.runs/impl_1/filter_power_summary_routed.pb index 653fd54..9cc152a 100644 Binary files a/synth/filter_vivado.runs/impl_1/filter_power_summary_routed.pb and b/synth/filter_vivado.runs/impl_1/filter_power_summary_routed.pb differ diff --git a/synth/filter_vivado.runs/impl_1/filter_reports.tcl b/synth/filter_vivado.runs/impl_1/filter_reports.tcl deleted file mode 100644 index 296f467..0000000 --- a/synth/filter_vivado.runs/impl_1/filter_reports.tcl +++ /dev/null @@ -1,129 +0,0 @@ -# -# Report generation script generated by Vivado -# - -proc create_report { reportName command } { - set status "." - append status $reportName ".fail" - if { [file exists $status] } { - eval file delete [glob $status] - } - send_msg_id runtcl-4 info "Executing : $command" - set retval [eval catch { $command } msg] - if { $retval != 0 } { - set fp [open $status w] - close $fp - send_msg_id runtcl-5 warning "$msg" - } -} -namespace eval ::optrace { - variable script "/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_reports.tcl" - variable category "vivado_impl" -} - -# Try to connect to running dispatch if we haven't done so already. -# This code assumes that the Tcl interpreter is not using threads, -# since the ::dispatch::connected variable isn't mutex protected. -if {![info exists ::dispatch::connected]} { - namespace eval ::dispatch { - variable connected false - if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} { - set result "true" - if {[catch { - if {[lsearch -exact [package names] DispatchTcl] < 0} { - set result [load librdi_cd_clienttcl[info sharedlibextension]] - } - if {$result eq "false"} { - puts "WARNING: Could not load dispatch client library" - } - set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ] - if { $connect_id eq "" } { - puts "WARNING: Could not initialize dispatch client" - } else { - puts "INFO: Dispatch client connection id - $connect_id" - set connected true - } - } catch_res]} { - puts "WARNING: failed to connect to dispatch server - $catch_res" - } - } - } -} -if {$::dispatch::connected} { - # Remove the dummy proc if it exists. - if { [expr {[llength [info procs ::OPTRACE]] > 0}] } { - rename ::OPTRACE "" - } - proc ::OPTRACE { task action {tags {} } } { - ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category - } - # dispatch is generic. We specifically want to attach logging. - ::vitis_log::connect_client -} else { - # Add dummy proc if it doesn't exist. - if { [expr {[llength [info procs ::OPTRACE]] == 0}] } { - proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} { - # Do nothing - } - } -} - -proc start_step { step } { - set stopFile ".stop.rst" - if {[file isfile .stop.rst]} { - puts "" - puts "*** Halting run - EA reset detected ***" - puts "" - puts "" - return -code error - } - set beginFile ".$step.begin.rst" - set platform "$::tcl_platform(platform)" - set user "$::tcl_platform(user)" - set pid [pid] - set host "" - if { [string equal $platform unix] } { - if { [info exist ::env(HOSTNAME)] } { - set host $::env(HOSTNAME) - } elseif { [info exist ::env(HOST)] } { - set host $::env(HOST) - } - } else { - if { [info exist ::env(COMPUTERNAME)] } { - set host $::env(COMPUTERNAME) - } - } - set ch [open $beginFile w] - puts $ch "" - puts $ch "" - puts $ch " " - puts $ch " " - puts $ch "" - close $ch -} - -proc end_step { step } { - set endFile ".$step.end.rst" - set ch [open $endFile w] - close $ch -} - -proc step_failed { step } { - set endFile ".$step.error.rst" - set ch [open $endFile w] - close $ch -OPTRACE "impl_1" END { } -} - -set_msg_config -id {Synth 8-256} -limit 10000 -set_msg_config -id {Synth 8-638} -limit 10000 - -if {$argv == "opt_design"} { - set retval [open_checkpoint filter_opt.dcp] - if { $retval == "checkpoint_filter_opt" } { - create_report "impl_1_opt_report_timing_summary_0" "report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_opted.rpt -pb filter_timing_summary_opted.pb -rpx filter_timing_summary_opted.rpx" - - close_design - } -} - diff --git a/synth/filter_vivado.runs/impl_1/filter_route_status.pb b/synth/filter_vivado.runs/impl_1/filter_route_status.pb index b57c662..d624378 100644 Binary files a/synth/filter_vivado.runs/impl_1/filter_route_status.pb and b/synth/filter_vivado.runs/impl_1/filter_route_status.pb differ diff --git a/synth/filter_vivado.runs/impl_1/filter_route_status.rpt b/synth/filter_vivado.runs/impl_1/filter_route_status.rpt index 2bdcb2b..6b6e22e 100644 --- a/synth/filter_vivado.runs/impl_1/filter_route_status.rpt +++ b/synth/filter_vivado.runs/impl_1/filter_route_status.rpt @@ -1,12 +1,12 @@ Design Route Status : # nets : ------------------------------------------- : ----------- : - # of logical nets.......................... : 8803 : - # of nets not needing routing.......... : 3633 : - # of internally routed nets........ : 3197 : + # of logical nets.......................... : 13669 : + # of nets not needing routing.......... : 6593 : + # of internally routed nets........ : 6157 : # of implicitly routed ports....... : 436 : - # of routable nets..................... : 5170 : - # of fully routed nets............. : 5170 : + # of routable nets..................... : 7076 : + # of fully routed nets............. : 7076 : # of nets with routing errors.......... : 0 : ------------------------------------------- : ----------- : diff --git a/synth/filter_vivado.runs/impl_1/filter_routed.dcp b/synth/filter_vivado.runs/impl_1/filter_routed.dcp index fec1c74..841ee8a 100644 Binary files a/synth/filter_vivado.runs/impl_1/filter_routed.dcp and b/synth/filter_vivado.runs/impl_1/filter_routed.dcp differ diff --git a/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.pb b/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.pb index 78fa794..72df1be 100644 Binary files a/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.pb and b/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.pb differ diff --git a/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.rpt b/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.rpt index 3f03922..ce3f3fd 100644 --- a/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.rpt +++ b/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 -| Date : Sun Dec 3 19:06:33 2023 +| Date : Sun Dec 3 21:17:29 2023 | Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux | Command : report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_opted.rpt -pb filter_timing_summary_opted.pb -rpx filter_timing_summary_opted.rpx | Design : filter @@ -138,7 +138,7 @@ Table of Contents WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - -14.185 -5464.168 413 2121 0.190 0.000 0 2121 1.505 0.000 0 635 + -0.708 -12.012 17 6513 0.169 0.000 0 6513 1.220 0.000 0 5027 Timing constraints are not met. @@ -161,7 +161,7 @@ CLK {0.000 2.000} 4.000 250.000 Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -CLK -14.185 -5464.168 413 2121 0.190 0.000 0 2121 1.505 0.000 0 635 +CLK -0.708 -12.012 17 6513 0.169 0.000 0 6513 1.220 0.000 0 5027 ------------------------------------------------------------------------------------------------ @@ -210,24 +210,24 @@ Path Group From Clock To Clock From Clock: CLK To Clock: CLK -Setup : 413 Failing Endpoints, Worst Slack -14.185ns, Total Violation -5464.168ns -Hold : 0 Failing Endpoints, Worst Slack 0.190ns, Total Violation 0.000ns -PW : 0 Failing Endpoints, Worst Slack 1.505ns, Total Violation 0.000ns +Setup : 17 Failing Endpoints, Worst Slack -0.708ns, Total Violation -12.012ns +Hold : 0 Failing Endpoints, Worst Slack 0.169ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.220ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (VIOLATED) : -14.185ns (required time - arrival time) - Source: registered_input.in_key_reg[3]/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[13] +Slack (VIOLATED) : -0.708ns (required time - arrival time) + Source: storage_generate[2].storage/memory_reg_1/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[0]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) - Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Data Path Delay: 4.688ns (logic 3.345ns (71.359%) route 1.343ns (28.641%)) + Logic Levels: 14 (CARRY4=11 LUT6=3) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) Source Clock Delay (SCD): 0.672ns @@ -242,360 +242,77 @@ Slack (VIOLATED) : -14.185ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.672 0.672 CLK - FDRE r registered_input.in_key_reg[3]/C - ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q - net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] - CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] - net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] - net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 - LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O - net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] - net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] - LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O - net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] - net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] - net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] - LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O - net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 - LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O - net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] - net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] - net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] - LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O - net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 - CARRY4 (Prop_carry4_S[1]_O[2]) - 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] - net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] - LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O - net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] - LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O - net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 - CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] - net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] - net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O - net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] - net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] - net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] - LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O - net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] - CARRY4 (Prop_carry4_DI[1]_CO[3]) - 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 - CARRY4 (Prop_carry4_CI_O[2]) - 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] - net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] - LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O - net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] - net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] - LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O - net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] - LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O - net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] - LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O - net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 - CARRY4 (Prop_carry4_CI_O[3]) - 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] - net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 - LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O - net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] - net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] - net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 - LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O - net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] - net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] - net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] - RAMB36E1 r storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[13] - ------------------------------------------------------------------- ------------------- - - (clock CLK rise edge) 4.000 4.000 r - 0.000 4.000 r CLK (IN) - net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK - RAMB36E1 r storage_generate[2].storage/memory_reg_0/CLKBWRCLK - clock pessimism 0.000 4.638 - clock uncertainty -0.035 4.603 - RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) - -0.578 4.025 storage_generate[2].storage/memory_reg_0 - ------------------------------------------------------------------- - required time 4.025 - arrival time -18.210 - ------------------------------------------------------------------- - slack -14.185 - -Slack (VIOLATED) : -14.185ns (required time - arrival time) - Source: registered_input.in_key_reg[3]/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[13] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Path Group: CLK - Path Type: Setup (Max at Slow Process Corner) - Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) - Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) - Source Clock Delay (SCD): 0.672ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.000ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock CLK rise edge) 0.000 0.000 r - 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.672 0.672 CLK - FDRE r registered_input.in_key_reg[3]/C - ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q - net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] - CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] - net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] - net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 - LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O - net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] - net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] - LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O - net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] - net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] - net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] - LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O - net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 - LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O - net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] - net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] - net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] - LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O - net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 - CARRY4 (Prop_carry4_S[1]_O[2]) - 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] - net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] - LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O - net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] - LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O - net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 - CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] - net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] - net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O - net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] - net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] - net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] - LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O - net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] - CARRY4 (Prop_carry4_DI[1]_CO[3]) - 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 - CARRY4 (Prop_carry4_CI_O[2]) - 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] - net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] - LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O - net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] - net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] - LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O - net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] - LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O - net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] - LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O - net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 - CARRY4 (Prop_carry4_CI_O[3]) - 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] - net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 - LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O - net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] - net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] - net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 - LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O - net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] - net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] - net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] - RAMB36E1 r storage_generate[2].storage/memory_reg_1/ADDRBWRADDR[13] - ------------------------------------------------------------------- ------------------- - - (clock CLK rise edge) 4.000 4.000 r - 0.000 4.000 r CLK (IN) - net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK + net (fo=5026, unset) 0.672 0.672 storage_generate[2].storage/CLK RAMB36E1 r storage_generate[2].storage/memory_reg_1/CLKBWRCLK + ------------------------------------------------------------------- ------------------- + RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[3]) + 2.080 2.752 r storage_generate[2].storage/memory_reg_1/DOBDO[3] + net (fo=1, unplaced) 0.584 3.336 storage_generate[2].storage/memory_rule[2][21] + LUT6 (Prop_lut6_I4_O) 0.053 3.389 r storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55/O + net (fo=1, unplaced) 0.000 3.389 storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.699 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48/CO[3] + net (fo=1, unplaced) 0.008 3.707 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 3.767 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43/CO[3] + net (fo=1, unplaced) 0.000 3.767 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 3.827 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38/CO[3] + net (fo=1, unplaced) 0.000 3.827 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 3.887 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33/CO[3] + net (fo=1, unplaced) 0.000 3.887 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 3.947 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28/CO[3] + net (fo=1, unplaced) 0.000 3.947 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 4.007 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23/CO[3] + net (fo=1, unplaced) 0.000 4.007 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 4.067 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18/CO[3] + net (fo=1, unplaced) 0.000 4.067 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 4.127 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13/CO[3] + net (fo=1, unplaced) 0.000 4.127 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 4.187 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8/CO[3] + net (fo=1, unplaced) 0.000 4.187 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 4.247 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4/CO[3] + net (fo=1, unplaced) 0.000 4.247 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4_n_0 + CARRY4 (Prop_carry4_CI_CO[2]) + 0.149 4.396 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_2/CO[2] + net (fo=33, unplaced) 0.411 4.807 storage_generate[1].storage/CO[0] + LUT6 (Prop_lut6_I4_O) 0.160 4.967 r storage_generate[1].storage/registered_output.OUTPUT_DATA[0]_i_2/O + net (fo=1, unplaced) 0.340 5.307 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[0]_0 + LUT6 (Prop_lut6_I5_O) 0.053 5.360 r storage_generate[2].storage/registered_output.OUTPUT_DATA[0]_i_1/O + net (fo=1, unplaced) 0.000 5.360 out_data[0] + FDRE r registered_output.OUTPUT_DATA_reg[0]/D + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=5026, unset) 0.638 4.638 CLK + FDRE r registered_output.OUTPUT_DATA_reg[0]/C clock pessimism 0.000 4.638 clock uncertainty -0.035 4.603 - RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) - -0.578 4.025 storage_generate[2].storage/memory_reg_1 + FDRE (Setup_fdre_C_D) 0.049 4.652 registered_output.OUTPUT_DATA_reg[0] ------------------------------------------------------------------- - required time 4.025 - arrival time -18.210 + required time 4.652 + arrival time -5.360 ------------------------------------------------------------------- - slack -14.185 + slack -0.708 -Slack (VIOLATED) : -14.185ns (required time - arrival time) - Source: registered_input.in_key_reg[3]/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[13] +Slack (VIOLATED) : -0.708ns (required time - arrival time) + Source: storage_generate[2].storage/memory_reg_1/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[10]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) - Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Data Path Delay: 4.688ns (logic 3.345ns (71.359%) route 1.343ns (28.641%)) + Logic Levels: 14 (CARRY4=11 LUT6=3) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) Source Clock Delay (SCD): 0.672ns @@ -610,176 +327,77 @@ Slack (VIOLATED) : -14.185ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.672 0.672 CLK - FDRE r registered_input.in_key_reg[3]/C + net (fo=5026, unset) 0.672 0.672 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_1/CLKBWRCLK ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q - net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] - CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] - net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] - net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 - LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O - net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[3]) + 2.080 2.752 r storage_generate[2].storage/memory_reg_1/DOBDO[3] + net (fo=1, unplaced) 0.584 3.336 storage_generate[2].storage/memory_rule[2][21] + LUT6 (Prop_lut6_I4_O) 0.053 3.389 r storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55/O + net (fo=1, unplaced) 0.000 3.389 storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55_n_0 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] - net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] - LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O - net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] - net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] - net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] - LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O - net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 - LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O - net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] - net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] - net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] - LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O - net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 - CARRY4 (Prop_carry4_S[1]_O[2]) - 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] - net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] - LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O - net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] - LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O - net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 - CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] - net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] - net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O - net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] - net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] - net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] - LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O - net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] - CARRY4 (Prop_carry4_DI[1]_CO[3]) - 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 - CARRY4 (Prop_carry4_CI_O[2]) - 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] - net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] - LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O - net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] - net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] - LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O - net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] - LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O - net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + 0.310 3.699 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48/CO[3] + net (fo=1, unplaced) 0.008 3.707 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + 0.060 3.767 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43/CO[3] + net (fo=1, unplaced) 0.000 3.767 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + 0.060 3.827 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38/CO[3] + net (fo=1, unplaced) 0.000 3.827 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + 0.060 3.887 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33/CO[3] + net (fo=1, unplaced) 0.000 3.887 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + 0.060 3.947 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28/CO[3] + net (fo=1, unplaced) 0.000 3.947 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + 0.060 4.007 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23/CO[3] + net (fo=1, unplaced) 0.000 4.007 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] - LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O - net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + 0.060 4.067 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18/CO[3] + net (fo=1, unplaced) 0.000 4.067 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + 0.060 4.127 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13/CO[3] + net (fo=1, unplaced) 0.000 4.127 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + 0.060 4.187 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8/CO[3] + net (fo=1, unplaced) 0.000 4.187 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 - CARRY4 (Prop_carry4_CI_O[3]) - 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] - net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 - LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O - net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] - net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] - net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 - LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O - net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] - net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] - net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] - RAMB36E1 r storage_generate[2].storage/memory_reg_2/ADDRBWRADDR[13] + 0.060 4.247 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4/CO[3] + net (fo=1, unplaced) 0.000 4.247 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4_n_0 + CARRY4 (Prop_carry4_CI_CO[2]) + 0.149 4.396 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_2/CO[2] + net (fo=33, unplaced) 0.411 4.807 storage_generate[1].storage/CO[0] + LUT6 (Prop_lut6_I4_O) 0.160 4.967 r storage_generate[1].storage/registered_output.OUTPUT_DATA[10]_i_2/O + net (fo=1, unplaced) 0.340 5.307 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[10] + LUT6 (Prop_lut6_I5_O) 0.053 5.360 r storage_generate[2].storage/registered_output.OUTPUT_DATA[10]_i_1/O + net (fo=1, unplaced) 0.000 5.360 out_data[10] + FDRE r registered_output.OUTPUT_DATA_reg[10]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 4.000 4.000 r 0.000 4.000 r CLK (IN) - net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK - RAMB36E1 r storage_generate[2].storage/memory_reg_2/CLKBWRCLK + net (fo=5026, unset) 0.638 4.638 CLK + FDRE r registered_output.OUTPUT_DATA_reg[10]/C clock pessimism 0.000 4.638 clock uncertainty -0.035 4.603 - RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) - -0.578 4.025 storage_generate[2].storage/memory_reg_2 + FDRE (Setup_fdre_C_D) 0.049 4.652 registered_output.OUTPUT_DATA_reg[10] ------------------------------------------------------------------- - required time 4.025 - arrival time -18.210 + required time 4.652 + arrival time -5.360 ------------------------------------------------------------------- - slack -14.185 + slack -0.708 -Slack (VIOLATED) : -14.185ns (required time - arrival time) - Source: registered_input.in_key_reg[3]/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[13] +Slack (VIOLATED) : -0.708ns (required time - arrival time) + Source: storage_generate[2].storage/memory_reg_1/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[11]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) - Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Data Path Delay: 4.688ns (logic 3.345ns (71.359%) route 1.343ns (28.641%)) + Logic Levels: 14 (CARRY4=11 LUT6=3) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) Source Clock Delay (SCD): 0.672ns @@ -794,176 +412,77 @@ Slack (VIOLATED) : -14.185ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.672 0.672 CLK - FDRE r registered_input.in_key_reg[3]/C + net (fo=5026, unset) 0.672 0.672 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_1/CLKBWRCLK ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q - net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] - CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] - net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] - net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 - LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O - net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[3]) + 2.080 2.752 r storage_generate[2].storage/memory_reg_1/DOBDO[3] + net (fo=1, unplaced) 0.584 3.336 storage_generate[2].storage/memory_rule[2][21] + LUT6 (Prop_lut6_I4_O) 0.053 3.389 r storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55/O + net (fo=1, unplaced) 0.000 3.389 storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55_n_0 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] - net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] - LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O - net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] - net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] - net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] - LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O - net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 - LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O - net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] - net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] - net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] - LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O - net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 - CARRY4 (Prop_carry4_S[1]_O[2]) - 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] - net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] - LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O - net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] - LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O - net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 - CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] - net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] - net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O - net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] - net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] - net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] - LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O - net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] - CARRY4 (Prop_carry4_DI[1]_CO[3]) - 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 - CARRY4 (Prop_carry4_CI_O[2]) - 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] - net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] - LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O - net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] - net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] - LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O - net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] - LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O - net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + 0.310 3.699 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48/CO[3] + net (fo=1, unplaced) 0.008 3.707 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + 0.060 3.767 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43/CO[3] + net (fo=1, unplaced) 0.000 3.767 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + 0.060 3.827 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38/CO[3] + net (fo=1, unplaced) 0.000 3.827 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + 0.060 3.887 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33/CO[3] + net (fo=1, unplaced) 0.000 3.887 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + 0.060 3.947 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28/CO[3] + net (fo=1, unplaced) 0.000 3.947 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + 0.060 4.007 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23/CO[3] + net (fo=1, unplaced) 0.000 4.007 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] - LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O - net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + 0.060 4.067 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18/CO[3] + net (fo=1, unplaced) 0.000 4.067 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + 0.060 4.127 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13/CO[3] + net (fo=1, unplaced) 0.000 4.127 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + 0.060 4.187 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8/CO[3] + net (fo=1, unplaced) 0.000 4.187 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 - CARRY4 (Prop_carry4_CI_O[3]) - 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] - net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 - LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O - net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] - net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] - net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 - LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O - net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] - net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] - net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] - RAMB36E1 r storage_generate[2].storage/memory_reg_3/ADDRBWRADDR[13] + 0.060 4.247 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4/CO[3] + net (fo=1, unplaced) 0.000 4.247 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4_n_0 + CARRY4 (Prop_carry4_CI_CO[2]) + 0.149 4.396 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_2/CO[2] + net (fo=33, unplaced) 0.411 4.807 storage_generate[1].storage/CO[0] + LUT6 (Prop_lut6_I4_O) 0.160 4.967 r storage_generate[1].storage/registered_output.OUTPUT_DATA[11]_i_2/O + net (fo=1, unplaced) 0.340 5.307 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[11] + LUT6 (Prop_lut6_I5_O) 0.053 5.360 r storage_generate[2].storage/registered_output.OUTPUT_DATA[11]_i_1/O + net (fo=1, unplaced) 0.000 5.360 out_data[11] + FDRE r registered_output.OUTPUT_DATA_reg[11]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 4.000 4.000 r 0.000 4.000 r CLK (IN) - net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK - RAMB36E1 r storage_generate[2].storage/memory_reg_3/CLKBWRCLK + net (fo=5026, unset) 0.638 4.638 CLK + FDRE r registered_output.OUTPUT_DATA_reg[11]/C clock pessimism 0.000 4.638 clock uncertainty -0.035 4.603 - RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) - -0.578 4.025 storage_generate[2].storage/memory_reg_3 + FDRE (Setup_fdre_C_D) 0.049 4.652 registered_output.OUTPUT_DATA_reg[11] ------------------------------------------------------------------- - required time 4.025 - arrival time -18.210 + required time 4.652 + arrival time -5.360 ------------------------------------------------------------------- - slack -14.185 + slack -0.708 -Slack (VIOLATED) : -14.185ns (required time - arrival time) - Source: registered_input.in_key_reg[3]/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[13] +Slack (VIOLATED) : -0.708ns (required time - arrival time) + Source: storage_generate[2].storage/memory_reg_1/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[12]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) - Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Data Path Delay: 4.688ns (logic 3.345ns (71.359%) route 1.343ns (28.641%)) + Logic Levels: 14 (CARRY4=11 LUT6=3) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) Source Clock Delay (SCD): 0.672ns @@ -978,176 +497,77 @@ Slack (VIOLATED) : -14.185ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.672 0.672 CLK - FDRE r registered_input.in_key_reg[3]/C + net (fo=5026, unset) 0.672 0.672 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_1/CLKBWRCLK ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q - net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] - CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] - net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] - net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 - LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O - net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[3]) + 2.080 2.752 r storage_generate[2].storage/memory_reg_1/DOBDO[3] + net (fo=1, unplaced) 0.584 3.336 storage_generate[2].storage/memory_rule[2][21] + LUT6 (Prop_lut6_I4_O) 0.053 3.389 r storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55/O + net (fo=1, unplaced) 0.000 3.389 storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55_n_0 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] - net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] - LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O - net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] - net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] - net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] - LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O - net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 - LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O - net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] - net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] - net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] - LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O - net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 - CARRY4 (Prop_carry4_S[1]_O[2]) - 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] - net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] - LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O - net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] - LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O - net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 - CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] - net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] - net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O - net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] - net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] - net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] - LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O - net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] - CARRY4 (Prop_carry4_DI[1]_CO[3]) - 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 - CARRY4 (Prop_carry4_CI_O[2]) - 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] - net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] - LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O - net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] - net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] - LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O - net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] - LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O - net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + 0.310 3.699 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48/CO[3] + net (fo=1, unplaced) 0.008 3.707 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + 0.060 3.767 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43/CO[3] + net (fo=1, unplaced) 0.000 3.767 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + 0.060 3.827 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38/CO[3] + net (fo=1, unplaced) 0.000 3.827 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + 0.060 3.887 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33/CO[3] + net (fo=1, unplaced) 0.000 3.887 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + 0.060 3.947 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28/CO[3] + net (fo=1, unplaced) 0.000 3.947 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + 0.060 4.007 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23/CO[3] + net (fo=1, unplaced) 0.000 4.007 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] - LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O - net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + 0.060 4.067 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18/CO[3] + net (fo=1, unplaced) 0.000 4.067 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + 0.060 4.127 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13/CO[3] + net (fo=1, unplaced) 0.000 4.127 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + 0.060 4.187 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8/CO[3] + net (fo=1, unplaced) 0.000 4.187 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 - CARRY4 (Prop_carry4_CI_O[3]) - 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] - net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 - LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O - net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] - net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] - net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 - LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O - net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] - net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] - net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] - RAMB36E1 r storage_generate[2].storage/memory_reg_4/ADDRBWRADDR[13] + 0.060 4.247 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4/CO[3] + net (fo=1, unplaced) 0.000 4.247 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4_n_0 + CARRY4 (Prop_carry4_CI_CO[2]) + 0.149 4.396 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_2/CO[2] + net (fo=33, unplaced) 0.411 4.807 storage_generate[1].storage/CO[0] + LUT6 (Prop_lut6_I4_O) 0.160 4.967 r storage_generate[1].storage/registered_output.OUTPUT_DATA[12]_i_2/O + net (fo=1, unplaced) 0.340 5.307 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[12] + LUT6 (Prop_lut6_I5_O) 0.053 5.360 r storage_generate[2].storage/registered_output.OUTPUT_DATA[12]_i_1/O + net (fo=1, unplaced) 0.000 5.360 out_data[12] + FDRE r registered_output.OUTPUT_DATA_reg[12]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 4.000 4.000 r 0.000 4.000 r CLK (IN) - net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK - RAMB36E1 r storage_generate[2].storage/memory_reg_4/CLKBWRCLK + net (fo=5026, unset) 0.638 4.638 CLK + FDRE r registered_output.OUTPUT_DATA_reg[12]/C clock pessimism 0.000 4.638 clock uncertainty -0.035 4.603 - RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) - -0.578 4.025 storage_generate[2].storage/memory_reg_4 + FDRE (Setup_fdre_C_D) 0.049 4.652 registered_output.OUTPUT_DATA_reg[12] ------------------------------------------------------------------- - required time 4.025 - arrival time -18.210 + required time 4.652 + arrival time -5.360 ------------------------------------------------------------------- - slack -14.185 + slack -0.708 -Slack (VIOLATED) : -14.185ns (required time - arrival time) - Source: registered_input.in_key_reg[3]/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[13] +Slack (VIOLATED) : -0.708ns (required time - arrival time) + Source: storage_generate[2].storage/memory_reg_1/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[13]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) - Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Data Path Delay: 4.688ns (logic 3.345ns (71.359%) route 1.343ns (28.641%)) + Logic Levels: 14 (CARRY4=11 LUT6=3) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) Source Clock Delay (SCD): 0.672ns @@ -1162,176 +582,77 @@ Slack (VIOLATED) : -14.185ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.672 0.672 CLK - FDRE r registered_input.in_key_reg[3]/C + net (fo=5026, unset) 0.672 0.672 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_1/CLKBWRCLK ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q - net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] - CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] - net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] - net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 - LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O - net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[3]) + 2.080 2.752 r storage_generate[2].storage/memory_reg_1/DOBDO[3] + net (fo=1, unplaced) 0.584 3.336 storage_generate[2].storage/memory_rule[2][21] + LUT6 (Prop_lut6_I4_O) 0.053 3.389 r storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55/O + net (fo=1, unplaced) 0.000 3.389 storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55_n_0 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] - net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] - LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O - net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] - net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] - net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] - LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O - net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 - LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O - net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] - net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] - net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] - LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O - net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 - CARRY4 (Prop_carry4_S[1]_O[2]) - 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] - net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] - LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O - net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] - LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O - net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 - CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] - net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] - net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O - net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] - net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] - net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] - LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O - net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] - CARRY4 (Prop_carry4_DI[1]_CO[3]) - 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 - CARRY4 (Prop_carry4_CI_O[2]) - 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] - net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] - LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O - net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] - net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] - LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O - net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] - LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O - net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + 0.310 3.699 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48/CO[3] + net (fo=1, unplaced) 0.008 3.707 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + 0.060 3.767 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43/CO[3] + net (fo=1, unplaced) 0.000 3.767 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + 0.060 3.827 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38/CO[3] + net (fo=1, unplaced) 0.000 3.827 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + 0.060 3.887 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33/CO[3] + net (fo=1, unplaced) 0.000 3.887 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + 0.060 3.947 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28/CO[3] + net (fo=1, unplaced) 0.000 3.947 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + 0.060 4.007 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23/CO[3] + net (fo=1, unplaced) 0.000 4.007 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] - LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O - net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + 0.060 4.067 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18/CO[3] + net (fo=1, unplaced) 0.000 4.067 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + 0.060 4.127 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13/CO[3] + net (fo=1, unplaced) 0.000 4.127 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + 0.060 4.187 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8/CO[3] + net (fo=1, unplaced) 0.000 4.187 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 - CARRY4 (Prop_carry4_CI_O[3]) - 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] - net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 - LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O - net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] - net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] - net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 - LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O - net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] - net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] - net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] - RAMB36E1 r storage_generate[2].storage/memory_reg_5/ADDRBWRADDR[13] + 0.060 4.247 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4/CO[3] + net (fo=1, unplaced) 0.000 4.247 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4_n_0 + CARRY4 (Prop_carry4_CI_CO[2]) + 0.149 4.396 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_2/CO[2] + net (fo=33, unplaced) 0.411 4.807 storage_generate[1].storage/CO[0] + LUT6 (Prop_lut6_I4_O) 0.160 4.967 r storage_generate[1].storage/registered_output.OUTPUT_DATA[13]_i_2/O + net (fo=1, unplaced) 0.340 5.307 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[13] + LUT6 (Prop_lut6_I5_O) 0.053 5.360 r storage_generate[2].storage/registered_output.OUTPUT_DATA[13]_i_1/O + net (fo=1, unplaced) 0.000 5.360 out_data[13] + FDRE r registered_output.OUTPUT_DATA_reg[13]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 4.000 4.000 r 0.000 4.000 r CLK (IN) - net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK - RAMB36E1 r storage_generate[2].storage/memory_reg_5/CLKBWRCLK + net (fo=5026, unset) 0.638 4.638 CLK + FDRE r registered_output.OUTPUT_DATA_reg[13]/C clock pessimism 0.000 4.638 clock uncertainty -0.035 4.603 - RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) - -0.578 4.025 storage_generate[2].storage/memory_reg_5 + FDRE (Setup_fdre_C_D) 0.049 4.652 registered_output.OUTPUT_DATA_reg[13] ------------------------------------------------------------------- - required time 4.025 - arrival time -18.210 + required time 4.652 + arrival time -5.360 ------------------------------------------------------------------- - slack -14.185 + slack -0.708 -Slack (VIOLATED) : -14.185ns (required time - arrival time) - Source: registered_input.in_key_reg[3]/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[13] +Slack (VIOLATED) : -0.708ns (required time - arrival time) + Source: storage_generate[2].storage/memory_reg_1/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[14]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) - Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Data Path Delay: 4.688ns (logic 3.345ns (71.359%) route 1.343ns (28.641%)) + Logic Levels: 14 (CARRY4=11 LUT6=3) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) Source Clock Delay (SCD): 0.672ns @@ -1346,176 +667,77 @@ Slack (VIOLATED) : -14.185ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.672 0.672 CLK - FDRE r registered_input.in_key_reg[3]/C + net (fo=5026, unset) 0.672 0.672 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_1/CLKBWRCLK ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q - net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] - CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] - net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] - net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 - LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O - net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[3]) + 2.080 2.752 r storage_generate[2].storage/memory_reg_1/DOBDO[3] + net (fo=1, unplaced) 0.584 3.336 storage_generate[2].storage/memory_rule[2][21] + LUT6 (Prop_lut6_I4_O) 0.053 3.389 r storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55/O + net (fo=1, unplaced) 0.000 3.389 storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55_n_0 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] - net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] - LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O - net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] - net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] - net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] - LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O - net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 - LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O - net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] - net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] - net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] - LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O - net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 - CARRY4 (Prop_carry4_S[1]_O[2]) - 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] - net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] - LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O - net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] - LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O - net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 - CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] - net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] - net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O - net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] - net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] - net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] - LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O - net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] - CARRY4 (Prop_carry4_DI[1]_CO[3]) - 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 - CARRY4 (Prop_carry4_CI_O[2]) - 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] - net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] - LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O - net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] - net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] - LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O - net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] - LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O - net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + 0.310 3.699 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48/CO[3] + net (fo=1, unplaced) 0.008 3.707 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + 0.060 3.767 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43/CO[3] + net (fo=1, unplaced) 0.000 3.767 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + 0.060 3.827 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38/CO[3] + net (fo=1, unplaced) 0.000 3.827 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + 0.060 3.887 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33/CO[3] + net (fo=1, unplaced) 0.000 3.887 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + 0.060 3.947 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28/CO[3] + net (fo=1, unplaced) 0.000 3.947 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + 0.060 4.007 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23/CO[3] + net (fo=1, unplaced) 0.000 4.007 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] - LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O - net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + 0.060 4.067 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18/CO[3] + net (fo=1, unplaced) 0.000 4.067 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + 0.060 4.127 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13/CO[3] + net (fo=1, unplaced) 0.000 4.127 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + 0.060 4.187 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8/CO[3] + net (fo=1, unplaced) 0.000 4.187 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 - CARRY4 (Prop_carry4_CI_O[3]) - 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] - net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 - LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O - net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] - net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] - net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 - LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O - net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] - net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] - net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] - RAMB36E1 r storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[13] + 0.060 4.247 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4/CO[3] + net (fo=1, unplaced) 0.000 4.247 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4_n_0 + CARRY4 (Prop_carry4_CI_CO[2]) + 0.149 4.396 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_2/CO[2] + net (fo=33, unplaced) 0.411 4.807 storage_generate[1].storage/CO[0] + LUT6 (Prop_lut6_I4_O) 0.160 4.967 r storage_generate[1].storage/registered_output.OUTPUT_DATA[14]_i_2/O + net (fo=1, unplaced) 0.340 5.307 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[14] + LUT6 (Prop_lut6_I5_O) 0.053 5.360 r storage_generate[2].storage/registered_output.OUTPUT_DATA[14]_i_1/O + net (fo=1, unplaced) 0.000 5.360 out_data[14] + FDRE r registered_output.OUTPUT_DATA_reg[14]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 4.000 4.000 r 0.000 4.000 r CLK (IN) - net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK - RAMB36E1 r storage_generate[2].storage/memory_reg_6/CLKBWRCLK + net (fo=5026, unset) 0.638 4.638 CLK + FDRE r registered_output.OUTPUT_DATA_reg[14]/C clock pessimism 0.000 4.638 clock uncertainty -0.035 4.603 - RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) - -0.578 4.025 storage_generate[2].storage/memory_reg_6 + FDRE (Setup_fdre_C_D) 0.049 4.652 registered_output.OUTPUT_DATA_reg[14] ------------------------------------------------------------------- - required time 4.025 - arrival time -18.210 + required time 4.652 + arrival time -5.360 ------------------------------------------------------------------- - slack -14.185 + slack -0.708 -Slack (VIOLATED) : -14.185ns (required time - arrival time) - Source: registered_input.in_key_reg[3]/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[13] +Slack (VIOLATED) : -0.708ns (required time - arrival time) + Source: storage_generate[2].storage/memory_reg_1/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[15]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) - Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Data Path Delay: 4.688ns (logic 3.345ns (71.359%) route 1.343ns (28.641%)) + Logic Levels: 14 (CARRY4=11 LUT6=3) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) Source Clock Delay (SCD): 0.672ns @@ -1530,360 +752,77 @@ Slack (VIOLATED) : -14.185ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.672 0.672 CLK - FDRE r registered_input.in_key_reg[3]/C + net (fo=5026, unset) 0.672 0.672 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_1/CLKBWRCLK ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q - net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] - CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] - net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] - net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 - LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O - net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[3]) + 2.080 2.752 r storage_generate[2].storage/memory_reg_1/DOBDO[3] + net (fo=1, unplaced) 0.584 3.336 storage_generate[2].storage/memory_rule[2][21] + LUT6 (Prop_lut6_I4_O) 0.053 3.389 r storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55/O + net (fo=1, unplaced) 0.000 3.389 storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55_n_0 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] - net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] - LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O - net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] - net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] - net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] - LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O - net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 - LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O - net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] - net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] - net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] - LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O - net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 - CARRY4 (Prop_carry4_S[1]_O[2]) - 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] - net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] - LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O - net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] - LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O - net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 - CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] - net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] - net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O - net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] - net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] - net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] - LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O - net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] - CARRY4 (Prop_carry4_DI[1]_CO[3]) - 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 - CARRY4 (Prop_carry4_CI_O[2]) - 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] - net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] - LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O - net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] - net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] - LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O - net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] - LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O - net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + 0.310 3.699 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48/CO[3] + net (fo=1, unplaced) 0.008 3.707 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + 0.060 3.767 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43/CO[3] + net (fo=1, unplaced) 0.000 3.767 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + 0.060 3.827 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38/CO[3] + net (fo=1, unplaced) 0.000 3.827 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + 0.060 3.887 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33/CO[3] + net (fo=1, unplaced) 0.000 3.887 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + 0.060 3.947 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28/CO[3] + net (fo=1, unplaced) 0.000 3.947 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + 0.060 4.007 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23/CO[3] + net (fo=1, unplaced) 0.000 4.007 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] - LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O - net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + 0.060 4.067 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18/CO[3] + net (fo=1, unplaced) 0.000 4.067 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + 0.060 4.127 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13/CO[3] + net (fo=1, unplaced) 0.000 4.127 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + 0.060 4.187 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8/CO[3] + net (fo=1, unplaced) 0.000 4.187 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 - CARRY4 (Prop_carry4_CI_O[3]) - 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] - net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 - LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O - net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] - net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] - net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 - LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O - net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] - net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] - net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] - RAMB36E1 r storage_generate[2].storage/memory_reg_7/ADDRBWRADDR[13] + 0.060 4.247 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4/CO[3] + net (fo=1, unplaced) 0.000 4.247 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4_n_0 + CARRY4 (Prop_carry4_CI_CO[2]) + 0.149 4.396 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_2/CO[2] + net (fo=33, unplaced) 0.411 4.807 storage_generate[1].storage/CO[0] + LUT6 (Prop_lut6_I4_O) 0.160 4.967 r storage_generate[1].storage/registered_output.OUTPUT_DATA[15]_i_3/O + net (fo=1, unplaced) 0.340 5.307 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_0 + LUT6 (Prop_lut6_I5_O) 0.053 5.360 r storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_1/O + net (fo=1, unplaced) 0.000 5.360 out_data[15] + FDRE r registered_output.OUTPUT_DATA_reg[15]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 4.000 4.000 r 0.000 4.000 r CLK (IN) - net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK - RAMB36E1 r storage_generate[2].storage/memory_reg_7/CLKBWRCLK + net (fo=5026, unset) 0.638 4.638 CLK + FDRE r registered_output.OUTPUT_DATA_reg[15]/C clock pessimism 0.000 4.638 clock uncertainty -0.035 4.603 - RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) - -0.578 4.025 storage_generate[2].storage/memory_reg_7 + FDRE (Setup_fdre_C_D) 0.049 4.652 registered_output.OUTPUT_DATA_reg[15] ------------------------------------------------------------------- - required time 4.025 - arrival time -18.210 + required time 4.652 + arrival time -5.360 ------------------------------------------------------------------- - slack -14.185 + slack -0.708 -Slack (VIOLATED) : -14.185ns (required time - arrival time) - Source: registered_input.in_key_reg[3]/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[12] - (rising edge-triggered cell RAMB18E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Path Group: CLK - Path Type: Setup (Max at Slow Process Corner) - Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 17.538ns (logic 10.027ns (57.174%) route 7.511ns (42.826%)) - Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) - Clock Path Skew: -0.034ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) - Source Clock Delay (SCD): 0.672ns - Clock Pessimism Removal (CPR): 0.000ns - Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE - Total System Jitter (TSJ): 0.071ns - Total Input Jitter (TIJ): 0.000ns - Discrete Jitter (DJ): 0.000ns - Phase Error (PE): 0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock CLK rise edge) 0.000 0.000 r - 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.672 0.672 CLK - FDRE r registered_input.in_key_reg[3]/C - ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q - net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] - CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] - net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] - net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 - LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O - net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] - net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] - LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O - net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] - net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] - net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] - LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O - net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 - LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O - net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] - net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] - net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] - LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O - net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 - CARRY4 (Prop_carry4_S[1]_O[2]) - 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] - net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] - LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O - net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] - LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O - net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 - CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] - net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] - net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O - net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] - net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] - net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] - LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O - net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] - CARRY4 (Prop_carry4_DI[1]_CO[3]) - 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 - CARRY4 (Prop_carry4_CI_O[2]) - 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] - net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] - LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O - net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] - net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] - LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O - net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] - LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O - net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] - LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O - net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 - CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 - CARRY4 (Prop_carry4_CI_O[3]) - 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] - net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 - LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O - net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] - net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] - net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 - LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O - net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] - net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 17.626 r hash_generate[2].hash/final/memory_reg_0_i_2/O[1] - net (fo=9, unplaced) 0.584 18.210 storage_generate[2].storage/O76[9] - RAMB18E1 r storage_generate[2].storage/memory_reg_8/ADDRBWRADDR[12] - ------------------------------------------------------------------- ------------------- - - (clock CLK rise edge) 4.000 4.000 r - 0.000 4.000 r CLK (IN) - net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK - RAMB18E1 r storage_generate[2].storage/memory_reg_8/CLKBWRCLK - clock pessimism 0.000 4.638 - clock uncertainty -0.035 4.603 - RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_ADDRBWRADDR[12]) - -0.578 4.025 storage_generate[2].storage/memory_reg_8 - ------------------------------------------------------------------- - required time 4.025 - arrival time -18.210 - ------------------------------------------------------------------- - slack -14.185 - -Slack (VIOLATED) : -14.110ns (required time - arrival time) - Source: registered_input.in_key_reg[3]/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[12] +Slack (VIOLATED) : -0.708ns (required time - arrival time) + Source: storage_generate[2].storage/memory_reg_1/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[1]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 17.460ns (logic 9.949ns (56.983%) route 7.511ns (43.017%)) - Logic Levels: 51 (CARRY4=36 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Data Path Delay: 4.688ns (logic 3.345ns (71.359%) route 1.343ns (28.641%)) + Logic Levels: 14 (CARRY4=11 LUT6=3) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) Source Clock Delay (SCD): 0.672ns @@ -1898,165 +837,236 @@ Slack (VIOLATED) : -14.110ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.672 0.672 CLK - FDRE r registered_input.in_key_reg[3]/C + net (fo=5026, unset) 0.672 0.672 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_1/CLKBWRCLK ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.281 0.953 r registered_input.in_key_reg[3]/Q - net (fo=6, unplaced) 0.613 1.566 hash_generate[2].hash/mix_pipeline[0].mix/Q[3] - CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.369 1.935 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0/CO[3] - net (fo=1, unplaced) 0.008 1.943 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_898__0_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 2.163 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889/O[1] - net (fo=2, unplaced) 0.463 2.626 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_889_n_6 - LUT2 (Prop_lut2_I0_O) 0.155 2.781 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1/O - net (fo=1, unplaced) 0.000 2.781 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_892__1_n_0 + RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[3]) + 2.080 2.752 r storage_generate[2].storage/memory_reg_1/DOBDO[3] + net (fo=1, unplaced) 0.584 3.336 storage_generate[2].storage/memory_rule[2][21] + LUT6 (Prop_lut6_I4_O) 0.053 3.389 r storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55/O + net (fo=1, unplaced) 0.000 3.389 storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55_n_0 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 3.091 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, unplaced) 0.000 3.091 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 3.311 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[1] - net (fo=12, unplaced) 0.288 3.599 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[9] - LUT3 (Prop_lut3_I1_O) 0.155 3.754 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2/O - net (fo=1, unplaced) 0.000 3.754 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_947__2_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 4.064 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/CO[3] - net (fo=1, unplaced) 0.000 4.064 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 4.284 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_590/O[1] - net (fo=8, unplaced) 0.278 4.562 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[13] - LUT3 (Prop_lut3_I0_O) 0.155 4.717 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_674__0/O - net (fo=10, unplaced) 0.383 5.100 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[65]_2 - LUT6 (Prop_lut6_I3_O) 0.053 5.153 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019/O - net (fo=1, unplaced) 0.000 5.153 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1019_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 5.463 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685/CO[3] - net (fo=1, unplaced) 0.000 5.463 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_685_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 5.683 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[1] - net (fo=8, unplaced) 0.278 5.961 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[16] - LUT5 (Prop_lut5_I4_O) 0.155 6.116 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1/O - net (fo=1, unplaced) 0.000 6.116 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_414__1_n_0 - CARRY4 (Prop_carry4_S[1]_O[2]) - 0.340 6.456 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[2] - net (fo=5, unplaced) 0.367 6.823 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[17] - LUT5 (Prop_lut5_I4_O) 0.152 6.975 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_278/O - net (fo=4, unplaced) 0.364 7.339 hash_generate[2].hash/mix_pipeline[0].mix/s[0][c]13_out[18] - LUT5 (Prop_lut5_I4_O) 0.053 7.392 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1/O - net (fo=1, unplaced) 0.348 7.740 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0 - CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.234 7.974 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/CO[3] - net (fo=1, unplaced) 0.000 7.974 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 8.194 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_731/O[1] - net (fo=4, unplaced) 0.476 8.670 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - LUT5 (Prop_lut5_I0_O) 0.155 8.825 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518/O - net (fo=1, unplaced) 0.000 8.825 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_518_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 9.135 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299/CO[3] - net (fo=1, unplaced) 0.000 9.135 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_299_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 9.355 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_279/O[1] - net (fo=5, unplaced) 0.480 9.835 hash_generate[2].hash/final/O75[25] - LUT6 (Prop_lut6_I0_O) 0.155 9.990 r hash_generate[2].hash/final/memory_reg_0_i_874/O - net (fo=1, unplaced) 0.363 10.353 hash_generate[2].hash/final/L8_out[25] - CARRY4 (Prop_carry4_DI[1]_CO[3]) - 0.307 10.660 r hash_generate[2].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, unplaced) 0.000 10.660 hash_generate[2].hash/final/memory_reg_0_i_580_n_0 - CARRY4 (Prop_carry4_CI_O[2]) - 0.145 10.805 r hash_generate[2].hash/final/memory_reg_0_i_562/O[2] - net (fo=5, unplaced) 0.367 11.172 hash_generate[2].hash/final/memory_reg_0_i_808__1[6] - LUT3 (Prop_lut3_I2_O) 0.152 11.324 r hash_generate[2].hash/final/memory_reg_0_i_321__1/O - net (fo=1, unplaced) 0.000 11.324 hash_generate[2].hash/final/memory_reg_0_i_321__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 11.634 r hash_generate[2].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, unplaced) 0.000 11.634 hash_generate[2].hash/final/memory_reg_0_i_256_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 11.854 r hash_generate[2].hash/final/memory_reg_0_i_259/O[1] - net (fo=5, unplaced) 0.480 12.334 hash_generate[2].hash/final/minusOp10_out_0[13] - LUT3 (Prop_lut3_I1_O) 0.155 12.489 r hash_generate[2].hash/final/memory_reg_0_i_238__1/O - net (fo=1, unplaced) 0.000 12.489 hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 12.799 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, unplaced) 0.000 12.799 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 13.019 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, unplaced) 0.268 13.287 hash_generate[2].hash/final/minusOp8_out[17] - LUT3 (Prop_lut3_I2_O) 0.155 13.442 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O - net (fo=1, unplaced) 0.000 13.442 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 13.752 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, unplaced) 0.008 13.760 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 + 0.310 3.699 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48/CO[3] + net (fo=1, unplaced) 0.008 3.707 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.820 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, unplaced) 0.000 13.820 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 + 0.060 3.767 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43/CO[3] + net (fo=1, unplaced) 0.000 3.767 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.880 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, unplaced) 0.000 13.880 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 + 0.060 3.827 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38/CO[3] + net (fo=1, unplaced) 0.000 3.827 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 13.940 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, unplaced) 0.000 13.940 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 + 0.060 3.887 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33/CO[3] + net (fo=1, unplaced) 0.000 3.887 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.000 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, unplaced) 0.000 14.000 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 + 0.060 3.947 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28/CO[3] + net (fo=1, unplaced) 0.000 3.947 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.060 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, unplaced) 0.000 14.060 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 + 0.060 4.007 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23/CO[3] + net (fo=1, unplaced) 0.000 4.007 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 14.120 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, unplaced) 0.000 14.120 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 14.340 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, unplaced) 0.258 14.598 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] - LUT3 (Prop_lut3_I2_O) 0.155 14.753 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O - net (fo=1, unplaced) 0.000 14.753 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.063 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, unplaced) 0.008 15.071 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 + 0.060 4.067 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18/CO[3] + net (fo=1, unplaced) 0.000 4.067 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.131 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, unplaced) 0.000 15.131 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 + 0.060 4.127 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13/CO[3] + net (fo=1, unplaced) 0.000 4.127 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.191 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, unplaced) 0.000 15.191 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 + 0.060 4.187 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8/CO[3] + net (fo=1, unplaced) 0.000 4.187 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8_n_0 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 15.251 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, unplaced) 0.000 15.251 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 - CARRY4 (Prop_carry4_CI_O[3]) - 0.189 15.440 r hash_generate[2].hash/final/memory_reg_0_i_101/O[3] - net (fo=1, unplaced) 0.358 15.798 hash_generate[2].hash/final/memory_reg_0_i_101_n_4 - LUT3 (Prop_lut3_I2_O) 0.142 15.940 r hash_generate[2].hash/final/memory_reg_0_i_85__1/O - net (fo=1, unplaced) 0.000 15.940 hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 16.250 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] - net (fo=1, unplaced) 0.008 16.258 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 - CARRY4 (Prop_carry4_CI_O[1]) - 0.220 16.478 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] - net (fo=2, unplaced) 0.463 16.941 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 - LUT3 (Prop_lut3_I1_O) 0.155 17.096 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O - net (fo=1, unplaced) 0.000 17.096 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 - CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 17.406 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] - net (fo=1, unplaced) 0.000 17.406 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 - CARRY4 (Prop_carry4_CI_O[0]) - 0.142 17.548 r hash_generate[2].hash/final/memory_reg_0_i_2/O[0] - net (fo=9, unplaced) 0.584 18.132 storage_generate[2].storage/O76[8] - RAMB36E1 r storage_generate[2].storage/memory_reg_0/ADDRBWRADDR[12] + 0.060 4.247 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4/CO[3] + net (fo=1, unplaced) 0.000 4.247 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4_n_0 + CARRY4 (Prop_carry4_CI_CO[2]) + 0.149 4.396 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_2/CO[2] + net (fo=33, unplaced) 0.411 4.807 storage_generate[1].storage/CO[0] + LUT6 (Prop_lut6_I4_O) 0.160 4.967 r storage_generate[1].storage/registered_output.OUTPUT_DATA[1]_i_2/O + net (fo=1, unplaced) 0.340 5.307 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[1] + LUT6 (Prop_lut6_I5_O) 0.053 5.360 r storage_generate[2].storage/registered_output.OUTPUT_DATA[1]_i_1/O + net (fo=1, unplaced) 0.000 5.360 out_data[1] + FDRE r registered_output.OUTPUT_DATA_reg[1]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 4.000 4.000 r 0.000 4.000 r CLK (IN) - net (fo=634, unset) 0.638 4.638 storage_generate[2].storage/CLK - RAMB36E1 r storage_generate[2].storage/memory_reg_0/CLKBWRCLK + net (fo=5026, unset) 0.638 4.638 CLK + FDRE r registered_output.OUTPUT_DATA_reg[1]/C clock pessimism 0.000 4.638 clock uncertainty -0.035 4.603 - RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[12]) - -0.581 4.022 storage_generate[2].storage/memory_reg_0 + FDRE (Setup_fdre_C_D) 0.049 4.652 registered_output.OUTPUT_DATA_reg[1] ------------------------------------------------------------------- - required time 4.022 - arrival time -18.132 + required time 4.652 + arrival time -5.360 ------------------------------------------------------------------- - slack -14.110 + slack -0.708 + +Slack (VIOLATED) : -0.708ns (required time - arrival time) + Source: storage_generate[2].storage/memory_reg_1/CLKBWRCLK + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[2]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 4.688ns (logic 3.345ns (71.359%) route 1.343ns (28.641%)) + Logic Levels: 14 (CARRY4=11 LUT6=3) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=5026, unset) 0.672 0.672 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_1/CLKBWRCLK + ------------------------------------------------------------------- ------------------- + RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[3]) + 2.080 2.752 r storage_generate[2].storage/memory_reg_1/DOBDO[3] + net (fo=1, unplaced) 0.584 3.336 storage_generate[2].storage/memory_rule[2][21] + LUT6 (Prop_lut6_I4_O) 0.053 3.389 r storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55/O + net (fo=1, unplaced) 0.000 3.389 storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.699 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48/CO[3] + net (fo=1, unplaced) 0.008 3.707 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 3.767 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43/CO[3] + net (fo=1, unplaced) 0.000 3.767 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 3.827 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38/CO[3] + net (fo=1, unplaced) 0.000 3.827 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 3.887 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33/CO[3] + net (fo=1, unplaced) 0.000 3.887 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 3.947 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28/CO[3] + net (fo=1, unplaced) 0.000 3.947 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 4.007 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23/CO[3] + net (fo=1, unplaced) 0.000 4.007 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 4.067 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18/CO[3] + net (fo=1, unplaced) 0.000 4.067 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 4.127 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13/CO[3] + net (fo=1, unplaced) 0.000 4.127 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 4.187 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8/CO[3] + net (fo=1, unplaced) 0.000 4.187 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 4.247 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4/CO[3] + net (fo=1, unplaced) 0.000 4.247 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4_n_0 + CARRY4 (Prop_carry4_CI_CO[2]) + 0.149 4.396 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_2/CO[2] + net (fo=33, unplaced) 0.411 4.807 storage_generate[1].storage/CO[0] + LUT6 (Prop_lut6_I4_O) 0.160 4.967 r storage_generate[1].storage/registered_output.OUTPUT_DATA[2]_i_2/O + net (fo=1, unplaced) 0.340 5.307 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[2] + LUT6 (Prop_lut6_I5_O) 0.053 5.360 r storage_generate[2].storage/registered_output.OUTPUT_DATA[2]_i_1/O + net (fo=1, unplaced) 0.000 5.360 out_data[2] + FDRE r registered_output.OUTPUT_DATA_reg[2]/D + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=5026, unset) 0.638 4.638 CLK + FDRE r registered_output.OUTPUT_DATA_reg[2]/C + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + FDRE (Setup_fdre_C_D) 0.049 4.652 registered_output.OUTPUT_DATA_reg[2] + ------------------------------------------------------------------- + required time 4.652 + arrival time -5.360 + ------------------------------------------------------------------- + slack -0.708 + +Slack (VIOLATED) : -0.708ns (required time - arrival time) + Source: storage_generate[2].storage/memory_reg_1/CLKBWRCLK + (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[3]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Setup (Max at Slow Process Corner) + Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) + Data Path Delay: 4.688ns (logic 3.345ns (71.359%) route 1.343ns (28.641%)) + Logic Levels: 14 (CARRY4=11 LUT6=3) + Clock Path Skew: -0.034ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) + Source Clock Delay (SCD): 0.672ns + Clock Pessimism Removal (CPR): 0.000ns + Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.071ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.000ns + Phase Error (PE): 0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=5026, unset) 0.672 0.672 storage_generate[2].storage/CLK + RAMB36E1 r storage_generate[2].storage/memory_reg_1/CLKBWRCLK + ------------------------------------------------------------------- ------------------- + RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[3]) + 2.080 2.752 r storage_generate[2].storage/memory_reg_1/DOBDO[3] + net (fo=1, unplaced) 0.584 3.336 storage_generate[2].storage/memory_rule[2][21] + LUT6 (Prop_lut6_I4_O) 0.053 3.389 r storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55/O + net (fo=1, unplaced) 0.000 3.389 storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55_n_0 + CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.310 3.699 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48/CO[3] + net (fo=1, unplaced) 0.008 3.707 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 3.767 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43/CO[3] + net (fo=1, unplaced) 0.000 3.767 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 3.827 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38/CO[3] + net (fo=1, unplaced) 0.000 3.827 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 3.887 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33/CO[3] + net (fo=1, unplaced) 0.000 3.887 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 3.947 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28/CO[3] + net (fo=1, unplaced) 0.000 3.947 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 4.007 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23/CO[3] + net (fo=1, unplaced) 0.000 4.007 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 4.067 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18/CO[3] + net (fo=1, unplaced) 0.000 4.067 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 4.127 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13/CO[3] + net (fo=1, unplaced) 0.000 4.127 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 4.187 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8/CO[3] + net (fo=1, unplaced) 0.000 4.187 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8_n_0 + CARRY4 (Prop_carry4_CI_CO[3]) + 0.060 4.247 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4/CO[3] + net (fo=1, unplaced) 0.000 4.247 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4_n_0 + CARRY4 (Prop_carry4_CI_CO[2]) + 0.149 4.396 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_2/CO[2] + net (fo=33, unplaced) 0.411 4.807 storage_generate[1].storage/CO[0] + LUT6 (Prop_lut6_I4_O) 0.160 4.967 r storage_generate[1].storage/registered_output.OUTPUT_DATA[3]_i_2/O + net (fo=1, unplaced) 0.340 5.307 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[3] + LUT6 (Prop_lut6_I5_O) 0.053 5.360 r storage_generate[2].storage/registered_output.OUTPUT_DATA[3]_i_1/O + net (fo=1, unplaced) 0.000 5.360 out_data[3] + FDRE r registered_output.OUTPUT_DATA_reg[3]/D + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 4.000 4.000 r + 0.000 4.000 r CLK (IN) + net (fo=5026, unset) 0.638 4.638 CLK + FDRE r registered_output.OUTPUT_DATA_reg[3]/C + clock pessimism 0.000 4.638 + clock uncertainty -0.035 4.603 + FDRE (Setup_fdre_C_D) 0.049 4.652 registered_output.OUTPUT_DATA_reg[3] + ------------------------------------------------------------------- + required time 4.652 + arrival time -5.360 + ------------------------------------------------------------------- + slack -0.708 @@ -2064,15 +1074,15 @@ Slack (VIOLATED) : -14.110ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.190ns (arrival time - required time) - Source: registered_config.cfg_item_reg[6]/C +Slack (MET) : 0.169ns (arrival time - required time) + Source: registered_input.in_valid_reg/C (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[10] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[0].hash/final/s_reg[7][valid]_srl13/D + (rising edge-triggered cell SRL16E clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Data Path Delay: 0.206ns (logic 0.104ns (50.484%) route 0.102ns (49.516%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2083,36 +1093,36 @@ Slack (MET) : 0.190ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.283 0.283 CLK - FDRE r registered_config.cfg_item_reg[6]/C + net (fo=5026, unset) 0.283 0.283 CLK + FDRE r registered_input.in_valid_reg/C ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[6]/Q - net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[6] - RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[10] + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_input.in_valid_reg/Q + net (fo=1, unplaced) 0.102 0.489 hash_generate[0].hash/final/in_valid + SRL16E r hash_generate[0].hash/final/s_reg[7][valid]_srl13/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK - RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + net (fo=5026, unset) 0.298 0.298 hash_generate[0].hash/final/CLK + SRL16E r hash_generate[0].hash/final/s_reg[7][valid]_srl13/CLK clock pessimism 0.000 0.298 - RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[10]) - 0.145 0.443 storage_generate[0].storage/memory_reg_0 + SRL16E (Hold_srl16e_CLK_D) + 0.022 0.320 hash_generate[0].hash/final/s_reg[7][valid]_srl13 ------------------------------------------------------------------- - required time -0.443 - arrival time 0.633 + required time -0.320 + arrival time 0.489 ------------------------------------------------------------------- - slack 0.190 + slack 0.169 -Slack (MET) : 0.190ns (arrival time - required time) - Source: registered_config.cfg_item_reg[7]/C +Slack (MET) : 0.169ns (arrival time - required time) + Source: registered_input.in_key_reg[100]__0/C (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[11] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][100]_srl5/D + (rising edge-triggered cell SRL16E clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Data Path Delay: 0.206ns (logic 0.104ns (50.484%) route 0.102ns (49.516%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2123,36 +1133,36 @@ Slack (MET) : 0.190ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.283 0.283 CLK - FDRE r registered_config.cfg_item_reg[7]/C + net (fo=5026, unset) 0.283 0.283 CLK + FDRE r registered_input.in_key_reg[100]__0/C ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[7]/Q - net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[7] - RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[11] + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_input.in_key_reg[100]__0/Q + net (fo=1, unplaced) 0.102 0.489 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[6][key][100]__0_0 + SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][100]_srl5/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK - RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + net (fo=5026, unset) 0.298 0.298 hash_generate[0].hash/mix_pipeline[0].mix/CLK + SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][100]_srl5/CLK clock pessimism 0.000 0.298 - RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[11]) - 0.145 0.443 storage_generate[0].storage/memory_reg_0 + SRL16E (Hold_srl16e_CLK_D) + 0.022 0.320 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][100]_srl5 ------------------------------------------------------------------- - required time -0.443 - arrival time 0.633 + required time -0.320 + arrival time 0.489 ------------------------------------------------------------------- - slack 0.190 + slack 0.169 -Slack (MET) : 0.190ns (arrival time - required time) - Source: registered_config.cfg_item_reg[8]/C +Slack (MET) : 0.169ns (arrival time - required time) + Source: registered_input.in_key_reg[101]__0/C (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[12] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][101]_srl5/D + (rising edge-triggered cell SRL16E clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Data Path Delay: 0.206ns (logic 0.104ns (50.484%) route 0.102ns (49.516%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2163,36 +1173,36 @@ Slack (MET) : 0.190ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.283 0.283 CLK - FDRE r registered_config.cfg_item_reg[8]/C + net (fo=5026, unset) 0.283 0.283 CLK + FDRE r registered_input.in_key_reg[101]__0/C ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[8]/Q - net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[8] - RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[12] + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_input.in_key_reg[101]__0/Q + net (fo=1, unplaced) 0.102 0.489 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[6][key][101]__0_0 + SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][101]_srl5/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK - RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + net (fo=5026, unset) 0.298 0.298 hash_generate[0].hash/mix_pipeline[0].mix/CLK + SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][101]_srl5/CLK clock pessimism 0.000 0.298 - RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[12]) - 0.145 0.443 storage_generate[0].storage/memory_reg_0 + SRL16E (Hold_srl16e_CLK_D) + 0.022 0.320 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][101]_srl5 ------------------------------------------------------------------- - required time -0.443 - arrival time 0.633 + required time -0.320 + arrival time 0.489 ------------------------------------------------------------------- - slack 0.190 + slack 0.169 -Slack (MET) : 0.190ns (arrival time - required time) - Source: registered_config.cfg_item_reg[9]/C +Slack (MET) : 0.169ns (arrival time - required time) + Source: registered_input.in_key_reg[102]__0/C (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[13] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][102]_srl5/D + (rising edge-triggered cell SRL16E clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Data Path Delay: 0.206ns (logic 0.104ns (50.484%) route 0.102ns (49.516%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2203,36 +1213,36 @@ Slack (MET) : 0.190ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.283 0.283 CLK - FDRE r registered_config.cfg_item_reg[9]/C + net (fo=5026, unset) 0.283 0.283 CLK + FDRE r registered_input.in_key_reg[102]__0/C ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[9]/Q - net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[9] - RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[13] + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_input.in_key_reg[102]__0/Q + net (fo=1, unplaced) 0.102 0.489 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[6][key][102]__0_0 + SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][102]_srl5/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK - RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + net (fo=5026, unset) 0.298 0.298 hash_generate[0].hash/mix_pipeline[0].mix/CLK + SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][102]_srl5/CLK clock pessimism 0.000 0.298 - RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[13]) - 0.145 0.443 storage_generate[0].storage/memory_reg_0 + SRL16E (Hold_srl16e_CLK_D) + 0.022 0.320 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][102]_srl5 ------------------------------------------------------------------- - required time -0.443 - arrival time 0.633 + required time -0.320 + arrival time 0.489 ------------------------------------------------------------------- - slack 0.190 + slack 0.169 -Slack (MET) : 0.190ns (arrival time - required time) - Source: registered_config.cfg_item_reg[10]/C +Slack (MET) : 0.169ns (arrival time - required time) + Source: registered_input.in_key_reg[103]__0/C (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[14] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][103]_srl5/D + (rising edge-triggered cell SRL16E clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Data Path Delay: 0.206ns (logic 0.104ns (50.484%) route 0.102ns (49.516%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2243,36 +1253,36 @@ Slack (MET) : 0.190ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.283 0.283 CLK - FDRE r registered_config.cfg_item_reg[10]/C + net (fo=5026, unset) 0.283 0.283 CLK + FDRE r registered_input.in_key_reg[103]__0/C ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[10]/Q - net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[10] - RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[14] + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_input.in_key_reg[103]__0/Q + net (fo=1, unplaced) 0.102 0.489 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[6][key][103]__0_0 + SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][103]_srl5/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK - RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + net (fo=5026, unset) 0.298 0.298 hash_generate[0].hash/mix_pipeline[0].mix/CLK + SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][103]_srl5/CLK clock pessimism 0.000 0.298 - RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[14]) - 0.145 0.443 storage_generate[0].storage/memory_reg_0 + SRL16E (Hold_srl16e_CLK_D) + 0.022 0.320 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][103]_srl5 ------------------------------------------------------------------- - required time -0.443 - arrival time 0.633 + required time -0.320 + arrival time 0.489 ------------------------------------------------------------------- - slack 0.190 + slack 0.169 -Slack (MET) : 0.190ns (arrival time - required time) - Source: registered_config.cfg_item_reg[0]/C +Slack (MET) : 0.169ns (arrival time - required time) + Source: registered_input.in_key_reg[104]__0/C (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[4] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][104]_srl5/D + (rising edge-triggered cell SRL16E clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Data Path Delay: 0.206ns (logic 0.104ns (50.484%) route 0.102ns (49.516%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2283,36 +1293,36 @@ Slack (MET) : 0.190ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.283 0.283 CLK - FDRE r registered_config.cfg_item_reg[0]/C + net (fo=5026, unset) 0.283 0.283 CLK + FDRE r registered_input.in_key_reg[104]__0/C ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[0]/Q - net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[0] - RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[4] + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_input.in_key_reg[104]__0/Q + net (fo=1, unplaced) 0.102 0.489 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[6][key][104]__0_0 + SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][104]_srl5/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK - RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + net (fo=5026, unset) 0.298 0.298 hash_generate[0].hash/mix_pipeline[0].mix/CLK + SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][104]_srl5/CLK clock pessimism 0.000 0.298 - RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[4]) - 0.145 0.443 storage_generate[0].storage/memory_reg_0 + SRL16E (Hold_srl16e_CLK_D) + 0.022 0.320 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][104]_srl5 ------------------------------------------------------------------- - required time -0.443 - arrival time 0.633 + required time -0.320 + arrival time 0.489 ------------------------------------------------------------------- - slack 0.190 + slack 0.169 -Slack (MET) : 0.190ns (arrival time - required time) - Source: registered_config.cfg_item_reg[1]/C +Slack (MET) : 0.169ns (arrival time - required time) + Source: registered_input.in_key_reg[105]__0/C (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[5] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][105]_srl5/D + (rising edge-triggered cell SRL16E clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Data Path Delay: 0.206ns (logic 0.104ns (50.484%) route 0.102ns (49.516%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2323,36 +1333,36 @@ Slack (MET) : 0.190ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.283 0.283 CLK - FDRE r registered_config.cfg_item_reg[1]/C + net (fo=5026, unset) 0.283 0.283 CLK + FDRE r registered_input.in_key_reg[105]__0/C ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[1]/Q - net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[1] - RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[5] + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_input.in_key_reg[105]__0/Q + net (fo=1, unplaced) 0.102 0.489 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[6][key][105]__0_0 + SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][105]_srl5/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK - RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + net (fo=5026, unset) 0.298 0.298 hash_generate[0].hash/mix_pipeline[0].mix/CLK + SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][105]_srl5/CLK clock pessimism 0.000 0.298 - RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[5]) - 0.145 0.443 storage_generate[0].storage/memory_reg_0 + SRL16E (Hold_srl16e_CLK_D) + 0.022 0.320 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][105]_srl5 ------------------------------------------------------------------- - required time -0.443 - arrival time 0.633 + required time -0.320 + arrival time 0.489 ------------------------------------------------------------------- - slack 0.190 + slack 0.169 -Slack (MET) : 0.190ns (arrival time - required time) - Source: registered_config.cfg_item_reg[2]/C +Slack (MET) : 0.169ns (arrival time - required time) + Source: registered_input.in_key_reg[106]__0/C (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[6] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][106]_srl5/D + (rising edge-triggered cell SRL16E clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Data Path Delay: 0.206ns (logic 0.104ns (50.484%) route 0.102ns (49.516%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2363,36 +1373,36 @@ Slack (MET) : 0.190ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.283 0.283 CLK - FDRE r registered_config.cfg_item_reg[2]/C + net (fo=5026, unset) 0.283 0.283 CLK + FDRE r registered_input.in_key_reg[106]__0/C ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[2]/Q - net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[2] - RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[6] + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_input.in_key_reg[106]__0/Q + net (fo=1, unplaced) 0.102 0.489 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[6][key][106]__0_0 + SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][106]_srl5/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK - RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + net (fo=5026, unset) 0.298 0.298 hash_generate[0].hash/mix_pipeline[0].mix/CLK + SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][106]_srl5/CLK clock pessimism 0.000 0.298 - RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[6]) - 0.145 0.443 storage_generate[0].storage/memory_reg_0 + SRL16E (Hold_srl16e_CLK_D) + 0.022 0.320 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][106]_srl5 ------------------------------------------------------------------- - required time -0.443 - arrival time 0.633 + required time -0.320 + arrival time 0.489 ------------------------------------------------------------------- - slack 0.190 + slack 0.169 -Slack (MET) : 0.190ns (arrival time - required time) - Source: registered_config.cfg_item_reg[3]/C +Slack (MET) : 0.169ns (arrival time - required time) + Source: registered_input.in_key_reg[107]__0/C (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[7] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][107]_srl5/D + (rising edge-triggered cell SRL16E clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Data Path Delay: 0.206ns (logic 0.104ns (50.484%) route 0.102ns (49.516%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2403,36 +1413,36 @@ Slack (MET) : 0.190ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.283 0.283 CLK - FDRE r registered_config.cfg_item_reg[3]/C + net (fo=5026, unset) 0.283 0.283 CLK + FDRE r registered_input.in_key_reg[107]__0/C ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[3]/Q - net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[3] - RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[7] + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_input.in_key_reg[107]__0/Q + net (fo=1, unplaced) 0.102 0.489 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[6][key][107]__0_0 + SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][107]_srl5/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK - RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + net (fo=5026, unset) 0.298 0.298 hash_generate[0].hash/mix_pipeline[0].mix/CLK + SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][107]_srl5/CLK clock pessimism 0.000 0.298 - RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[7]) - 0.145 0.443 storage_generate[0].storage/memory_reg_0 + SRL16E (Hold_srl16e_CLK_D) + 0.022 0.320 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][107]_srl5 ------------------------------------------------------------------- - required time -0.443 - arrival time 0.633 + required time -0.320 + arrival time 0.489 ------------------------------------------------------------------- - slack 0.190 + slack 0.169 -Slack (MET) : 0.190ns (arrival time - required time) - Source: registered_config.cfg_item_reg[4]/C +Slack (MET) : 0.169ns (arrival time - required time) + Source: registered_input.in_key_reg[108]__0/C (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[0].storage/memory_reg_0/ADDRARDADDR[8] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][108]_srl5/D + (rising edge-triggered cell SRL16E clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%)) + Data Path Delay: 0.206ns (logic 0.104ns (50.484%) route 0.102ns (49.516%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2443,26 +1453,26 @@ Slack (MET) : 0.190ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.283 0.283 CLK - FDRE r registered_config.cfg_item_reg[4]/C + net (fo=5026, unset) 0.283 0.283 CLK + FDRE r registered_input.in_key_reg[108]__0/C ------------------------------------------------------------------- ------------------- - FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_config.cfg_item_reg[4]/Q - net (fo=36, unplaced) 0.246 0.633 storage_generate[0].storage/memory_reg_8_0[4] - RAMB36E1 r storage_generate[0].storage/memory_reg_0/ADDRARDADDR[8] + FDRE (Prop_fdre_C_Q) 0.104 0.387 r registered_input.in_key_reg[108]__0/Q + net (fo=1, unplaced) 0.102 0.489 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[6][key][108]__0_0 + SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][108]_srl5/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=634, unset) 0.298 0.298 storage_generate[0].storage/CLK - RAMB36E1 r storage_generate[0].storage/memory_reg_0/CLKARDCLK + net (fo=5026, unset) 0.298 0.298 hash_generate[0].hash/mix_pipeline[0].mix/CLK + SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][108]_srl5/CLK clock pessimism 0.000 0.298 - RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[8]) - 0.145 0.443 storage_generate[0].storage/memory_reg_0 + SRL16E (Hold_srl16e_CLK_D) + 0.022 0.320 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][108]_srl5 ------------------------------------------------------------------- - required time -0.443 - arrival time 0.633 + required time -0.320 + arrival time 0.489 ------------------------------------------------------------------- - slack 0.190 + slack 0.169 @@ -2486,26 +1496,26 @@ Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_7/CLKARDCLK Min Period n/a RAMB18E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[0].storage/memory_reg_8/CLKARDCLK Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 storage_generate[1].storage/memory_reg_0/CLKARDCLK -Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[0]/C -Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[0]/C -Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[100]/C -Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[100]/C -Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[101]/C -Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[101]/C -Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[102]/C -Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[102]/C -Low Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[103]/C -Low Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[103]/C -High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[0]/C -High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[0]/C -High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[100]/C -High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[100]/C -High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[101]/C -High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[101]/C -High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[102]/C -High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[102]/C -High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[103]/C -High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 memory_key_reg[103]/C +Low Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][0]_srl13/CLK +Low Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][0]_srl13/CLK +Low Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][100]_srl7/CLK +Low Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][100]_srl7/CLK +Low Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][101]_srl7/CLK +Low Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][101]_srl7/CLK +Low Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][102]_srl7/CLK +Low Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][102]_srl7/CLK +Low Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][103]_srl7/CLK +Low Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][103]_srl7/CLK +High Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][0]_srl13/CLK +High Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][0]_srl13/CLK +High Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][100]_srl7/CLK +High Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][100]_srl7/CLK +High Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][101]_srl7/CLK +High Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][101]_srl7/CLK +High Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][102]_srl7/CLK +High Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][102]_srl7/CLK +High Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][103]_srl7/CLK +High Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 hash_generate[0].hash/final/s_reg[7][key][103]_srl7/CLK diff --git a/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.rpx b/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.rpx index 4f75903..d3bb149 100644 Binary files a/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.rpx and b/synth/filter_vivado.runs/impl_1/filter_timing_summary_opted.rpx differ diff --git a/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.pb b/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.pb index 6525ab0..208dec5 100644 Binary files a/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.pb and b/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.pb differ diff --git a/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.rpt b/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.rpt index 810d424..9f85db6 100644 --- a/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.rpt +++ b/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 -| Date : Sun Dec 3 18:58:40 2023 +| Date : Sun Dec 3 21:20:43 2023 | Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux | Command : report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_routed.rpt -pb filter_timing_summary_routed.pb -rpx filter_timing_summary_routed.rpx -warn_on_violation | Design : filter @@ -43,7 +43,7 @@ Timing Summary Report Rule Severity Description Violations --------- -------- ---------------------------------------- ---------- -TIMING-16 Warning Large setup violation 420 +TIMING-16 Warning Large setup violation 7 XDCH-2 Warning Same min and max delay values on IO port 436 Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report. @@ -143,7 +143,7 @@ Table of Contents WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - -17.396 -6762.482 465 2155 0.081 0.000 0 2155 1.505 0.000 0 669 + -1.240 -22.558 42 6558 0.038 0.000 0 6558 1.220 0.000 0 5072 Timing constraints are not met. @@ -166,7 +166,7 @@ CLK {0.000 2.000} 4.000 250.000 Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -CLK -17.396 -6762.482 465 2155 0.081 0.000 0 2155 1.505 0.000 0 669 +CLK -1.240 -22.558 42 6558 0.038 0.000 0 6558 1.220 0.000 0 5072 ------------------------------------------------------------------------------------------------ @@ -215,24 +215,24 @@ Path Group From Clock To Clock From Clock: CLK To Clock: CLK -Setup : 465 Failing Endpoints, Worst Slack -17.396ns, Total Violation -6762.482ns -Hold : 0 Failing Endpoints, Worst Slack 0.081ns, Total Violation 0.000ns -PW : 0 Failing Endpoints, Worst Slack 1.505ns, Total Violation 0.000ns +Setup : 42 Failing Endpoints, Worst Slack -1.240ns, Total Violation -22.558ns +Hold : 0 Failing Endpoints, Worst Slack 0.038ns, Total Violation 0.000ns +PW : 0 Failing Endpoints, Worst Slack 1.220ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (VIOLATED) : -17.396ns (required time - arrival time) - Source: registered_input.in_key_reg[64]_replica_5/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[13] +Slack (VIOLATED) : -1.240ns (required time - arrival time) + Source: storage_generate[2].storage/memory_reg_0/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_KEY_FOUND_reg/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 20.749ns (logic 9.946ns (47.935%) route 10.803ns (52.065%)) - Logic Levels: 56 (CARRY4=41 LUT2=1 LUT3=8 LUT5=3 LUT6=3) + Data Path Delay: 5.206ns (logic 3.314ns (63.662%) route 1.892ns (36.338%)) + Logic Levels: 14 (CARRY4=11 LUT2=1 LUT6=2) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) Source Clock Delay (SCD): 0.672ns @@ -247,191 +247,77 @@ Slack (VIOLATED) : -17.396ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.672 0.672 CLK - SLICE_X43Y171 FDRE r registered_input.in_key_reg[64]_replica_5/C + net (fo=5071, unset) 0.672 0.672 storage_generate[2].storage/CLK + RAMB36_X3Y11 RAMB36E1 r storage_generate[2].storage/memory_reg_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- - SLICE_X43Y171 FDRE (Prop_fdre_C_Q) 0.269 0.941 r registered_input.in_key_reg[64]_replica_5/Q - net (fo=5, routed) 0.321 1.262 hash_generate[1].hash/mix_pipeline[0].mix/in_key[64]_repN_5_alias - SLICE_X41Y170 CARRY4 (Prop_carry4_CYINIT_CO[3]) - 0.346 1.608 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, routed) 0.000 1.608 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - SLICE_X41Y171 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 1.747 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[0] - net (fo=18, routed) 0.541 2.287 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559_n_7 - SLICE_X38Y168 LUT2 (Prop_lut2_I1_O) 0.155 2.442 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1/O - net (fo=1, routed) 0.000 2.442 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1_n_0 - SLICE_X38Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 2.752 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] - net (fo=1, routed) 0.000 2.752 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 - SLICE_X38Y169 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 2.964 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] - net (fo=12, routed) 0.584 3.548 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] - SLICE_X44Y169 LUT3 (Prop_lut3_I1_O) 0.155 3.703 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O - net (fo=1, routed) 0.000 3.703 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 - SLICE_X44Y169 CARRY4 (Prop_carry4_S[1]_O[3]) - 0.374 4.077 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[3] - net (fo=8, routed) 0.489 4.566 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[11] - SLICE_X46Y168 LUT3 (Prop_lut3_I0_O) 0.142 4.708 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_734/O - net (fo=10, routed) 0.699 5.407 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_0 - SLICE_X47Y169 LUT6 (Prop_lut6_I3_O) 0.053 5.460 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O - net (fo=1, routed) 0.000 5.460 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 - SLICE_X47Y169 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.233 5.693 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568/CO[3] - net (fo=1, routed) 0.000 5.693 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568_n_0 - SLICE_X47Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 5.906 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/O[1] - net (fo=8, routed) 0.601 6.506 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[12] - SLICE_X49Y168 LUT5 (Prop_lut5_I4_O) 0.152 6.658 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1/O - net (fo=1, routed) 0.000 6.658 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1_n_0 - SLICE_X49Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 6.982 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291/CO[3] - net (fo=1, routed) 0.000 6.982 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291_n_0 - SLICE_X49Y169 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 7.195 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[1] - net (fo=5, routed) 0.631 7.826 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[16] - SLICE_X48Y166 LUT5 (Prop_lut5_I4_O) 0.152 7.978 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_280/O - net (fo=4, routed) 0.698 8.676 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[17] - SLICE_X51Y169 LUT6 (Prop_lut6_I4_O) 0.053 8.729 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009/O - net (fo=1, routed) 0.000 8.729 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009_n_0 - SLICE_X51Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 9.053 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] - net (fo=1, routed) 0.000 9.053 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 - SLICE_X51Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 9.266 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] - net (fo=4, routed) 0.600 9.866 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - SLICE_X50Y169 LUT5 (Prop_lut5_I1_O) 0.152 10.018 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155/O - net (fo=1, routed) 0.000 10.018 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155_n_0 - SLICE_X50Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 10.328 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107/CO[3] - net (fo=1, routed) 0.000 10.328 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107_n_0 - SLICE_X50Y170 CARRY4 (Prop_carry4_CI_O[3]) - 0.181 10.509 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1109/O[3] - net (fo=2, routed) 0.522 11.031 hash_generate[1].hash/final/minusOp1_out[27] - SLICE_X52Y173 LUT6 (Prop_lut6_I5_O) 0.142 11.173 r hash_generate[1].hash/final/memory_reg_0_i_874/O - net (fo=1, routed) 0.644 11.817 hash_generate[1].hash/final/L8_out[27] - SLICE_X52Y170 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.230 12.047 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, routed) 0.000 12.047 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 - SLICE_X52Y171 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 12.260 r hash_generate[1].hash/final/memory_reg_0_i_562/O[1] - net (fo=5, routed) 0.578 12.839 hash_generate[1].hash/final/memory_reg_0_i_810__0[5] - SLICE_X56Y170 LUT3 (Prop_lut3_I2_O) 0.152 12.991 r hash_generate[1].hash/final/memory_reg_0_i_322__0/O - net (fo=1, routed) 0.000 12.991 hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0 - SLICE_X56Y170 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.313 13.304 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, routed) 0.000 13.304 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 - SLICE_X56Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.362 r hash_generate[1].hash/final/memory_reg_0_i_259/CO[3] - net (fo=1, routed) 0.000 13.362 hash_generate[1].hash/final/memory_reg_0_i_259_n_0 - SLICE_X56Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.420 r hash_generate[1].hash/final/memory_reg_0_i_258/CO[3] - net (fo=1, routed) 0.000 13.420 hash_generate[1].hash/final/memory_reg_0_i_258_n_0 - SLICE_X56Y173 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 13.633 r hash_generate[1].hash/final/memory_reg_0_i_285/O[1] - net (fo=5, routed) 0.646 14.279 hash_generate[1].hash/final/memory_reg_0_i_357__0[4] - SLICE_X57Y169 LUT3 (Prop_lut3_I2_O) 0.152 14.431 r hash_generate[1].hash/final/memory_reg_0_i_237__0/O - net (fo=1, routed) 0.000 14.431 hash_generate[1].hash/final/memory_reg_0_i_237__0_n_0 - SLICE_X57Y169 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 14.666 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, routed) 0.000 14.666 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 - SLICE_X57Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 14.879 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, routed) 0.635 15.514 hash_generate[1].hash/final/minusOp8_out[17] - SLICE_X58Y167 LUT3 (Prop_lut3_I2_O) 0.152 15.666 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O - net (fo=1, routed) 0.000 15.666 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 - SLICE_X58Y167 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.976 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, routed) 0.000 15.976 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 - SLICE_X58Y168 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.036 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, routed) 0.000 16.036 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 - SLICE_X58Y169 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.096 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, routed) 0.000 16.096 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 - SLICE_X58Y170 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.156 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, routed) 0.000 16.156 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 - SLICE_X58Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.216 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, routed) 0.000 16.216 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 - SLICE_X58Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.276 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, routed) 0.000 16.276 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 - SLICE_X58Y173 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.336 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, routed) 0.000 16.336 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 - SLICE_X58Y174 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 16.548 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, routed) 0.574 17.123 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] - SLICE_X59Y170 LUT3 (Prop_lut3_I2_O) 0.155 17.278 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O - net (fo=1, routed) 0.000 17.278 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 - SLICE_X59Y170 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 17.602 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, routed) 0.000 17.602 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 - SLICE_X59Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.660 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, routed) 0.000 17.660 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 - SLICE_X59Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.718 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, routed) 0.000 17.718 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 - SLICE_X59Y173 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.776 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, routed) 0.000 17.776 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 - SLICE_X59Y174 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.834 r hash_generate[1].hash/final/memory_reg_0_i_101/CO[3] - net (fo=1, routed) 0.008 17.841 hash_generate[1].hash/final/memory_reg_0_i_101_n_0 - SLICE_X59Y175 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.899 r hash_generate[1].hash/final/memory_reg_0_i_106/CO[3] - net (fo=1, routed) 0.000 17.899 hash_generate[1].hash/final/memory_reg_0_i_106_n_0 - SLICE_X59Y176 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 18.038 r hash_generate[1].hash/final/memory_reg_0_i_98/O[0] - net (fo=1, routed) 0.548 18.586 hash_generate[1].hash/final/memory_reg_0_i_98_n_7 - SLICE_X60Y173 LUT3 (Prop_lut3_I2_O) 0.155 18.741 r hash_generate[1].hash/final/memory_reg_0_i_60__0/O - net (fo=1, routed) 0.000 18.741 hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0 - SLICE_X60Y173 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 18.976 r hash_generate[1].hash/final/memory_reg_0_i_29/CO[3] - net (fo=1, routed) 0.000 18.976 hash_generate[1].hash/final/memory_reg_0_i_29_n_0 - SLICE_X60Y174 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 19.189 r hash_generate[1].hash/final/memory_reg_0_i_26/O[1] - net (fo=3, routed) 0.557 19.747 hash_generate[1].hash/final/memory_reg_0_i_26_n_6 - SLICE_X52Y174 LUT3 (Prop_lut3_I2_O) 0.152 19.899 r hash_generate[1].hash/final/memory_reg_0_i_24__0/O - net (fo=1, routed) 0.000 19.899 hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0 - SLICE_X52Y174 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 20.223 r hash_generate[1].hash/final/memory_reg_0_i_4/CO[3] - net (fo=1, routed) 0.008 20.231 hash_generate[1].hash/final/memory_reg_0_i_4_n_0 - SLICE_X52Y175 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 20.289 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] - net (fo=1, routed) 0.000 20.289 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 - SLICE_X52Y176 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 20.502 r hash_generate[1].hash/final/memory_reg_0_i_2/O[1] - net (fo=9, routed) 0.919 21.421 storage_generate[1].storage/O76[9] - RAMB36_X2Y32 RAMB36E1 r storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[13] + RAMB36_X3Y11 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOPBDOP[1]) + 2.080 2.752 r storage_generate[2].storage/memory_reg_0/DOPBDOP[1] + net (fo=1, routed) 0.909 3.661 storage_generate[2].storage/memory_rule[2][17] + SLICE_X60Y78 LUT6 (Prop_lut6_I5_O) 0.053 3.714 r storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_56/O + net (fo=1, routed) 0.000 3.714 storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_56_n_0 + SLICE_X60Y78 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.313 4.027 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48/CO[3] + net (fo=1, routed) 0.000 4.027 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48_n_0 + SLICE_X60Y79 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.085 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43/CO[3] + net (fo=1, routed) 0.000 4.085 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43_n_0 + SLICE_X60Y80 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.143 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38/CO[3] + net (fo=1, routed) 0.000 4.143 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38_n_0 + SLICE_X60Y81 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.201 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33/CO[3] + net (fo=1, routed) 0.000 4.201 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33_n_0 + SLICE_X60Y82 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.259 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28/CO[3] + net (fo=1, routed) 0.000 4.259 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28_n_0 + SLICE_X60Y83 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.317 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23/CO[3] + net (fo=1, routed) 0.000 4.317 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23_n_0 + SLICE_X60Y84 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.375 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18/CO[3] + net (fo=1, routed) 0.000 4.375 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18_n_0 + SLICE_X60Y85 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.433 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13/CO[3] + net (fo=1, routed) 0.000 4.433 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13_n_0 + SLICE_X60Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.491 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8/CO[3] + net (fo=1, routed) 0.000 4.491 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8_n_0 + SLICE_X60Y87 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.549 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4/CO[3] + net (fo=1, routed) 0.000 4.549 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4_n_0 + SLICE_X60Y88 CARRY4 (Prop_carry4_CI_CO[2]) + 0.132 4.681 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_2/CO[2] + net (fo=33, routed) 0.575 5.255 storage_generate[2].storage/CO[0] + SLICE_X51Y88 LUT2 (Prop_lut2_I0_O) 0.161 5.416 r storage_generate[2].storage/registered_output.OUTPUT_KEY_FOUND_i_4/O + net (fo=1, routed) 0.408 5.825 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_0 + SLICE_X49Y88 LUT6 (Prop_lut6_I4_O) 0.053 5.878 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_1/O + net (fo=1, routed) 0.000 5.878 storage_generate[1].storage_n_16 + SLICE_X49Y88 FDRE r registered_output.OUTPUT_KEY_FOUND_reg/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 4.000 4.000 r 0.000 4.000 r CLK (IN) - net (fo=668, unset) 0.638 4.638 storage_generate[1].storage/CLK - RAMB36_X2Y32 RAMB36E1 r storage_generate[1].storage/memory_reg_1/CLKBWRCLK + net (fo=5071, unset) 0.638 4.638 CLK + SLICE_X49Y88 FDRE r registered_output.OUTPUT_KEY_FOUND_reg/C clock pessimism 0.000 4.638 clock uncertainty -0.035 4.603 - RAMB36_X2Y32 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) - -0.578 4.025 storage_generate[1].storage/memory_reg_1 + SLICE_X49Y88 FDRE (Setup_fdre_C_D) 0.035 4.638 registered_output.OUTPUT_KEY_FOUND_reg ------------------------------------------------------------------- - required time 4.025 - arrival time -21.421 + required time 4.638 + arrival time -5.878 ------------------------------------------------------------------- - slack -17.396 + slack -1.240 -Slack (VIOLATED) : -17.364ns (required time - arrival time) - Source: registered_input.in_key_reg[64]_replica_5/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[11] +Slack (VIOLATED) : -1.144ns (required time - arrival time) + Source: storage_generate[1].storage/memory_reg_2/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[1]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 20.727ns (logic 9.854ns (47.542%) route 10.873ns (52.458%)) - Logic Levels: 55 (CARRY4=40 LUT2=1 LUT3=8 LUT5=3 LUT6=3) + Data Path Delay: 5.148ns (logic 3.209ns (62.339%) route 1.939ns (37.661%)) + Logic Levels: 12 (CARRY4=9 LUT6=3) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) Source Clock Delay (SCD): 0.672ns @@ -446,188 +332,71 @@ Slack (VIOLATED) : -17.364ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.672 0.672 CLK - SLICE_X43Y171 FDRE r registered_input.in_key_reg[64]_replica_5/C + net (fo=5071, unset) 0.672 0.672 storage_generate[1].storage/CLK + RAMB36_X3Y12 RAMB36E1 r storage_generate[1].storage/memory_reg_2/CLKBWRCLK ------------------------------------------------------------------- ------------------- - SLICE_X43Y171 FDRE (Prop_fdre_C_Q) 0.269 0.941 r registered_input.in_key_reg[64]_replica_5/Q - net (fo=5, routed) 0.321 1.262 hash_generate[1].hash/mix_pipeline[0].mix/in_key[64]_repN_5_alias - SLICE_X41Y170 CARRY4 (Prop_carry4_CYINIT_CO[3]) - 0.346 1.608 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, routed) 0.000 1.608 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - SLICE_X41Y171 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 1.747 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[0] - net (fo=18, routed) 0.541 2.287 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559_n_7 - SLICE_X38Y168 LUT2 (Prop_lut2_I1_O) 0.155 2.442 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1/O - net (fo=1, routed) 0.000 2.442 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1_n_0 - SLICE_X38Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 2.752 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] - net (fo=1, routed) 0.000 2.752 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 - SLICE_X38Y169 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 2.964 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] - net (fo=12, routed) 0.584 3.548 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] - SLICE_X44Y169 LUT3 (Prop_lut3_I1_O) 0.155 3.703 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O - net (fo=1, routed) 0.000 3.703 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 - SLICE_X44Y169 CARRY4 (Prop_carry4_S[1]_O[3]) - 0.374 4.077 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[3] - net (fo=8, routed) 0.489 4.566 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[11] - SLICE_X46Y168 LUT3 (Prop_lut3_I0_O) 0.142 4.708 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_734/O - net (fo=10, routed) 0.699 5.407 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_0 - SLICE_X47Y169 LUT6 (Prop_lut6_I3_O) 0.053 5.460 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O - net (fo=1, routed) 0.000 5.460 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 - SLICE_X47Y169 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.233 5.693 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568/CO[3] - net (fo=1, routed) 0.000 5.693 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568_n_0 - SLICE_X47Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 5.906 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/O[1] - net (fo=8, routed) 0.601 6.506 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[12] - SLICE_X49Y168 LUT5 (Prop_lut5_I4_O) 0.152 6.658 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1/O - net (fo=1, routed) 0.000 6.658 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1_n_0 - SLICE_X49Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 6.982 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291/CO[3] - net (fo=1, routed) 0.000 6.982 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291_n_0 - SLICE_X49Y169 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 7.195 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[1] - net (fo=5, routed) 0.631 7.826 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[16] - SLICE_X48Y166 LUT5 (Prop_lut5_I4_O) 0.152 7.978 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_280/O - net (fo=4, routed) 0.698 8.676 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[17] - SLICE_X51Y169 LUT6 (Prop_lut6_I4_O) 0.053 8.729 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009/O - net (fo=1, routed) 0.000 8.729 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009_n_0 - SLICE_X51Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 9.053 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] - net (fo=1, routed) 0.000 9.053 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 - SLICE_X51Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 9.266 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] - net (fo=4, routed) 0.600 9.866 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - SLICE_X50Y169 LUT5 (Prop_lut5_I1_O) 0.152 10.018 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155/O - net (fo=1, routed) 0.000 10.018 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155_n_0 - SLICE_X50Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 10.328 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107/CO[3] - net (fo=1, routed) 0.000 10.328 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107_n_0 - SLICE_X50Y170 CARRY4 (Prop_carry4_CI_O[3]) - 0.181 10.509 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1109/O[3] - net (fo=2, routed) 0.522 11.031 hash_generate[1].hash/final/minusOp1_out[27] - SLICE_X52Y173 LUT6 (Prop_lut6_I5_O) 0.142 11.173 r hash_generate[1].hash/final/memory_reg_0_i_874/O - net (fo=1, routed) 0.644 11.817 hash_generate[1].hash/final/L8_out[27] - SLICE_X52Y170 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.230 12.047 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, routed) 0.000 12.047 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 - SLICE_X52Y171 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 12.260 r hash_generate[1].hash/final/memory_reg_0_i_562/O[1] - net (fo=5, routed) 0.578 12.839 hash_generate[1].hash/final/memory_reg_0_i_810__0[5] - SLICE_X56Y170 LUT3 (Prop_lut3_I2_O) 0.152 12.991 r hash_generate[1].hash/final/memory_reg_0_i_322__0/O - net (fo=1, routed) 0.000 12.991 hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0 - SLICE_X56Y170 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.313 13.304 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, routed) 0.000 13.304 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 - SLICE_X56Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.362 r hash_generate[1].hash/final/memory_reg_0_i_259/CO[3] - net (fo=1, routed) 0.000 13.362 hash_generate[1].hash/final/memory_reg_0_i_259_n_0 - SLICE_X56Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.420 r hash_generate[1].hash/final/memory_reg_0_i_258/CO[3] - net (fo=1, routed) 0.000 13.420 hash_generate[1].hash/final/memory_reg_0_i_258_n_0 - SLICE_X56Y173 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 13.633 r hash_generate[1].hash/final/memory_reg_0_i_285/O[1] - net (fo=5, routed) 0.646 14.279 hash_generate[1].hash/final/memory_reg_0_i_357__0[4] - SLICE_X57Y169 LUT3 (Prop_lut3_I2_O) 0.152 14.431 r hash_generate[1].hash/final/memory_reg_0_i_237__0/O - net (fo=1, routed) 0.000 14.431 hash_generate[1].hash/final/memory_reg_0_i_237__0_n_0 - SLICE_X57Y169 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 14.666 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, routed) 0.000 14.666 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 - SLICE_X57Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 14.879 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, routed) 0.635 15.514 hash_generate[1].hash/final/minusOp8_out[17] - SLICE_X58Y167 LUT3 (Prop_lut3_I2_O) 0.152 15.666 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O - net (fo=1, routed) 0.000 15.666 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 - SLICE_X58Y167 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.976 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, routed) 0.000 15.976 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 - SLICE_X58Y168 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.036 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, routed) 0.000 16.036 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 - SLICE_X58Y169 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.096 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, routed) 0.000 16.096 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 - SLICE_X58Y170 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.156 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, routed) 0.000 16.156 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 - SLICE_X58Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.216 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, routed) 0.000 16.216 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 - SLICE_X58Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.276 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, routed) 0.000 16.276 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 - SLICE_X58Y173 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.336 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, routed) 0.000 16.336 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 - SLICE_X58Y174 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 16.548 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, routed) 0.574 17.123 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] - SLICE_X59Y170 LUT3 (Prop_lut3_I2_O) 0.155 17.278 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O - net (fo=1, routed) 0.000 17.278 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 - SLICE_X59Y170 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 17.602 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, routed) 0.000 17.602 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 - SLICE_X59Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.660 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, routed) 0.000 17.660 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 - SLICE_X59Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.718 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, routed) 0.000 17.718 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 - SLICE_X59Y173 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.776 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, routed) 0.000 17.776 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 - SLICE_X59Y174 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.834 r hash_generate[1].hash/final/memory_reg_0_i_101/CO[3] - net (fo=1, routed) 0.008 17.841 hash_generate[1].hash/final/memory_reg_0_i_101_n_0 - SLICE_X59Y175 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.899 r hash_generate[1].hash/final/memory_reg_0_i_106/CO[3] - net (fo=1, routed) 0.000 17.899 hash_generate[1].hash/final/memory_reg_0_i_106_n_0 - SLICE_X59Y176 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 18.038 r hash_generate[1].hash/final/memory_reg_0_i_98/O[0] - net (fo=1, routed) 0.548 18.586 hash_generate[1].hash/final/memory_reg_0_i_98_n_7 - SLICE_X60Y173 LUT3 (Prop_lut3_I2_O) 0.155 18.741 r hash_generate[1].hash/final/memory_reg_0_i_60__0/O - net (fo=1, routed) 0.000 18.741 hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0 - SLICE_X60Y173 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 18.976 r hash_generate[1].hash/final/memory_reg_0_i_29/CO[3] - net (fo=1, routed) 0.000 18.976 hash_generate[1].hash/final/memory_reg_0_i_29_n_0 - SLICE_X60Y174 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 19.189 r hash_generate[1].hash/final/memory_reg_0_i_26/O[1] - net (fo=3, routed) 0.557 19.747 hash_generate[1].hash/final/memory_reg_0_i_26_n_6 - SLICE_X52Y174 LUT3 (Prop_lut3_I2_O) 0.152 19.899 r hash_generate[1].hash/final/memory_reg_0_i_24__0/O - net (fo=1, routed) 0.000 19.899 hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0 - SLICE_X52Y174 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 20.223 r hash_generate[1].hash/final/memory_reg_0_i_4/CO[3] - net (fo=1, routed) 0.008 20.231 hash_generate[1].hash/final/memory_reg_0_i_4_n_0 - SLICE_X52Y175 CARRY4 (Prop_carry4_CI_O[3]) - 0.179 20.410 r hash_generate[1].hash/final/memory_reg_0_i_3/O[3] - net (fo=9, routed) 0.989 21.399 storage_generate[1].storage/O76[7] - RAMB36_X2Y32 RAMB36E1 r storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[11] + RAMB36_X3Y12 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[9]) + 2.080 2.752 r storage_generate[1].storage/memory_reg_2/DOBDO[9] + net (fo=1, routed) 1.081 3.833 storage_generate[1].storage/memory_rule[1][45] + SLICE_X61Y79 LUT6 (Prop_lut6_I5_O) 0.053 3.886 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122/O + net (fo=1, routed) 0.000 3.886 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122_n_0 + SLICE_X61Y79 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 4.210 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_104/CO[3] + net (fo=1, routed) 0.000 4.210 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_104_n_0 + SLICE_X61Y80 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.268 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_89/CO[3] + net (fo=1, routed) 0.000 4.268 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_89_n_0 + SLICE_X61Y81 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.326 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_74/CO[3] + net (fo=1, routed) 0.000 4.326 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_74_n_0 + SLICE_X61Y82 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.384 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_59/CO[3] + net (fo=1, routed) 0.000 4.384 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_59_n_0 + SLICE_X61Y83 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.442 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_44/CO[3] + net (fo=1, routed) 0.000 4.442 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_44_n_0 + SLICE_X61Y84 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.500 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_29/CO[3] + net (fo=1, routed) 0.000 4.500 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_29_n_0 + SLICE_X61Y85 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.558 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_15/CO[3] + net (fo=1, routed) 0.000 4.558 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_15_n_0 + SLICE_X61Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.616 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_6/CO[3] + net (fo=1, routed) 0.000 4.616 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_6_n_0 + SLICE_X61Y87 CARRY4 (Prop_carry4_CI_CO[2]) + 0.132 4.748 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_2/CO[2] + net (fo=17, routed) 0.438 5.186 storage_generate[1].storage/out_key_found13_out + SLICE_X58Y87 LUT6 (Prop_lut6_I3_O) 0.161 5.347 r storage_generate[1].storage/registered_output.OUTPUT_DATA[1]_i_2/O + net (fo=1, routed) 0.420 5.767 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[1] + SLICE_X58Y88 LUT6 (Prop_lut6_I5_O) 0.053 5.820 r storage_generate[2].storage/registered_output.OUTPUT_DATA[1]_i_1/O + net (fo=1, routed) 0.000 5.820 out_data[1] + SLICE_X58Y88 FDRE r registered_output.OUTPUT_DATA_reg[1]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 4.000 4.000 r 0.000 4.000 r CLK (IN) - net (fo=668, unset) 0.638 4.638 storage_generate[1].storage/CLK - RAMB36_X2Y32 RAMB36E1 r storage_generate[1].storage/memory_reg_1/CLKBWRCLK + net (fo=5071, unset) 0.638 4.638 CLK + SLICE_X58Y88 FDRE r registered_output.OUTPUT_DATA_reg[1]/C clock pessimism 0.000 4.638 clock uncertainty -0.035 4.603 - RAMB36_X2Y32 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[11]) - -0.568 4.035 storage_generate[1].storage/memory_reg_1 + SLICE_X58Y88 FDRE (Setup_fdre_C_D) 0.073 4.676 registered_output.OUTPUT_DATA_reg[1] ------------------------------------------------------------------- - required time 4.035 - arrival time -21.399 + required time 4.676 + arrival time -5.820 ------------------------------------------------------------------- - slack -17.364 + slack -1.144 -Slack (VIOLATED) : -17.363ns (required time - arrival time) - Source: registered_input.in_key_reg[64]_replica_5/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[9] +Slack (VIOLATED) : -1.051ns (required time - arrival time) + Source: storage_generate[3].storage/memory_reg_3/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[11]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 20.716ns (logic 9.888ns (47.731%) route 10.828ns (52.269%)) - Logic Levels: 55 (CARRY4=40 LUT2=1 LUT3=8 LUT5=3 LUT6=3) + Data Path Delay: 5.017ns (logic 3.093ns (61.645%) route 1.924ns (38.355%)) + Logic Levels: 10 (CARRY4=7 LUT2=1 LUT6=2) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) Source Clock Delay (SCD): 0.672ns @@ -642,188 +411,65 @@ Slack (VIOLATED) : -17.363ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.672 0.672 CLK - SLICE_X43Y171 FDRE r registered_input.in_key_reg[64]_replica_5/C + net (fo=5071, unset) 0.672 0.672 storage_generate[3].storage/CLK + RAMB36_X2Y14 RAMB36E1 r storage_generate[3].storage/memory_reg_3/CLKBWRCLK ------------------------------------------------------------------- ------------------- - SLICE_X43Y171 FDRE (Prop_fdre_C_Q) 0.269 0.941 r registered_input.in_key_reg[64]_replica_5/Q - net (fo=5, routed) 0.321 1.262 hash_generate[1].hash/mix_pipeline[0].mix/in_key[64]_repN_5_alias - SLICE_X41Y170 CARRY4 (Prop_carry4_CYINIT_CO[3]) - 0.346 1.608 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, routed) 0.000 1.608 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - SLICE_X41Y171 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 1.747 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[0] - net (fo=18, routed) 0.541 2.287 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559_n_7 - SLICE_X38Y168 LUT2 (Prop_lut2_I1_O) 0.155 2.442 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1/O - net (fo=1, routed) 0.000 2.442 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1_n_0 - SLICE_X38Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 2.752 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] - net (fo=1, routed) 0.000 2.752 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 - SLICE_X38Y169 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 2.964 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] - net (fo=12, routed) 0.584 3.548 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] - SLICE_X44Y169 LUT3 (Prop_lut3_I1_O) 0.155 3.703 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O - net (fo=1, routed) 0.000 3.703 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 - SLICE_X44Y169 CARRY4 (Prop_carry4_S[1]_O[3]) - 0.374 4.077 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[3] - net (fo=8, routed) 0.489 4.566 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[11] - SLICE_X46Y168 LUT3 (Prop_lut3_I0_O) 0.142 4.708 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_734/O - net (fo=10, routed) 0.699 5.407 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_0 - SLICE_X47Y169 LUT6 (Prop_lut6_I3_O) 0.053 5.460 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O - net (fo=1, routed) 0.000 5.460 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 - SLICE_X47Y169 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.233 5.693 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568/CO[3] - net (fo=1, routed) 0.000 5.693 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568_n_0 - SLICE_X47Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 5.906 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/O[1] - net (fo=8, routed) 0.601 6.506 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[12] - SLICE_X49Y168 LUT5 (Prop_lut5_I4_O) 0.152 6.658 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1/O - net (fo=1, routed) 0.000 6.658 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1_n_0 - SLICE_X49Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 6.982 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291/CO[3] - net (fo=1, routed) 0.000 6.982 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291_n_0 - SLICE_X49Y169 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 7.195 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[1] - net (fo=5, routed) 0.631 7.826 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[16] - SLICE_X48Y166 LUT5 (Prop_lut5_I4_O) 0.152 7.978 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_280/O - net (fo=4, routed) 0.698 8.676 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[17] - SLICE_X51Y169 LUT6 (Prop_lut6_I4_O) 0.053 8.729 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009/O - net (fo=1, routed) 0.000 8.729 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009_n_0 - SLICE_X51Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 9.053 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] - net (fo=1, routed) 0.000 9.053 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 - SLICE_X51Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 9.266 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] - net (fo=4, routed) 0.600 9.866 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - SLICE_X50Y169 LUT5 (Prop_lut5_I1_O) 0.152 10.018 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155/O - net (fo=1, routed) 0.000 10.018 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155_n_0 - SLICE_X50Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 10.328 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107/CO[3] - net (fo=1, routed) 0.000 10.328 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107_n_0 - SLICE_X50Y170 CARRY4 (Prop_carry4_CI_O[3]) - 0.181 10.509 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1109/O[3] - net (fo=2, routed) 0.522 11.031 hash_generate[1].hash/final/minusOp1_out[27] - SLICE_X52Y173 LUT6 (Prop_lut6_I5_O) 0.142 11.173 r hash_generate[1].hash/final/memory_reg_0_i_874/O - net (fo=1, routed) 0.644 11.817 hash_generate[1].hash/final/L8_out[27] - SLICE_X52Y170 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.230 12.047 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, routed) 0.000 12.047 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 - SLICE_X52Y171 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 12.260 r hash_generate[1].hash/final/memory_reg_0_i_562/O[1] - net (fo=5, routed) 0.578 12.839 hash_generate[1].hash/final/memory_reg_0_i_810__0[5] - SLICE_X56Y170 LUT3 (Prop_lut3_I2_O) 0.152 12.991 r hash_generate[1].hash/final/memory_reg_0_i_322__0/O - net (fo=1, routed) 0.000 12.991 hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0 - SLICE_X56Y170 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.313 13.304 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, routed) 0.000 13.304 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 - SLICE_X56Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.362 r hash_generate[1].hash/final/memory_reg_0_i_259/CO[3] - net (fo=1, routed) 0.000 13.362 hash_generate[1].hash/final/memory_reg_0_i_259_n_0 - SLICE_X56Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.420 r hash_generate[1].hash/final/memory_reg_0_i_258/CO[3] - net (fo=1, routed) 0.000 13.420 hash_generate[1].hash/final/memory_reg_0_i_258_n_0 - SLICE_X56Y173 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 13.633 r hash_generate[1].hash/final/memory_reg_0_i_285/O[1] - net (fo=5, routed) 0.646 14.279 hash_generate[1].hash/final/memory_reg_0_i_357__0[4] - SLICE_X57Y169 LUT3 (Prop_lut3_I2_O) 0.152 14.431 r hash_generate[1].hash/final/memory_reg_0_i_237__0/O - net (fo=1, routed) 0.000 14.431 hash_generate[1].hash/final/memory_reg_0_i_237__0_n_0 - SLICE_X57Y169 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 14.666 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, routed) 0.000 14.666 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 - SLICE_X57Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 14.879 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, routed) 0.635 15.514 hash_generate[1].hash/final/minusOp8_out[17] - SLICE_X58Y167 LUT3 (Prop_lut3_I2_O) 0.152 15.666 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O - net (fo=1, routed) 0.000 15.666 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 - SLICE_X58Y167 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.976 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, routed) 0.000 15.976 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 - SLICE_X58Y168 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.036 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, routed) 0.000 16.036 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 - SLICE_X58Y169 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.096 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, routed) 0.000 16.096 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 - SLICE_X58Y170 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.156 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, routed) 0.000 16.156 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 - SLICE_X58Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.216 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, routed) 0.000 16.216 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 - SLICE_X58Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.276 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, routed) 0.000 16.276 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 - SLICE_X58Y173 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.336 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, routed) 0.000 16.336 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 - SLICE_X58Y174 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 16.548 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, routed) 0.574 17.123 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] - SLICE_X59Y170 LUT3 (Prop_lut3_I2_O) 0.155 17.278 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O - net (fo=1, routed) 0.000 17.278 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 - SLICE_X59Y170 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 17.602 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, routed) 0.000 17.602 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 - SLICE_X59Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.660 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, routed) 0.000 17.660 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 - SLICE_X59Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.718 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, routed) 0.000 17.718 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 - SLICE_X59Y173 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.776 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, routed) 0.000 17.776 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 - SLICE_X59Y174 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.834 r hash_generate[1].hash/final/memory_reg_0_i_101/CO[3] - net (fo=1, routed) 0.008 17.841 hash_generate[1].hash/final/memory_reg_0_i_101_n_0 - SLICE_X59Y175 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.899 r hash_generate[1].hash/final/memory_reg_0_i_106/CO[3] - net (fo=1, routed) 0.000 17.899 hash_generate[1].hash/final/memory_reg_0_i_106_n_0 - SLICE_X59Y176 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 18.038 r hash_generate[1].hash/final/memory_reg_0_i_98/O[0] - net (fo=1, routed) 0.548 18.586 hash_generate[1].hash/final/memory_reg_0_i_98_n_7 - SLICE_X60Y173 LUT3 (Prop_lut3_I2_O) 0.155 18.741 r hash_generate[1].hash/final/memory_reg_0_i_60__0/O - net (fo=1, routed) 0.000 18.741 hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0 - SLICE_X60Y173 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 18.976 r hash_generate[1].hash/final/memory_reg_0_i_29/CO[3] - net (fo=1, routed) 0.000 18.976 hash_generate[1].hash/final/memory_reg_0_i_29_n_0 - SLICE_X60Y174 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 19.189 r hash_generate[1].hash/final/memory_reg_0_i_26/O[1] - net (fo=3, routed) 0.557 19.747 hash_generate[1].hash/final/memory_reg_0_i_26_n_6 - SLICE_X52Y174 LUT3 (Prop_lut3_I2_O) 0.152 19.899 r hash_generate[1].hash/final/memory_reg_0_i_24__0/O - net (fo=1, routed) 0.000 19.899 hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0 - SLICE_X52Y174 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 20.223 r hash_generate[1].hash/final/memory_reg_0_i_4/CO[3] - net (fo=1, routed) 0.008 20.231 hash_generate[1].hash/final/memory_reg_0_i_4_n_0 - SLICE_X52Y175 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 20.444 r hash_generate[1].hash/final/memory_reg_0_i_3/O[1] - net (fo=9, routed) 0.944 21.388 storage_generate[1].storage/O76[5] - RAMB36_X2Y32 RAMB36E1 r storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[9] + RAMB36_X2Y14 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[14]) + 2.080 2.752 r storage_generate[3].storage/memory_reg_3/DOBDO[14] + net (fo=1, routed) 1.081 3.833 storage_generate[3].storage/memory_rule[3][68] + SLICE_X52Y82 LUT6 (Prop_lut6_I1_O) 0.053 3.886 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_117/O + net (fo=1, routed) 0.000 3.886 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_117_n_0 + SLICE_X52Y82 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 4.210 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_99/CO[3] + net (fo=1, routed) 0.000 4.210 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_99_n_0 + SLICE_X52Y83 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.268 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_84/CO[3] + net (fo=1, routed) 0.000 4.268 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_84_n_0 + SLICE_X52Y84 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.326 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_69/CO[3] + net (fo=1, routed) 0.000 4.326 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_69_n_0 + SLICE_X52Y85 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.384 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_54/CO[3] + net (fo=1, routed) 0.000 4.384 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_54_n_0 + SLICE_X52Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.442 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_39/CO[3] + net (fo=1, routed) 0.000 4.442 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_39_n_0 + SLICE_X52Y87 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.500 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_25/CO[3] + net (fo=1, routed) 0.000 4.500 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_25_n_0 + SLICE_X52Y88 CARRY4 (Prop_carry4_CI_CO[2]) + 0.132 4.632 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_14/CO[2] + net (fo=2, routed) 0.247 4.878 storage_generate[3].storage/out_key_found1 + SLICE_X55Y88 LUT2 (Prop_lut2_I0_O) 0.161 5.039 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_5/O + net (fo=16, routed) 0.597 5.636 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[0] + SLICE_X56Y87 LUT6 (Prop_lut6_I1_O) 0.053 5.689 r storage_generate[2].storage/registered_output.OUTPUT_DATA[11]_i_1/O + net (fo=1, routed) 0.000 5.689 out_data[11] + SLICE_X56Y87 FDRE r registered_output.OUTPUT_DATA_reg[11]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 4.000 4.000 r 0.000 4.000 r CLK (IN) - net (fo=668, unset) 0.638 4.638 storage_generate[1].storage/CLK - RAMB36_X2Y32 RAMB36E1 r storage_generate[1].storage/memory_reg_1/CLKBWRCLK + net (fo=5071, unset) 0.638 4.638 CLK + SLICE_X56Y87 FDRE r registered_output.OUTPUT_DATA_reg[11]/C clock pessimism 0.000 4.638 clock uncertainty -0.035 4.603 - RAMB36_X2Y32 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[9]) - -0.578 4.025 storage_generate[1].storage/memory_reg_1 + SLICE_X56Y87 FDRE (Setup_fdre_C_D) 0.035 4.638 registered_output.OUTPUT_DATA_reg[11] ------------------------------------------------------------------- - required time 4.025 - arrival time -21.388 + required time 4.638 + arrival time -5.689 ------------------------------------------------------------------- - slack -17.363 + slack -1.051 -Slack (VIOLATED) : -17.342ns (required time - arrival time) - Source: registered_input.in_key_reg[64]_replica_5/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[14] +Slack (VIOLATED) : -1.047ns (required time - arrival time) + Source: storage_generate[3].storage/memory_reg_3/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[15]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 20.695ns (logic 9.869ns (47.688%) route 10.826ns (52.312%)) - Logic Levels: 56 (CARRY4=41 LUT2=1 LUT3=8 LUT5=3 LUT6=3) + Data Path Delay: 5.013ns (logic 3.093ns (61.696%) route 1.920ns (38.304%)) + Logic Levels: 10 (CARRY4=7 LUT2=1 LUT6=2) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) Source Clock Delay (SCD): 0.672ns @@ -838,191 +484,65 @@ Slack (VIOLATED) : -17.342ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.672 0.672 CLK - SLICE_X43Y171 FDRE r registered_input.in_key_reg[64]_replica_5/C + net (fo=5071, unset) 0.672 0.672 storage_generate[3].storage/CLK + RAMB36_X2Y14 RAMB36E1 r storage_generate[3].storage/memory_reg_3/CLKBWRCLK ------------------------------------------------------------------- ------------------- - SLICE_X43Y171 FDRE (Prop_fdre_C_Q) 0.269 0.941 r registered_input.in_key_reg[64]_replica_5/Q - net (fo=5, routed) 0.321 1.262 hash_generate[1].hash/mix_pipeline[0].mix/in_key[64]_repN_5_alias - SLICE_X41Y170 CARRY4 (Prop_carry4_CYINIT_CO[3]) - 0.346 1.608 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, routed) 0.000 1.608 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - SLICE_X41Y171 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 1.747 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[0] - net (fo=18, routed) 0.541 2.287 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559_n_7 - SLICE_X38Y168 LUT2 (Prop_lut2_I1_O) 0.155 2.442 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1/O - net (fo=1, routed) 0.000 2.442 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1_n_0 - SLICE_X38Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 2.752 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] - net (fo=1, routed) 0.000 2.752 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 - SLICE_X38Y169 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 2.964 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] - net (fo=12, routed) 0.584 3.548 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] - SLICE_X44Y169 LUT3 (Prop_lut3_I1_O) 0.155 3.703 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O - net (fo=1, routed) 0.000 3.703 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 - SLICE_X44Y169 CARRY4 (Prop_carry4_S[1]_O[3]) - 0.374 4.077 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[3] - net (fo=8, routed) 0.489 4.566 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[11] - SLICE_X46Y168 LUT3 (Prop_lut3_I0_O) 0.142 4.708 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_734/O - net (fo=10, routed) 0.699 5.407 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_0 - SLICE_X47Y169 LUT6 (Prop_lut6_I3_O) 0.053 5.460 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O - net (fo=1, routed) 0.000 5.460 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 - SLICE_X47Y169 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.233 5.693 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568/CO[3] - net (fo=1, routed) 0.000 5.693 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568_n_0 - SLICE_X47Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 5.906 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/O[1] - net (fo=8, routed) 0.601 6.506 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[12] - SLICE_X49Y168 LUT5 (Prop_lut5_I4_O) 0.152 6.658 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1/O - net (fo=1, routed) 0.000 6.658 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1_n_0 - SLICE_X49Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 6.982 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291/CO[3] - net (fo=1, routed) 0.000 6.982 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291_n_0 - SLICE_X49Y169 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 7.195 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[1] - net (fo=5, routed) 0.631 7.826 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[16] - SLICE_X48Y166 LUT5 (Prop_lut5_I4_O) 0.152 7.978 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_280/O - net (fo=4, routed) 0.698 8.676 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[17] - SLICE_X51Y169 LUT6 (Prop_lut6_I4_O) 0.053 8.729 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009/O - net (fo=1, routed) 0.000 8.729 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009_n_0 - SLICE_X51Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 9.053 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] - net (fo=1, routed) 0.000 9.053 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 - SLICE_X51Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 9.266 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] - net (fo=4, routed) 0.600 9.866 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - SLICE_X50Y169 LUT5 (Prop_lut5_I1_O) 0.152 10.018 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155/O - net (fo=1, routed) 0.000 10.018 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155_n_0 - SLICE_X50Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 10.328 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107/CO[3] - net (fo=1, routed) 0.000 10.328 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107_n_0 - SLICE_X50Y170 CARRY4 (Prop_carry4_CI_O[3]) - 0.181 10.509 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1109/O[3] - net (fo=2, routed) 0.522 11.031 hash_generate[1].hash/final/minusOp1_out[27] - SLICE_X52Y173 LUT6 (Prop_lut6_I5_O) 0.142 11.173 r hash_generate[1].hash/final/memory_reg_0_i_874/O - net (fo=1, routed) 0.644 11.817 hash_generate[1].hash/final/L8_out[27] - SLICE_X52Y170 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.230 12.047 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, routed) 0.000 12.047 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 - SLICE_X52Y171 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 12.260 r hash_generate[1].hash/final/memory_reg_0_i_562/O[1] - net (fo=5, routed) 0.578 12.839 hash_generate[1].hash/final/memory_reg_0_i_810__0[5] - SLICE_X56Y170 LUT3 (Prop_lut3_I2_O) 0.152 12.991 r hash_generate[1].hash/final/memory_reg_0_i_322__0/O - net (fo=1, routed) 0.000 12.991 hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0 - SLICE_X56Y170 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.313 13.304 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, routed) 0.000 13.304 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 - SLICE_X56Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.362 r hash_generate[1].hash/final/memory_reg_0_i_259/CO[3] - net (fo=1, routed) 0.000 13.362 hash_generate[1].hash/final/memory_reg_0_i_259_n_0 - SLICE_X56Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.420 r hash_generate[1].hash/final/memory_reg_0_i_258/CO[3] - net (fo=1, routed) 0.000 13.420 hash_generate[1].hash/final/memory_reg_0_i_258_n_0 - SLICE_X56Y173 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 13.633 r hash_generate[1].hash/final/memory_reg_0_i_285/O[1] - net (fo=5, routed) 0.646 14.279 hash_generate[1].hash/final/memory_reg_0_i_357__0[4] - SLICE_X57Y169 LUT3 (Prop_lut3_I2_O) 0.152 14.431 r hash_generate[1].hash/final/memory_reg_0_i_237__0/O - net (fo=1, routed) 0.000 14.431 hash_generate[1].hash/final/memory_reg_0_i_237__0_n_0 - SLICE_X57Y169 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 14.666 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, routed) 0.000 14.666 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 - SLICE_X57Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 14.879 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, routed) 0.635 15.514 hash_generate[1].hash/final/minusOp8_out[17] - SLICE_X58Y167 LUT3 (Prop_lut3_I2_O) 0.152 15.666 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O - net (fo=1, routed) 0.000 15.666 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 - SLICE_X58Y167 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.976 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, routed) 0.000 15.976 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 - SLICE_X58Y168 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.036 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, routed) 0.000 16.036 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 - SLICE_X58Y169 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.096 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, routed) 0.000 16.096 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 - SLICE_X58Y170 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.156 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, routed) 0.000 16.156 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 - SLICE_X58Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.216 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, routed) 0.000 16.216 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 - SLICE_X58Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.276 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, routed) 0.000 16.276 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 - SLICE_X58Y173 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.336 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, routed) 0.000 16.336 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 - SLICE_X58Y174 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 16.548 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, routed) 0.574 17.123 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] - SLICE_X59Y170 LUT3 (Prop_lut3_I2_O) 0.155 17.278 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O - net (fo=1, routed) 0.000 17.278 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 - SLICE_X59Y170 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 17.602 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, routed) 0.000 17.602 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 - SLICE_X59Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.660 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, routed) 0.000 17.660 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 - SLICE_X59Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.718 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, routed) 0.000 17.718 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 - SLICE_X59Y173 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.776 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, routed) 0.000 17.776 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 - SLICE_X59Y174 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.834 r hash_generate[1].hash/final/memory_reg_0_i_101/CO[3] - net (fo=1, routed) 0.008 17.841 hash_generate[1].hash/final/memory_reg_0_i_101_n_0 - SLICE_X59Y175 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.899 r hash_generate[1].hash/final/memory_reg_0_i_106/CO[3] - net (fo=1, routed) 0.000 17.899 hash_generate[1].hash/final/memory_reg_0_i_106_n_0 - SLICE_X59Y176 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 18.038 r hash_generate[1].hash/final/memory_reg_0_i_98/O[0] - net (fo=1, routed) 0.548 18.586 hash_generate[1].hash/final/memory_reg_0_i_98_n_7 - SLICE_X60Y173 LUT3 (Prop_lut3_I2_O) 0.155 18.741 r hash_generate[1].hash/final/memory_reg_0_i_60__0/O - net (fo=1, routed) 0.000 18.741 hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0 - SLICE_X60Y173 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 18.976 r hash_generate[1].hash/final/memory_reg_0_i_29/CO[3] - net (fo=1, routed) 0.000 18.976 hash_generate[1].hash/final/memory_reg_0_i_29_n_0 - SLICE_X60Y174 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 19.189 r hash_generate[1].hash/final/memory_reg_0_i_26/O[1] - net (fo=3, routed) 0.557 19.747 hash_generate[1].hash/final/memory_reg_0_i_26_n_6 - SLICE_X52Y174 LUT3 (Prop_lut3_I2_O) 0.152 19.899 r hash_generate[1].hash/final/memory_reg_0_i_24__0/O - net (fo=1, routed) 0.000 19.899 hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0 - SLICE_X52Y174 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 20.223 r hash_generate[1].hash/final/memory_reg_0_i_4/CO[3] - net (fo=1, routed) 0.008 20.231 hash_generate[1].hash/final/memory_reg_0_i_4_n_0 - SLICE_X52Y175 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 20.289 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] - net (fo=1, routed) 0.000 20.289 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 - SLICE_X52Y176 CARRY4 (Prop_carry4_CI_O[2]) - 0.136 20.425 r hash_generate[1].hash/final/memory_reg_0_i_2/O[2] - net (fo=9, routed) 0.942 21.367 storage_generate[1].storage/O76[10] - RAMB36_X2Y37 RAMB36E1 r storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[14] + RAMB36_X2Y14 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[14]) + 2.080 2.752 r storage_generate[3].storage/memory_reg_3/DOBDO[14] + net (fo=1, routed) 1.081 3.833 storage_generate[3].storage/memory_rule[3][68] + SLICE_X52Y82 LUT6 (Prop_lut6_I1_O) 0.053 3.886 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_117/O + net (fo=1, routed) 0.000 3.886 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_117_n_0 + SLICE_X52Y82 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 4.210 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_99/CO[3] + net (fo=1, routed) 0.000 4.210 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_99_n_0 + SLICE_X52Y83 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.268 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_84/CO[3] + net (fo=1, routed) 0.000 4.268 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_84_n_0 + SLICE_X52Y84 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.326 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_69/CO[3] + net (fo=1, routed) 0.000 4.326 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_69_n_0 + SLICE_X52Y85 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.384 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_54/CO[3] + net (fo=1, routed) 0.000 4.384 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_54_n_0 + SLICE_X52Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.442 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_39/CO[3] + net (fo=1, routed) 0.000 4.442 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_39_n_0 + SLICE_X52Y87 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.500 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_25/CO[3] + net (fo=1, routed) 0.000 4.500 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_25_n_0 + SLICE_X52Y88 CARRY4 (Prop_carry4_CI_CO[2]) + 0.132 4.632 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_14/CO[2] + net (fo=2, routed) 0.247 4.878 storage_generate[3].storage/out_key_found1 + SLICE_X55Y88 LUT2 (Prop_lut2_I0_O) 0.161 5.039 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_5/O + net (fo=16, routed) 0.593 5.632 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[0] + SLICE_X57Y87 LUT6 (Prop_lut6_I1_O) 0.053 5.685 r storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_1/O + net (fo=1, routed) 0.000 5.685 out_data[15] + SLICE_X57Y87 FDRE r registered_output.OUTPUT_DATA_reg[15]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 4.000 4.000 r 0.000 4.000 r CLK (IN) - net (fo=668, unset) 0.638 4.638 storage_generate[1].storage/CLK - RAMB36_X2Y37 RAMB36E1 r storage_generate[1].storage/memory_reg_2/CLKBWRCLK + net (fo=5071, unset) 0.638 4.638 CLK + SLICE_X57Y87 FDRE r registered_output.OUTPUT_DATA_reg[15]/C clock pessimism 0.000 4.638 clock uncertainty -0.035 4.603 - RAMB36_X2Y37 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[14]) - -0.578 4.025 storage_generate[1].storage/memory_reg_2 + SLICE_X57Y87 FDRE (Setup_fdre_C_D) 0.035 4.638 registered_output.OUTPUT_DATA_reg[15] ------------------------------------------------------------------- - required time 4.025 - arrival time -21.367 + required time 4.638 + arrival time -5.685 ------------------------------------------------------------------- - slack -17.342 + slack -1.047 -Slack (VIOLATED) : -17.335ns (required time - arrival time) - Source: registered_input.in_key_reg[64]_replica_5/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[13] +Slack (VIOLATED) : -1.045ns (required time - arrival time) + Source: storage_generate[2].storage/memory_reg_0/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[12]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 20.688ns (logic 9.946ns (48.077%) route 10.742ns (51.923%)) - Logic Levels: 56 (CARRY4=41 LUT2=1 LUT3=8 LUT5=3 LUT6=3) + Data Path Delay: 5.011ns (logic 3.314ns (66.133%) route 1.697ns (33.867%)) + Logic Levels: 14 (CARRY4=11 LUT6=3) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) Source Clock Delay (SCD): 0.672ns @@ -1037,191 +557,77 @@ Slack (VIOLATED) : -17.335ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.672 0.672 CLK - SLICE_X43Y171 FDRE r registered_input.in_key_reg[64]_replica_5/C + net (fo=5071, unset) 0.672 0.672 storage_generate[2].storage/CLK + RAMB36_X3Y11 RAMB36E1 r storage_generate[2].storage/memory_reg_0/CLKBWRCLK ------------------------------------------------------------------- ------------------- - SLICE_X43Y171 FDRE (Prop_fdre_C_Q) 0.269 0.941 r registered_input.in_key_reg[64]_replica_5/Q - net (fo=5, routed) 0.321 1.262 hash_generate[1].hash/mix_pipeline[0].mix/in_key[64]_repN_5_alias - SLICE_X41Y170 CARRY4 (Prop_carry4_CYINIT_CO[3]) - 0.346 1.608 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, routed) 0.000 1.608 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - SLICE_X41Y171 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 1.747 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[0] - net (fo=18, routed) 0.541 2.287 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559_n_7 - SLICE_X38Y168 LUT2 (Prop_lut2_I1_O) 0.155 2.442 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1/O - net (fo=1, routed) 0.000 2.442 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1_n_0 - SLICE_X38Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 2.752 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] - net (fo=1, routed) 0.000 2.752 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 - SLICE_X38Y169 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 2.964 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] - net (fo=12, routed) 0.584 3.548 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] - SLICE_X44Y169 LUT3 (Prop_lut3_I1_O) 0.155 3.703 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O - net (fo=1, routed) 0.000 3.703 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 - SLICE_X44Y169 CARRY4 (Prop_carry4_S[1]_O[3]) - 0.374 4.077 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[3] - net (fo=8, routed) 0.489 4.566 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[11] - SLICE_X46Y168 LUT3 (Prop_lut3_I0_O) 0.142 4.708 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_734/O - net (fo=10, routed) 0.699 5.407 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_0 - SLICE_X47Y169 LUT6 (Prop_lut6_I3_O) 0.053 5.460 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O - net (fo=1, routed) 0.000 5.460 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 - SLICE_X47Y169 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.233 5.693 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568/CO[3] - net (fo=1, routed) 0.000 5.693 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568_n_0 - SLICE_X47Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 5.906 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/O[1] - net (fo=8, routed) 0.601 6.506 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[12] - SLICE_X49Y168 LUT5 (Prop_lut5_I4_O) 0.152 6.658 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1/O - net (fo=1, routed) 0.000 6.658 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1_n_0 - SLICE_X49Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 6.982 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291/CO[3] - net (fo=1, routed) 0.000 6.982 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291_n_0 - SLICE_X49Y169 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 7.195 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[1] - net (fo=5, routed) 0.631 7.826 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[16] - SLICE_X48Y166 LUT5 (Prop_lut5_I4_O) 0.152 7.978 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_280/O - net (fo=4, routed) 0.698 8.676 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[17] - SLICE_X51Y169 LUT6 (Prop_lut6_I4_O) 0.053 8.729 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009/O - net (fo=1, routed) 0.000 8.729 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009_n_0 - SLICE_X51Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 9.053 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] - net (fo=1, routed) 0.000 9.053 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 - SLICE_X51Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 9.266 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] - net (fo=4, routed) 0.600 9.866 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - SLICE_X50Y169 LUT5 (Prop_lut5_I1_O) 0.152 10.018 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155/O - net (fo=1, routed) 0.000 10.018 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155_n_0 - SLICE_X50Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 10.328 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107/CO[3] - net (fo=1, routed) 0.000 10.328 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107_n_0 - SLICE_X50Y170 CARRY4 (Prop_carry4_CI_O[3]) - 0.181 10.509 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1109/O[3] - net (fo=2, routed) 0.522 11.031 hash_generate[1].hash/final/minusOp1_out[27] - SLICE_X52Y173 LUT6 (Prop_lut6_I5_O) 0.142 11.173 r hash_generate[1].hash/final/memory_reg_0_i_874/O - net (fo=1, routed) 0.644 11.817 hash_generate[1].hash/final/L8_out[27] - SLICE_X52Y170 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.230 12.047 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, routed) 0.000 12.047 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 - SLICE_X52Y171 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 12.260 r hash_generate[1].hash/final/memory_reg_0_i_562/O[1] - net (fo=5, routed) 0.578 12.839 hash_generate[1].hash/final/memory_reg_0_i_810__0[5] - SLICE_X56Y170 LUT3 (Prop_lut3_I2_O) 0.152 12.991 r hash_generate[1].hash/final/memory_reg_0_i_322__0/O - net (fo=1, routed) 0.000 12.991 hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0 - SLICE_X56Y170 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.313 13.304 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, routed) 0.000 13.304 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 - SLICE_X56Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.362 r hash_generate[1].hash/final/memory_reg_0_i_259/CO[3] - net (fo=1, routed) 0.000 13.362 hash_generate[1].hash/final/memory_reg_0_i_259_n_0 - SLICE_X56Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.420 r hash_generate[1].hash/final/memory_reg_0_i_258/CO[3] - net (fo=1, routed) 0.000 13.420 hash_generate[1].hash/final/memory_reg_0_i_258_n_0 - SLICE_X56Y173 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 13.633 r hash_generate[1].hash/final/memory_reg_0_i_285/O[1] - net (fo=5, routed) 0.646 14.279 hash_generate[1].hash/final/memory_reg_0_i_357__0[4] - SLICE_X57Y169 LUT3 (Prop_lut3_I2_O) 0.152 14.431 r hash_generate[1].hash/final/memory_reg_0_i_237__0/O - net (fo=1, routed) 0.000 14.431 hash_generate[1].hash/final/memory_reg_0_i_237__0_n_0 - SLICE_X57Y169 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 14.666 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, routed) 0.000 14.666 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 - SLICE_X57Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 14.879 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, routed) 0.635 15.514 hash_generate[1].hash/final/minusOp8_out[17] - SLICE_X58Y167 LUT3 (Prop_lut3_I2_O) 0.152 15.666 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O - net (fo=1, routed) 0.000 15.666 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 - SLICE_X58Y167 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.976 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, routed) 0.000 15.976 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 - SLICE_X58Y168 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.036 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, routed) 0.000 16.036 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 - SLICE_X58Y169 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.096 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, routed) 0.000 16.096 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 - SLICE_X58Y170 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.156 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, routed) 0.000 16.156 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 - SLICE_X58Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.216 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, routed) 0.000 16.216 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 - SLICE_X58Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.276 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, routed) 0.000 16.276 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 - SLICE_X58Y173 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.336 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, routed) 0.000 16.336 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 - SLICE_X58Y174 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 16.548 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, routed) 0.574 17.123 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] - SLICE_X59Y170 LUT3 (Prop_lut3_I2_O) 0.155 17.278 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O - net (fo=1, routed) 0.000 17.278 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 - SLICE_X59Y170 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 17.602 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, routed) 0.000 17.602 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 - SLICE_X59Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.660 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, routed) 0.000 17.660 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 - SLICE_X59Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.718 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, routed) 0.000 17.718 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 - SLICE_X59Y173 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.776 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, routed) 0.000 17.776 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 - SLICE_X59Y174 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.834 r hash_generate[1].hash/final/memory_reg_0_i_101/CO[3] - net (fo=1, routed) 0.008 17.841 hash_generate[1].hash/final/memory_reg_0_i_101_n_0 - SLICE_X59Y175 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.899 r hash_generate[1].hash/final/memory_reg_0_i_106/CO[3] - net (fo=1, routed) 0.000 17.899 hash_generate[1].hash/final/memory_reg_0_i_106_n_0 - SLICE_X59Y176 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 18.038 r hash_generate[1].hash/final/memory_reg_0_i_98/O[0] - net (fo=1, routed) 0.548 18.586 hash_generate[1].hash/final/memory_reg_0_i_98_n_7 - SLICE_X60Y173 LUT3 (Prop_lut3_I2_O) 0.155 18.741 r hash_generate[1].hash/final/memory_reg_0_i_60__0/O - net (fo=1, routed) 0.000 18.741 hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0 - SLICE_X60Y173 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 18.976 r hash_generate[1].hash/final/memory_reg_0_i_29/CO[3] - net (fo=1, routed) 0.000 18.976 hash_generate[1].hash/final/memory_reg_0_i_29_n_0 - SLICE_X60Y174 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 19.189 r hash_generate[1].hash/final/memory_reg_0_i_26/O[1] - net (fo=3, routed) 0.557 19.747 hash_generate[1].hash/final/memory_reg_0_i_26_n_6 - SLICE_X52Y174 LUT3 (Prop_lut3_I2_O) 0.152 19.899 r hash_generate[1].hash/final/memory_reg_0_i_24__0/O - net (fo=1, routed) 0.000 19.899 hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0 - SLICE_X52Y174 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 20.223 r hash_generate[1].hash/final/memory_reg_0_i_4/CO[3] - net (fo=1, routed) 0.008 20.231 hash_generate[1].hash/final/memory_reg_0_i_4_n_0 - SLICE_X52Y175 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 20.289 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] - net (fo=1, routed) 0.000 20.289 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 - SLICE_X52Y176 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 20.502 r hash_generate[1].hash/final/memory_reg_0_i_2/O[1] - net (fo=9, routed) 0.858 21.360 storage_generate[1].storage/O76[9] - RAMB36_X2Y33 RAMB36E1 r storage_generate[1].storage/memory_reg_0/ADDRBWRADDR[13] + RAMB36_X3Y11 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOPBDOP[1]) + 2.080 2.752 r storage_generate[2].storage/memory_reg_0/DOPBDOP[1] + net (fo=1, routed) 0.909 3.661 storage_generate[2].storage/memory_rule[2][17] + SLICE_X60Y78 LUT6 (Prop_lut6_I5_O) 0.053 3.714 r storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_56/O + net (fo=1, routed) 0.000 3.714 storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_56_n_0 + SLICE_X60Y78 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.313 4.027 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48/CO[3] + net (fo=1, routed) 0.000 4.027 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48_n_0 + SLICE_X60Y79 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.085 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43/CO[3] + net (fo=1, routed) 0.000 4.085 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43_n_0 + SLICE_X60Y80 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.143 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38/CO[3] + net (fo=1, routed) 0.000 4.143 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38_n_0 + SLICE_X60Y81 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.201 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33/CO[3] + net (fo=1, routed) 0.000 4.201 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33_n_0 + SLICE_X60Y82 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.259 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28/CO[3] + net (fo=1, routed) 0.000 4.259 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28_n_0 + SLICE_X60Y83 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.317 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23/CO[3] + net (fo=1, routed) 0.000 4.317 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23_n_0 + SLICE_X60Y84 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.375 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18/CO[3] + net (fo=1, routed) 0.000 4.375 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18_n_0 + SLICE_X60Y85 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.433 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13/CO[3] + net (fo=1, routed) 0.000 4.433 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13_n_0 + SLICE_X60Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.491 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8/CO[3] + net (fo=1, routed) 0.000 4.491 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8_n_0 + SLICE_X60Y87 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.549 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4/CO[3] + net (fo=1, routed) 0.000 4.549 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4_n_0 + SLICE_X60Y88 CARRY4 (Prop_carry4_CI_CO[2]) + 0.132 4.681 r storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_2/CO[2] + net (fo=33, routed) 0.547 5.228 storage_generate[1].storage/CO[0] + SLICE_X59Y86 LUT6 (Prop_lut6_I4_O) 0.161 5.389 r storage_generate[1].storage/registered_output.OUTPUT_DATA[12]_i_2/O + net (fo=1, routed) 0.241 5.630 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[12] + SLICE_X57Y87 LUT6 (Prop_lut6_I5_O) 0.053 5.683 r storage_generate[2].storage/registered_output.OUTPUT_DATA[12]_i_1/O + net (fo=1, routed) 0.000 5.683 out_data[12] + SLICE_X57Y87 FDRE r registered_output.OUTPUT_DATA_reg[12]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 4.000 4.000 r 0.000 4.000 r CLK (IN) - net (fo=668, unset) 0.638 4.638 storage_generate[1].storage/CLK - RAMB36_X2Y33 RAMB36E1 r storage_generate[1].storage/memory_reg_0/CLKBWRCLK + net (fo=5071, unset) 0.638 4.638 CLK + SLICE_X57Y87 FDRE r registered_output.OUTPUT_DATA_reg[12]/C clock pessimism 0.000 4.638 clock uncertainty -0.035 4.603 - RAMB36_X2Y33 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[13]) - -0.578 4.025 storage_generate[1].storage/memory_reg_0 + SLICE_X57Y87 FDRE (Setup_fdre_C_D) 0.035 4.638 registered_output.OUTPUT_DATA_reg[12] ------------------------------------------------------------------- - required time 4.025 - arrival time -21.360 + required time 4.638 + arrival time -5.683 ------------------------------------------------------------------- - slack -17.335 + slack -1.045 -Slack (VIOLATED) : -17.331ns (required time - arrival time) - Source: registered_input.in_key_reg[64]_replica_5/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[14] +Slack (VIOLATED) : -1.030ns (required time - arrival time) + Source: storage_generate[3].storage/memory_reg_3/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[10]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 20.684ns (logic 9.869ns (47.714%) route 10.815ns (52.286%)) - Logic Levels: 56 (CARRY4=41 LUT2=1 LUT3=8 LUT5=3 LUT6=3) + Data Path Delay: 4.996ns (logic 3.093ns (61.911%) route 1.903ns (38.089%)) + Logic Levels: 10 (CARRY4=7 LUT2=1 LUT6=2) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) Source Clock Delay (SCD): 0.672ns @@ -1236,191 +642,65 @@ Slack (VIOLATED) : -17.331ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.672 0.672 CLK - SLICE_X43Y171 FDRE r registered_input.in_key_reg[64]_replica_5/C + net (fo=5071, unset) 0.672 0.672 storage_generate[3].storage/CLK + RAMB36_X2Y14 RAMB36E1 r storage_generate[3].storage/memory_reg_3/CLKBWRCLK ------------------------------------------------------------------- ------------------- - SLICE_X43Y171 FDRE (Prop_fdre_C_Q) 0.269 0.941 r registered_input.in_key_reg[64]_replica_5/Q - net (fo=5, routed) 0.321 1.262 hash_generate[1].hash/mix_pipeline[0].mix/in_key[64]_repN_5_alias - SLICE_X41Y170 CARRY4 (Prop_carry4_CYINIT_CO[3]) - 0.346 1.608 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, routed) 0.000 1.608 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - SLICE_X41Y171 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 1.747 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[0] - net (fo=18, routed) 0.541 2.287 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559_n_7 - SLICE_X38Y168 LUT2 (Prop_lut2_I1_O) 0.155 2.442 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1/O - net (fo=1, routed) 0.000 2.442 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1_n_0 - SLICE_X38Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 2.752 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] - net (fo=1, routed) 0.000 2.752 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 - SLICE_X38Y169 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 2.964 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] - net (fo=12, routed) 0.584 3.548 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] - SLICE_X44Y169 LUT3 (Prop_lut3_I1_O) 0.155 3.703 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O - net (fo=1, routed) 0.000 3.703 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 - SLICE_X44Y169 CARRY4 (Prop_carry4_S[1]_O[3]) - 0.374 4.077 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[3] - net (fo=8, routed) 0.489 4.566 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[11] - SLICE_X46Y168 LUT3 (Prop_lut3_I0_O) 0.142 4.708 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_734/O - net (fo=10, routed) 0.699 5.407 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_0 - SLICE_X47Y169 LUT6 (Prop_lut6_I3_O) 0.053 5.460 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O - net (fo=1, routed) 0.000 5.460 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 - SLICE_X47Y169 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.233 5.693 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568/CO[3] - net (fo=1, routed) 0.000 5.693 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568_n_0 - SLICE_X47Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 5.906 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/O[1] - net (fo=8, routed) 0.601 6.506 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[12] - SLICE_X49Y168 LUT5 (Prop_lut5_I4_O) 0.152 6.658 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1/O - net (fo=1, routed) 0.000 6.658 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1_n_0 - SLICE_X49Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 6.982 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291/CO[3] - net (fo=1, routed) 0.000 6.982 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291_n_0 - SLICE_X49Y169 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 7.195 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[1] - net (fo=5, routed) 0.631 7.826 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[16] - SLICE_X48Y166 LUT5 (Prop_lut5_I4_O) 0.152 7.978 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_280/O - net (fo=4, routed) 0.698 8.676 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[17] - SLICE_X51Y169 LUT6 (Prop_lut6_I4_O) 0.053 8.729 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009/O - net (fo=1, routed) 0.000 8.729 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009_n_0 - SLICE_X51Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 9.053 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] - net (fo=1, routed) 0.000 9.053 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 - SLICE_X51Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 9.266 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] - net (fo=4, routed) 0.600 9.866 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - SLICE_X50Y169 LUT5 (Prop_lut5_I1_O) 0.152 10.018 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155/O - net (fo=1, routed) 0.000 10.018 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155_n_0 - SLICE_X50Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 10.328 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107/CO[3] - net (fo=1, routed) 0.000 10.328 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107_n_0 - SLICE_X50Y170 CARRY4 (Prop_carry4_CI_O[3]) - 0.181 10.509 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1109/O[3] - net (fo=2, routed) 0.522 11.031 hash_generate[1].hash/final/minusOp1_out[27] - SLICE_X52Y173 LUT6 (Prop_lut6_I5_O) 0.142 11.173 r hash_generate[1].hash/final/memory_reg_0_i_874/O - net (fo=1, routed) 0.644 11.817 hash_generate[1].hash/final/L8_out[27] - SLICE_X52Y170 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.230 12.047 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, routed) 0.000 12.047 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 - SLICE_X52Y171 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 12.260 r hash_generate[1].hash/final/memory_reg_0_i_562/O[1] - net (fo=5, routed) 0.578 12.839 hash_generate[1].hash/final/memory_reg_0_i_810__0[5] - SLICE_X56Y170 LUT3 (Prop_lut3_I2_O) 0.152 12.991 r hash_generate[1].hash/final/memory_reg_0_i_322__0/O - net (fo=1, routed) 0.000 12.991 hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0 - SLICE_X56Y170 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.313 13.304 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, routed) 0.000 13.304 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 - SLICE_X56Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.362 r hash_generate[1].hash/final/memory_reg_0_i_259/CO[3] - net (fo=1, routed) 0.000 13.362 hash_generate[1].hash/final/memory_reg_0_i_259_n_0 - SLICE_X56Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.420 r hash_generate[1].hash/final/memory_reg_0_i_258/CO[3] - net (fo=1, routed) 0.000 13.420 hash_generate[1].hash/final/memory_reg_0_i_258_n_0 - SLICE_X56Y173 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 13.633 r hash_generate[1].hash/final/memory_reg_0_i_285/O[1] - net (fo=5, routed) 0.646 14.279 hash_generate[1].hash/final/memory_reg_0_i_357__0[4] - SLICE_X57Y169 LUT3 (Prop_lut3_I2_O) 0.152 14.431 r hash_generate[1].hash/final/memory_reg_0_i_237__0/O - net (fo=1, routed) 0.000 14.431 hash_generate[1].hash/final/memory_reg_0_i_237__0_n_0 - SLICE_X57Y169 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 14.666 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, routed) 0.000 14.666 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 - SLICE_X57Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 14.879 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, routed) 0.635 15.514 hash_generate[1].hash/final/minusOp8_out[17] - SLICE_X58Y167 LUT3 (Prop_lut3_I2_O) 0.152 15.666 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O - net (fo=1, routed) 0.000 15.666 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 - SLICE_X58Y167 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.976 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, routed) 0.000 15.976 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 - SLICE_X58Y168 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.036 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, routed) 0.000 16.036 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 - SLICE_X58Y169 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.096 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, routed) 0.000 16.096 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 - SLICE_X58Y170 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.156 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, routed) 0.000 16.156 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 - SLICE_X58Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.216 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, routed) 0.000 16.216 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 - SLICE_X58Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.276 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, routed) 0.000 16.276 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 - SLICE_X58Y173 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.336 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, routed) 0.000 16.336 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 - SLICE_X58Y174 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 16.548 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, routed) 0.574 17.123 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] - SLICE_X59Y170 LUT3 (Prop_lut3_I2_O) 0.155 17.278 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O - net (fo=1, routed) 0.000 17.278 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 - SLICE_X59Y170 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 17.602 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, routed) 0.000 17.602 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 - SLICE_X59Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.660 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, routed) 0.000 17.660 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 - SLICE_X59Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.718 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, routed) 0.000 17.718 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 - SLICE_X59Y173 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.776 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, routed) 0.000 17.776 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 - SLICE_X59Y174 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.834 r hash_generate[1].hash/final/memory_reg_0_i_101/CO[3] - net (fo=1, routed) 0.008 17.841 hash_generate[1].hash/final/memory_reg_0_i_101_n_0 - SLICE_X59Y175 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.899 r hash_generate[1].hash/final/memory_reg_0_i_106/CO[3] - net (fo=1, routed) 0.000 17.899 hash_generate[1].hash/final/memory_reg_0_i_106_n_0 - SLICE_X59Y176 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 18.038 r hash_generate[1].hash/final/memory_reg_0_i_98/O[0] - net (fo=1, routed) 0.548 18.586 hash_generate[1].hash/final/memory_reg_0_i_98_n_7 - SLICE_X60Y173 LUT3 (Prop_lut3_I2_O) 0.155 18.741 r hash_generate[1].hash/final/memory_reg_0_i_60__0/O - net (fo=1, routed) 0.000 18.741 hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0 - SLICE_X60Y173 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 18.976 r hash_generate[1].hash/final/memory_reg_0_i_29/CO[3] - net (fo=1, routed) 0.000 18.976 hash_generate[1].hash/final/memory_reg_0_i_29_n_0 - SLICE_X60Y174 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 19.189 r hash_generate[1].hash/final/memory_reg_0_i_26/O[1] - net (fo=3, routed) 0.557 19.747 hash_generate[1].hash/final/memory_reg_0_i_26_n_6 - SLICE_X52Y174 LUT3 (Prop_lut3_I2_O) 0.152 19.899 r hash_generate[1].hash/final/memory_reg_0_i_24__0/O - net (fo=1, routed) 0.000 19.899 hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0 - SLICE_X52Y174 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 20.223 r hash_generate[1].hash/final/memory_reg_0_i_4/CO[3] - net (fo=1, routed) 0.008 20.231 hash_generate[1].hash/final/memory_reg_0_i_4_n_0 - SLICE_X52Y175 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 20.289 r hash_generate[1].hash/final/memory_reg_0_i_3/CO[3] - net (fo=1, routed) 0.000 20.289 hash_generate[1].hash/final/memory_reg_0_i_3_n_0 - SLICE_X52Y176 CARRY4 (Prop_carry4_CI_O[2]) - 0.136 20.425 r hash_generate[1].hash/final/memory_reg_0_i_2/O[2] - net (fo=9, routed) 0.931 21.356 storage_generate[1].storage/O76[10] - RAMB36_X3Y36 RAMB36E1 r storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[14] + RAMB36_X2Y14 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[14]) + 2.080 2.752 r storage_generate[3].storage/memory_reg_3/DOBDO[14] + net (fo=1, routed) 1.081 3.833 storage_generate[3].storage/memory_rule[3][68] + SLICE_X52Y82 LUT6 (Prop_lut6_I1_O) 0.053 3.886 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_117/O + net (fo=1, routed) 0.000 3.886 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_117_n_0 + SLICE_X52Y82 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 4.210 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_99/CO[3] + net (fo=1, routed) 0.000 4.210 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_99_n_0 + SLICE_X52Y83 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.268 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_84/CO[3] + net (fo=1, routed) 0.000 4.268 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_84_n_0 + SLICE_X52Y84 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.326 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_69/CO[3] + net (fo=1, routed) 0.000 4.326 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_69_n_0 + SLICE_X52Y85 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.384 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_54/CO[3] + net (fo=1, routed) 0.000 4.384 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_54_n_0 + SLICE_X52Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.442 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_39/CO[3] + net (fo=1, routed) 0.000 4.442 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_39_n_0 + SLICE_X52Y87 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.500 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_25/CO[3] + net (fo=1, routed) 0.000 4.500 storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_25_n_0 + SLICE_X52Y88 CARRY4 (Prop_carry4_CI_CO[2]) + 0.132 4.632 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_14/CO[2] + net (fo=2, routed) 0.247 4.878 storage_generate[3].storage/out_key_found1 + SLICE_X55Y88 LUT2 (Prop_lut2_I0_O) 0.161 5.039 r storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_5/O + net (fo=16, routed) 0.575 5.615 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[0] + SLICE_X59Y87 LUT6 (Prop_lut6_I1_O) 0.053 5.668 r storage_generate[2].storage/registered_output.OUTPUT_DATA[10]_i_1/O + net (fo=1, routed) 0.000 5.668 out_data[10] + SLICE_X59Y87 FDRE r registered_output.OUTPUT_DATA_reg[10]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 4.000 4.000 r 0.000 4.000 r CLK (IN) - net (fo=668, unset) 0.638 4.638 storage_generate[1].storage/CLK - RAMB36_X3Y36 RAMB36E1 r storage_generate[1].storage/memory_reg_7/CLKBWRCLK + net (fo=5071, unset) 0.638 4.638 CLK + SLICE_X59Y87 FDRE r registered_output.OUTPUT_DATA_reg[10]/C clock pessimism 0.000 4.638 clock uncertainty -0.035 4.603 - RAMB36_X3Y36 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[14]) - -0.578 4.025 storage_generate[1].storage/memory_reg_7 + SLICE_X59Y87 FDRE (Setup_fdre_C_D) 0.035 4.638 registered_output.OUTPUT_DATA_reg[10] ------------------------------------------------------------------- - required time 4.025 - arrival time -21.356 + required time 4.638 + arrival time -5.668 ------------------------------------------------------------------- - slack -17.331 + slack -1.030 -Slack (VIOLATED) : -17.330ns (required time - arrival time) - Source: registered_input.in_key_reg[64]_replica_5/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[9] +Slack (VIOLATED) : -1.024ns (required time - arrival time) + Source: storage_generate[1].storage/memory_reg_2/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[8]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 20.683ns (logic 9.888ns (47.807%) route 10.795ns (52.193%)) - Logic Levels: 55 (CARRY4=40 LUT2=1 LUT3=8 LUT5=3 LUT6=3) + Data Path Delay: 4.990ns (logic 3.209ns (64.303%) route 1.781ns (35.697%)) + Logic Levels: 12 (CARRY4=9 LUT6=3) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) Source Clock Delay (SCD): 0.672ns @@ -1435,188 +715,71 @@ Slack (VIOLATED) : -17.330ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.672 0.672 CLK - SLICE_X43Y171 FDRE r registered_input.in_key_reg[64]_replica_5/C + net (fo=5071, unset) 0.672 0.672 storage_generate[1].storage/CLK + RAMB36_X3Y12 RAMB36E1 r storage_generate[1].storage/memory_reg_2/CLKBWRCLK ------------------------------------------------------------------- ------------------- - SLICE_X43Y171 FDRE (Prop_fdre_C_Q) 0.269 0.941 r registered_input.in_key_reg[64]_replica_5/Q - net (fo=5, routed) 0.321 1.262 hash_generate[1].hash/mix_pipeline[0].mix/in_key[64]_repN_5_alias - SLICE_X41Y170 CARRY4 (Prop_carry4_CYINIT_CO[3]) - 0.346 1.608 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, routed) 0.000 1.608 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - SLICE_X41Y171 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 1.747 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[0] - net (fo=18, routed) 0.541 2.287 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559_n_7 - SLICE_X38Y168 LUT2 (Prop_lut2_I1_O) 0.155 2.442 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1/O - net (fo=1, routed) 0.000 2.442 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1_n_0 - SLICE_X38Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 2.752 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] - net (fo=1, routed) 0.000 2.752 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 - SLICE_X38Y169 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 2.964 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] - net (fo=12, routed) 0.584 3.548 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] - SLICE_X44Y169 LUT3 (Prop_lut3_I1_O) 0.155 3.703 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O - net (fo=1, routed) 0.000 3.703 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 - SLICE_X44Y169 CARRY4 (Prop_carry4_S[1]_O[3]) - 0.374 4.077 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[3] - net (fo=8, routed) 0.489 4.566 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[11] - SLICE_X46Y168 LUT3 (Prop_lut3_I0_O) 0.142 4.708 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_734/O - net (fo=10, routed) 0.699 5.407 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_0 - SLICE_X47Y169 LUT6 (Prop_lut6_I3_O) 0.053 5.460 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O - net (fo=1, routed) 0.000 5.460 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 - SLICE_X47Y169 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.233 5.693 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568/CO[3] - net (fo=1, routed) 0.000 5.693 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568_n_0 - SLICE_X47Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 5.906 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/O[1] - net (fo=8, routed) 0.601 6.506 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[12] - SLICE_X49Y168 LUT5 (Prop_lut5_I4_O) 0.152 6.658 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1/O - net (fo=1, routed) 0.000 6.658 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1_n_0 - SLICE_X49Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 6.982 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291/CO[3] - net (fo=1, routed) 0.000 6.982 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291_n_0 - SLICE_X49Y169 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 7.195 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[1] - net (fo=5, routed) 0.631 7.826 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[16] - SLICE_X48Y166 LUT5 (Prop_lut5_I4_O) 0.152 7.978 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_280/O - net (fo=4, routed) 0.698 8.676 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[17] - SLICE_X51Y169 LUT6 (Prop_lut6_I4_O) 0.053 8.729 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009/O - net (fo=1, routed) 0.000 8.729 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009_n_0 - SLICE_X51Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 9.053 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] - net (fo=1, routed) 0.000 9.053 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 - SLICE_X51Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 9.266 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] - net (fo=4, routed) 0.600 9.866 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - SLICE_X50Y169 LUT5 (Prop_lut5_I1_O) 0.152 10.018 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155/O - net (fo=1, routed) 0.000 10.018 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155_n_0 - SLICE_X50Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 10.328 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107/CO[3] - net (fo=1, routed) 0.000 10.328 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107_n_0 - SLICE_X50Y170 CARRY4 (Prop_carry4_CI_O[3]) - 0.181 10.509 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1109/O[3] - net (fo=2, routed) 0.522 11.031 hash_generate[1].hash/final/minusOp1_out[27] - SLICE_X52Y173 LUT6 (Prop_lut6_I5_O) 0.142 11.173 r hash_generate[1].hash/final/memory_reg_0_i_874/O - net (fo=1, routed) 0.644 11.817 hash_generate[1].hash/final/L8_out[27] - SLICE_X52Y170 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.230 12.047 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, routed) 0.000 12.047 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 - SLICE_X52Y171 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 12.260 r hash_generate[1].hash/final/memory_reg_0_i_562/O[1] - net (fo=5, routed) 0.578 12.839 hash_generate[1].hash/final/memory_reg_0_i_810__0[5] - SLICE_X56Y170 LUT3 (Prop_lut3_I2_O) 0.152 12.991 r hash_generate[1].hash/final/memory_reg_0_i_322__0/O - net (fo=1, routed) 0.000 12.991 hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0 - SLICE_X56Y170 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.313 13.304 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, routed) 0.000 13.304 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 - SLICE_X56Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.362 r hash_generate[1].hash/final/memory_reg_0_i_259/CO[3] - net (fo=1, routed) 0.000 13.362 hash_generate[1].hash/final/memory_reg_0_i_259_n_0 - SLICE_X56Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.420 r hash_generate[1].hash/final/memory_reg_0_i_258/CO[3] - net (fo=1, routed) 0.000 13.420 hash_generate[1].hash/final/memory_reg_0_i_258_n_0 - SLICE_X56Y173 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 13.633 r hash_generate[1].hash/final/memory_reg_0_i_285/O[1] - net (fo=5, routed) 0.646 14.279 hash_generate[1].hash/final/memory_reg_0_i_357__0[4] - SLICE_X57Y169 LUT3 (Prop_lut3_I2_O) 0.152 14.431 r hash_generate[1].hash/final/memory_reg_0_i_237__0/O - net (fo=1, routed) 0.000 14.431 hash_generate[1].hash/final/memory_reg_0_i_237__0_n_0 - SLICE_X57Y169 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 14.666 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, routed) 0.000 14.666 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 - SLICE_X57Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 14.879 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, routed) 0.635 15.514 hash_generate[1].hash/final/minusOp8_out[17] - SLICE_X58Y167 LUT3 (Prop_lut3_I2_O) 0.152 15.666 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O - net (fo=1, routed) 0.000 15.666 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 - SLICE_X58Y167 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.976 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, routed) 0.000 15.976 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 - SLICE_X58Y168 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.036 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, routed) 0.000 16.036 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 - SLICE_X58Y169 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.096 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, routed) 0.000 16.096 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 - SLICE_X58Y170 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.156 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, routed) 0.000 16.156 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 - SLICE_X58Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.216 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, routed) 0.000 16.216 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 - SLICE_X58Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.276 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, routed) 0.000 16.276 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 - SLICE_X58Y173 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.336 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, routed) 0.000 16.336 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 - SLICE_X58Y174 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 16.548 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, routed) 0.574 17.123 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] - SLICE_X59Y170 LUT3 (Prop_lut3_I2_O) 0.155 17.278 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O - net (fo=1, routed) 0.000 17.278 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 - SLICE_X59Y170 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 17.602 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, routed) 0.000 17.602 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 - SLICE_X59Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.660 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, routed) 0.000 17.660 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 - SLICE_X59Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.718 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, routed) 0.000 17.718 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 - SLICE_X59Y173 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.776 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, routed) 0.000 17.776 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 - SLICE_X59Y174 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.834 r hash_generate[1].hash/final/memory_reg_0_i_101/CO[3] - net (fo=1, routed) 0.008 17.841 hash_generate[1].hash/final/memory_reg_0_i_101_n_0 - SLICE_X59Y175 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.899 r hash_generate[1].hash/final/memory_reg_0_i_106/CO[3] - net (fo=1, routed) 0.000 17.899 hash_generate[1].hash/final/memory_reg_0_i_106_n_0 - SLICE_X59Y176 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 18.038 r hash_generate[1].hash/final/memory_reg_0_i_98/O[0] - net (fo=1, routed) 0.548 18.586 hash_generate[1].hash/final/memory_reg_0_i_98_n_7 - SLICE_X60Y173 LUT3 (Prop_lut3_I2_O) 0.155 18.741 r hash_generate[1].hash/final/memory_reg_0_i_60__0/O - net (fo=1, routed) 0.000 18.741 hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0 - SLICE_X60Y173 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 18.976 r hash_generate[1].hash/final/memory_reg_0_i_29/CO[3] - net (fo=1, routed) 0.000 18.976 hash_generate[1].hash/final/memory_reg_0_i_29_n_0 - SLICE_X60Y174 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 19.189 r hash_generate[1].hash/final/memory_reg_0_i_26/O[1] - net (fo=3, routed) 0.557 19.747 hash_generate[1].hash/final/memory_reg_0_i_26_n_6 - SLICE_X52Y174 LUT3 (Prop_lut3_I2_O) 0.152 19.899 r hash_generate[1].hash/final/memory_reg_0_i_24__0/O - net (fo=1, routed) 0.000 19.899 hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0 - SLICE_X52Y174 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 20.223 r hash_generate[1].hash/final/memory_reg_0_i_4/CO[3] - net (fo=1, routed) 0.008 20.231 hash_generate[1].hash/final/memory_reg_0_i_4_n_0 - SLICE_X52Y175 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 20.444 r hash_generate[1].hash/final/memory_reg_0_i_3/O[1] - net (fo=9, routed) 0.911 21.355 storage_generate[1].storage/O76[5] - RAMB36_X2Y37 RAMB36E1 r storage_generate[1].storage/memory_reg_2/ADDRBWRADDR[9] + RAMB36_X3Y12 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[9]) + 2.080 2.752 r storage_generate[1].storage/memory_reg_2/DOBDO[9] + net (fo=1, routed) 1.081 3.833 storage_generate[1].storage/memory_rule[1][45] + SLICE_X61Y79 LUT6 (Prop_lut6_I5_O) 0.053 3.886 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122/O + net (fo=1, routed) 0.000 3.886 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122_n_0 + SLICE_X61Y79 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 4.210 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_104/CO[3] + net (fo=1, routed) 0.000 4.210 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_104_n_0 + SLICE_X61Y80 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.268 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_89/CO[3] + net (fo=1, routed) 0.000 4.268 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_89_n_0 + SLICE_X61Y81 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.326 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_74/CO[3] + net (fo=1, routed) 0.000 4.326 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_74_n_0 + SLICE_X61Y82 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.384 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_59/CO[3] + net (fo=1, routed) 0.000 4.384 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_59_n_0 + SLICE_X61Y83 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.442 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_44/CO[3] + net (fo=1, routed) 0.000 4.442 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_44_n_0 + SLICE_X61Y84 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.500 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_29/CO[3] + net (fo=1, routed) 0.000 4.500 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_29_n_0 + SLICE_X61Y85 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.558 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_15/CO[3] + net (fo=1, routed) 0.000 4.558 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_15_n_0 + SLICE_X61Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.616 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_6/CO[3] + net (fo=1, routed) 0.000 4.616 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_6_n_0 + SLICE_X61Y87 CARRY4 (Prop_carry4_CI_CO[2]) + 0.132 4.748 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_2/CO[2] + net (fo=17, routed) 0.405 5.153 storage_generate[1].storage/out_key_found13_out + SLICE_X59Y86 LUT6 (Prop_lut6_I3_O) 0.161 5.314 r storage_generate[1].storage/registered_output.OUTPUT_DATA[8]_i_2/O + net (fo=1, routed) 0.295 5.609 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[8] + SLICE_X57Y87 LUT6 (Prop_lut6_I5_O) 0.053 5.662 r storage_generate[2].storage/registered_output.OUTPUT_DATA[8]_i_1/O + net (fo=1, routed) 0.000 5.662 out_data[8] + SLICE_X57Y87 FDRE r registered_output.OUTPUT_DATA_reg[8]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 4.000 4.000 r 0.000 4.000 r CLK (IN) - net (fo=668, unset) 0.638 4.638 storage_generate[1].storage/CLK - RAMB36_X2Y37 RAMB36E1 r storage_generate[1].storage/memory_reg_2/CLKBWRCLK + net (fo=5071, unset) 0.638 4.638 CLK + SLICE_X57Y87 FDRE r registered_output.OUTPUT_DATA_reg[8]/C clock pessimism 0.000 4.638 clock uncertainty -0.035 4.603 - RAMB36_X2Y37 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[9]) - -0.578 4.025 storage_generate[1].storage/memory_reg_2 + SLICE_X57Y87 FDRE (Setup_fdre_C_D) 0.035 4.638 registered_output.OUTPUT_DATA_reg[8] ------------------------------------------------------------------- - required time 4.025 - arrival time -21.355 + required time 4.638 + arrival time -5.662 ------------------------------------------------------------------- - slack -17.330 + slack -1.024 -Slack (VIOLATED) : -17.310ns (required time - arrival time) - Source: registered_input.in_key_reg[64]_replica_5/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[10] +Slack (VIOLATED) : -0.993ns (required time - arrival time) + Source: storage_generate[1].storage/memory_reg_2/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[7]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 20.663ns (logic 9.811ns (47.480%) route 10.852ns (52.520%)) - Logic Levels: 55 (CARRY4=40 LUT2=1 LUT3=8 LUT5=3 LUT6=3) + Data Path Delay: 4.958ns (logic 3.209ns (64.721%) route 1.749ns (35.279%)) + Logic Levels: 12 (CARRY4=9 LUT6=3) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) Source Clock Delay (SCD): 0.672ns @@ -1631,188 +794,71 @@ Slack (VIOLATED) : -17.310ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.672 0.672 CLK - SLICE_X43Y171 FDRE r registered_input.in_key_reg[64]_replica_5/C + net (fo=5071, unset) 0.672 0.672 storage_generate[1].storage/CLK + RAMB36_X3Y12 RAMB36E1 r storage_generate[1].storage/memory_reg_2/CLKBWRCLK ------------------------------------------------------------------- ------------------- - SLICE_X43Y171 FDRE (Prop_fdre_C_Q) 0.269 0.941 r registered_input.in_key_reg[64]_replica_5/Q - net (fo=5, routed) 0.321 1.262 hash_generate[1].hash/mix_pipeline[0].mix/in_key[64]_repN_5_alias - SLICE_X41Y170 CARRY4 (Prop_carry4_CYINIT_CO[3]) - 0.346 1.608 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, routed) 0.000 1.608 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - SLICE_X41Y171 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 1.747 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[0] - net (fo=18, routed) 0.541 2.287 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559_n_7 - SLICE_X38Y168 LUT2 (Prop_lut2_I1_O) 0.155 2.442 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1/O - net (fo=1, routed) 0.000 2.442 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1_n_0 - SLICE_X38Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 2.752 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] - net (fo=1, routed) 0.000 2.752 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 - SLICE_X38Y169 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 2.964 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] - net (fo=12, routed) 0.584 3.548 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] - SLICE_X44Y169 LUT3 (Prop_lut3_I1_O) 0.155 3.703 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O - net (fo=1, routed) 0.000 3.703 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 - SLICE_X44Y169 CARRY4 (Prop_carry4_S[1]_O[3]) - 0.374 4.077 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[3] - net (fo=8, routed) 0.489 4.566 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[11] - SLICE_X46Y168 LUT3 (Prop_lut3_I0_O) 0.142 4.708 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_734/O - net (fo=10, routed) 0.699 5.407 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_0 - SLICE_X47Y169 LUT6 (Prop_lut6_I3_O) 0.053 5.460 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O - net (fo=1, routed) 0.000 5.460 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 - SLICE_X47Y169 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.233 5.693 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568/CO[3] - net (fo=1, routed) 0.000 5.693 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568_n_0 - SLICE_X47Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 5.906 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/O[1] - net (fo=8, routed) 0.601 6.506 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[12] - SLICE_X49Y168 LUT5 (Prop_lut5_I4_O) 0.152 6.658 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1/O - net (fo=1, routed) 0.000 6.658 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1_n_0 - SLICE_X49Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 6.982 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291/CO[3] - net (fo=1, routed) 0.000 6.982 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291_n_0 - SLICE_X49Y169 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 7.195 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[1] - net (fo=5, routed) 0.631 7.826 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[16] - SLICE_X48Y166 LUT5 (Prop_lut5_I4_O) 0.152 7.978 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_280/O - net (fo=4, routed) 0.698 8.676 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[17] - SLICE_X51Y169 LUT6 (Prop_lut6_I4_O) 0.053 8.729 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009/O - net (fo=1, routed) 0.000 8.729 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009_n_0 - SLICE_X51Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 9.053 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] - net (fo=1, routed) 0.000 9.053 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 - SLICE_X51Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 9.266 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] - net (fo=4, routed) 0.600 9.866 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - SLICE_X50Y169 LUT5 (Prop_lut5_I1_O) 0.152 10.018 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155/O - net (fo=1, routed) 0.000 10.018 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155_n_0 - SLICE_X50Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 10.328 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107/CO[3] - net (fo=1, routed) 0.000 10.328 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107_n_0 - SLICE_X50Y170 CARRY4 (Prop_carry4_CI_O[3]) - 0.181 10.509 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1109/O[3] - net (fo=2, routed) 0.522 11.031 hash_generate[1].hash/final/minusOp1_out[27] - SLICE_X52Y173 LUT6 (Prop_lut6_I5_O) 0.142 11.173 r hash_generate[1].hash/final/memory_reg_0_i_874/O - net (fo=1, routed) 0.644 11.817 hash_generate[1].hash/final/L8_out[27] - SLICE_X52Y170 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.230 12.047 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, routed) 0.000 12.047 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 - SLICE_X52Y171 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 12.260 r hash_generate[1].hash/final/memory_reg_0_i_562/O[1] - net (fo=5, routed) 0.578 12.839 hash_generate[1].hash/final/memory_reg_0_i_810__0[5] - SLICE_X56Y170 LUT3 (Prop_lut3_I2_O) 0.152 12.991 r hash_generate[1].hash/final/memory_reg_0_i_322__0/O - net (fo=1, routed) 0.000 12.991 hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0 - SLICE_X56Y170 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.313 13.304 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, routed) 0.000 13.304 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 - SLICE_X56Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.362 r hash_generate[1].hash/final/memory_reg_0_i_259/CO[3] - net (fo=1, routed) 0.000 13.362 hash_generate[1].hash/final/memory_reg_0_i_259_n_0 - SLICE_X56Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.420 r hash_generate[1].hash/final/memory_reg_0_i_258/CO[3] - net (fo=1, routed) 0.000 13.420 hash_generate[1].hash/final/memory_reg_0_i_258_n_0 - SLICE_X56Y173 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 13.633 r hash_generate[1].hash/final/memory_reg_0_i_285/O[1] - net (fo=5, routed) 0.646 14.279 hash_generate[1].hash/final/memory_reg_0_i_357__0[4] - SLICE_X57Y169 LUT3 (Prop_lut3_I2_O) 0.152 14.431 r hash_generate[1].hash/final/memory_reg_0_i_237__0/O - net (fo=1, routed) 0.000 14.431 hash_generate[1].hash/final/memory_reg_0_i_237__0_n_0 - SLICE_X57Y169 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 14.666 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, routed) 0.000 14.666 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 - SLICE_X57Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 14.879 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, routed) 0.635 15.514 hash_generate[1].hash/final/minusOp8_out[17] - SLICE_X58Y167 LUT3 (Prop_lut3_I2_O) 0.152 15.666 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O - net (fo=1, routed) 0.000 15.666 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 - SLICE_X58Y167 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.976 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, routed) 0.000 15.976 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 - SLICE_X58Y168 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.036 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, routed) 0.000 16.036 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 - SLICE_X58Y169 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.096 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, routed) 0.000 16.096 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 - SLICE_X58Y170 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.156 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, routed) 0.000 16.156 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 - SLICE_X58Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.216 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, routed) 0.000 16.216 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 - SLICE_X58Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.276 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, routed) 0.000 16.276 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 - SLICE_X58Y173 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.336 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, routed) 0.000 16.336 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 - SLICE_X58Y174 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 16.548 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, routed) 0.574 17.123 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] - SLICE_X59Y170 LUT3 (Prop_lut3_I2_O) 0.155 17.278 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O - net (fo=1, routed) 0.000 17.278 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 - SLICE_X59Y170 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 17.602 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, routed) 0.000 17.602 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 - SLICE_X59Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.660 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, routed) 0.000 17.660 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 - SLICE_X59Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.718 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, routed) 0.000 17.718 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 - SLICE_X59Y173 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.776 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, routed) 0.000 17.776 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 - SLICE_X59Y174 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.834 r hash_generate[1].hash/final/memory_reg_0_i_101/CO[3] - net (fo=1, routed) 0.008 17.841 hash_generate[1].hash/final/memory_reg_0_i_101_n_0 - SLICE_X59Y175 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.899 r hash_generate[1].hash/final/memory_reg_0_i_106/CO[3] - net (fo=1, routed) 0.000 17.899 hash_generate[1].hash/final/memory_reg_0_i_106_n_0 - SLICE_X59Y176 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 18.038 r hash_generate[1].hash/final/memory_reg_0_i_98/O[0] - net (fo=1, routed) 0.548 18.586 hash_generate[1].hash/final/memory_reg_0_i_98_n_7 - SLICE_X60Y173 LUT3 (Prop_lut3_I2_O) 0.155 18.741 r hash_generate[1].hash/final/memory_reg_0_i_60__0/O - net (fo=1, routed) 0.000 18.741 hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0 - SLICE_X60Y173 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 18.976 r hash_generate[1].hash/final/memory_reg_0_i_29/CO[3] - net (fo=1, routed) 0.000 18.976 hash_generate[1].hash/final/memory_reg_0_i_29_n_0 - SLICE_X60Y174 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 19.189 r hash_generate[1].hash/final/memory_reg_0_i_26/O[1] - net (fo=3, routed) 0.557 19.747 hash_generate[1].hash/final/memory_reg_0_i_26_n_6 - SLICE_X52Y174 LUT3 (Prop_lut3_I2_O) 0.152 19.899 r hash_generate[1].hash/final/memory_reg_0_i_24__0/O - net (fo=1, routed) 0.000 19.899 hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0 - SLICE_X52Y174 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 20.223 r hash_generate[1].hash/final/memory_reg_0_i_4/CO[3] - net (fo=1, routed) 0.008 20.231 hash_generate[1].hash/final/memory_reg_0_i_4_n_0 - SLICE_X52Y175 CARRY4 (Prop_carry4_CI_O[2]) - 0.136 20.367 r hash_generate[1].hash/final/memory_reg_0_i_3/O[2] - net (fo=9, routed) 0.969 21.335 storage_generate[1].storage/O76[6] - RAMB36_X2Y32 RAMB36E1 r storage_generate[1].storage/memory_reg_1/ADDRBWRADDR[10] + RAMB36_X3Y12 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[9]) + 2.080 2.752 r storage_generate[1].storage/memory_reg_2/DOBDO[9] + net (fo=1, routed) 1.081 3.833 storage_generate[1].storage/memory_rule[1][45] + SLICE_X61Y79 LUT6 (Prop_lut6_I5_O) 0.053 3.886 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122/O + net (fo=1, routed) 0.000 3.886 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122_n_0 + SLICE_X61Y79 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 4.210 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_104/CO[3] + net (fo=1, routed) 0.000 4.210 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_104_n_0 + SLICE_X61Y80 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.268 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_89/CO[3] + net (fo=1, routed) 0.000 4.268 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_89_n_0 + SLICE_X61Y81 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.326 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_74/CO[3] + net (fo=1, routed) 0.000 4.326 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_74_n_0 + SLICE_X61Y82 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.384 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_59/CO[3] + net (fo=1, routed) 0.000 4.384 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_59_n_0 + SLICE_X61Y83 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.442 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_44/CO[3] + net (fo=1, routed) 0.000 4.442 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_44_n_0 + SLICE_X61Y84 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.500 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_29/CO[3] + net (fo=1, routed) 0.000 4.500 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_29_n_0 + SLICE_X61Y85 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.558 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_15/CO[3] + net (fo=1, routed) 0.000 4.558 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_15_n_0 + SLICE_X61Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.616 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_6/CO[3] + net (fo=1, routed) 0.000 4.616 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_6_n_0 + SLICE_X61Y87 CARRY4 (Prop_carry4_CI_CO[2]) + 0.132 4.748 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_2/CO[2] + net (fo=17, routed) 0.425 5.173 storage_generate[1].storage/out_key_found13_out + SLICE_X58Y86 LUT6 (Prop_lut6_I3_O) 0.161 5.334 r storage_generate[1].storage/registered_output.OUTPUT_DATA[7]_i_2/O + net (fo=1, routed) 0.243 5.577 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[7] + SLICE_X59Y88 LUT6 (Prop_lut6_I5_O) 0.053 5.630 r storage_generate[2].storage/registered_output.OUTPUT_DATA[7]_i_1/O + net (fo=1, routed) 0.000 5.630 out_data[7] + SLICE_X59Y88 FDRE r registered_output.OUTPUT_DATA_reg[7]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 4.000 4.000 r 0.000 4.000 r CLK (IN) - net (fo=668, unset) 0.638 4.638 storage_generate[1].storage/CLK - RAMB36_X2Y32 RAMB36E1 r storage_generate[1].storage/memory_reg_1/CLKBWRCLK + net (fo=5071, unset) 0.638 4.638 CLK + SLICE_X59Y88 FDRE r registered_output.OUTPUT_DATA_reg[7]/C clock pessimism 0.000 4.638 clock uncertainty -0.035 4.603 - RAMB36_X2Y32 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[10]) - -0.578 4.025 storage_generate[1].storage/memory_reg_1 + SLICE_X59Y88 FDRE (Setup_fdre_C_D) 0.034 4.637 registered_output.OUTPUT_DATA_reg[7] ------------------------------------------------------------------- - required time 4.025 - arrival time -21.335 + required time 4.637 + arrival time -5.630 ------------------------------------------------------------------- - slack -17.310 + slack -0.993 -Slack (VIOLATED) : -17.309ns (required time - arrival time) - Source: registered_input.in_key_reg[64]_replica_5/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[9] +Slack (VIOLATED) : -0.985ns (required time - arrival time) + Source: storage_generate[1].storage/memory_reg_2/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[3]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 20.662ns (logic 9.888ns (47.855%) route 10.774ns (52.145%)) - Logic Levels: 55 (CARRY4=40 LUT2=1 LUT3=8 LUT5=3 LUT6=3) + Data Path Delay: 4.951ns (logic 3.209ns (64.809%) route 1.742ns (35.191%)) + Logic Levels: 12 (CARRY4=9 LUT6=3) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) Source Clock Delay (SCD): 0.672ns @@ -1827,188 +873,71 @@ Slack (VIOLATED) : -17.309ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.672 0.672 CLK - SLICE_X43Y171 FDRE r registered_input.in_key_reg[64]_replica_5/C + net (fo=5071, unset) 0.672 0.672 storage_generate[1].storage/CLK + RAMB36_X3Y12 RAMB36E1 r storage_generate[1].storage/memory_reg_2/CLKBWRCLK ------------------------------------------------------------------- ------------------- - SLICE_X43Y171 FDRE (Prop_fdre_C_Q) 0.269 0.941 r registered_input.in_key_reg[64]_replica_5/Q - net (fo=5, routed) 0.321 1.262 hash_generate[1].hash/mix_pipeline[0].mix/in_key[64]_repN_5_alias - SLICE_X41Y170 CARRY4 (Prop_carry4_CYINIT_CO[3]) - 0.346 1.608 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591/CO[3] - net (fo=1, routed) 0.000 1.608 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_591_n_0 - SLICE_X41Y171 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 1.747 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559/O[0] - net (fo=18, routed) 0.541 2.287 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_559_n_7 - SLICE_X38Y168 LUT2 (Prop_lut2_I1_O) 0.155 2.442 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1/O - net (fo=1, routed) 0.000 2.442 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_894__1_n_0 - SLICE_X38Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 2.752 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592/CO[3] - net (fo=1, routed) 0.000 2.752 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_592_n_0 - SLICE_X38Y169 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 2.964 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_560/O[1] - net (fo=12, routed) 0.584 3.548 hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[9] - SLICE_X44Y169 LUT3 (Prop_lut3_I1_O) 0.155 3.703 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953/O - net (fo=1, routed) 0.000 3.703 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_953_n_0 - SLICE_X44Y169 CARRY4 (Prop_carry4_S[1]_O[3]) - 0.374 4.077 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_642/O[3] - net (fo=8, routed) 0.489 4.566 hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[11] - SLICE_X46Y168 LUT3 (Prop_lut3_I0_O) 0.142 4.708 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_734/O - net (fo=10, routed) 0.699 5.407 hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[64]_0 - SLICE_X47Y169 LUT6 (Prop_lut6_I3_O) 0.053 5.460 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O - net (fo=1, routed) 0.000 5.460 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 - SLICE_X47Y169 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.233 5.693 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568/CO[3] - net (fo=1, routed) 0.000 5.693 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_568_n_0 - SLICE_X47Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 5.906 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_686/O[1] - net (fo=8, routed) 0.601 6.506 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[12] - SLICE_X49Y168 LUT5 (Prop_lut5_I4_O) 0.152 6.658 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1/O - net (fo=1, routed) 0.000 6.658 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_503__1_n_0 - SLICE_X49Y168 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 6.982 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291/CO[3] - net (fo=1, routed) 0.000 6.982 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_291_n_0 - SLICE_X49Y169 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 7.195 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_270/O[1] - net (fo=5, routed) 0.631 7.826 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1018_0[16] - SLICE_X48Y166 LUT5 (Prop_lut5_I4_O) 0.152 7.978 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_280/O - net (fo=4, routed) 0.698 8.676 hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]13_out[17] - SLICE_X51Y169 LUT6 (Prop_lut6_I4_O) 0.053 8.729 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009/O - net (fo=1, routed) 0.000 8.729 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1009_n_0 - SLICE_X51Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 9.053 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682/CO[3] - net (fo=1, routed) 0.000 9.053 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_682_n_0 - SLICE_X51Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 9.266 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_732/O[1] - net (fo=4, routed) 0.600 9.866 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21] - SLICE_X50Y169 LUT5 (Prop_lut5_I1_O) 0.152 10.018 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155/O - net (fo=1, routed) 0.000 10.018 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1155_n_0 - SLICE_X50Y169 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 10.328 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107/CO[3] - net (fo=1, routed) 0.000 10.328 hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1107_n_0 - SLICE_X50Y170 CARRY4 (Prop_carry4_CI_O[3]) - 0.181 10.509 r hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1109/O[3] - net (fo=2, routed) 0.522 11.031 hash_generate[1].hash/final/minusOp1_out[27] - SLICE_X52Y173 LUT6 (Prop_lut6_I5_O) 0.142 11.173 r hash_generate[1].hash/final/memory_reg_0_i_874/O - net (fo=1, routed) 0.644 11.817 hash_generate[1].hash/final/L8_out[27] - SLICE_X52Y170 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.230 12.047 r hash_generate[1].hash/final/memory_reg_0_i_580/CO[3] - net (fo=1, routed) 0.000 12.047 hash_generate[1].hash/final/memory_reg_0_i_580_n_0 - SLICE_X52Y171 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 12.260 r hash_generate[1].hash/final/memory_reg_0_i_562/O[1] - net (fo=5, routed) 0.578 12.839 hash_generate[1].hash/final/memory_reg_0_i_810__0[5] - SLICE_X56Y170 LUT3 (Prop_lut3_I2_O) 0.152 12.991 r hash_generate[1].hash/final/memory_reg_0_i_322__0/O - net (fo=1, routed) 0.000 12.991 hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0 - SLICE_X56Y170 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.313 13.304 r hash_generate[1].hash/final/memory_reg_0_i_256/CO[3] - net (fo=1, routed) 0.000 13.304 hash_generate[1].hash/final/memory_reg_0_i_256_n_0 - SLICE_X56Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.362 r hash_generate[1].hash/final/memory_reg_0_i_259/CO[3] - net (fo=1, routed) 0.000 13.362 hash_generate[1].hash/final/memory_reg_0_i_259_n_0 - SLICE_X56Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.420 r hash_generate[1].hash/final/memory_reg_0_i_258/CO[3] - net (fo=1, routed) 0.000 13.420 hash_generate[1].hash/final/memory_reg_0_i_258_n_0 - SLICE_X56Y173 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 13.633 r hash_generate[1].hash/final/memory_reg_0_i_285/O[1] - net (fo=5, routed) 0.646 14.279 hash_generate[1].hash/final/memory_reg_0_i_357__0[4] - SLICE_X57Y169 LUT3 (Prop_lut3_I2_O) 0.152 14.431 r hash_generate[1].hash/final/memory_reg_0_i_237__0/O - net (fo=1, routed) 0.000 14.431 hash_generate[1].hash/final/memory_reg_0_i_237__0_n_0 - SLICE_X57Y169 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 14.666 r hash_generate[1].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, routed) 0.000 14.666 hash_generate[1].hash/final/memory_reg_0_i_110_n_0 - SLICE_X57Y170 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 14.879 r hash_generate[1].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, routed) 0.635 15.514 hash_generate[1].hash/final/minusOp8_out[17] - SLICE_X58Y167 LUT3 (Prop_lut3_I2_O) 0.152 15.666 r hash_generate[1].hash/final/memory_reg_0_i_93__0/O - net (fo=1, routed) 0.000 15.666 hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0 - SLICE_X58Y167 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.310 15.976 r hash_generate[1].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, routed) 0.000 15.976 hash_generate[1].hash/final/memory_reg_0_i_33_n_0 - SLICE_X58Y168 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.036 r hash_generate[1].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, routed) 0.000 16.036 hash_generate[1].hash/final/memory_reg_0_i_30_n_0 - SLICE_X58Y169 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.096 r hash_generate[1].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, routed) 0.000 16.096 hash_generate[1].hash/final/memory_reg_0_i_27_n_0 - SLICE_X58Y170 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.156 r hash_generate[1].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, routed) 0.000 16.156 hash_generate[1].hash/final/memory_reg_0_i_283_n_0 - SLICE_X58Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.216 r hash_generate[1].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, routed) 0.000 16.216 hash_generate[1].hash/final/memory_reg_0_i_282_n_0 - SLICE_X58Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.276 r hash_generate[1].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, routed) 0.000 16.276 hash_generate[1].hash/final/memory_reg_0_i_264_n_0 - SLICE_X58Y173 CARRY4 (Prop_carry4_CI_CO[3]) - 0.060 16.336 r hash_generate[1].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, routed) 0.000 16.336 hash_generate[1].hash/final/memory_reg_0_i_262_n_0 - SLICE_X58Y174 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 16.548 r hash_generate[1].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, routed) 0.574 17.123 hash_generate[1].hash/final/memory_reg_0_i_350__0[5] - SLICE_X59Y170 LUT3 (Prop_lut3_I2_O) 0.155 17.278 r hash_generate[1].hash/final/memory_reg_0_i_190__0/O - net (fo=1, routed) 0.000 17.278 hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0 - SLICE_X59Y170 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 17.602 r hash_generate[1].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, routed) 0.000 17.602 hash_generate[1].hash/final/memory_reg_0_i_104_n_0 - SLICE_X59Y171 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.660 r hash_generate[1].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, routed) 0.000 17.660 hash_generate[1].hash/final/memory_reg_0_i_103_n_0 - SLICE_X59Y172 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.718 r hash_generate[1].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, routed) 0.000 17.718 hash_generate[1].hash/final/memory_reg_0_i_95_n_0 - SLICE_X59Y173 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.776 r hash_generate[1].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, routed) 0.000 17.776 hash_generate[1].hash/final/memory_reg_0_i_109_n_0 - SLICE_X59Y174 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.834 r hash_generate[1].hash/final/memory_reg_0_i_101/CO[3] - net (fo=1, routed) 0.008 17.841 hash_generate[1].hash/final/memory_reg_0_i_101_n_0 - SLICE_X59Y175 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.899 r hash_generate[1].hash/final/memory_reg_0_i_106/CO[3] - net (fo=1, routed) 0.000 17.899 hash_generate[1].hash/final/memory_reg_0_i_106_n_0 - SLICE_X59Y176 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 18.038 r hash_generate[1].hash/final/memory_reg_0_i_98/O[0] - net (fo=1, routed) 0.548 18.586 hash_generate[1].hash/final/memory_reg_0_i_98_n_7 - SLICE_X60Y173 LUT3 (Prop_lut3_I2_O) 0.155 18.741 r hash_generate[1].hash/final/memory_reg_0_i_60__0/O - net (fo=1, routed) 0.000 18.741 hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0 - SLICE_X60Y173 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 18.976 r hash_generate[1].hash/final/memory_reg_0_i_29/CO[3] - net (fo=1, routed) 0.000 18.976 hash_generate[1].hash/final/memory_reg_0_i_29_n_0 - SLICE_X60Y174 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 19.189 r hash_generate[1].hash/final/memory_reg_0_i_26/O[1] - net (fo=3, routed) 0.557 19.747 hash_generate[1].hash/final/memory_reg_0_i_26_n_6 - SLICE_X52Y174 LUT3 (Prop_lut3_I2_O) 0.152 19.899 r hash_generate[1].hash/final/memory_reg_0_i_24__0/O - net (fo=1, routed) 0.000 19.899 hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0 - SLICE_X52Y174 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 20.223 r hash_generate[1].hash/final/memory_reg_0_i_4/CO[3] - net (fo=1, routed) 0.008 20.231 hash_generate[1].hash/final/memory_reg_0_i_4_n_0 - SLICE_X52Y175 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 20.444 r hash_generate[1].hash/final/memory_reg_0_i_3/O[1] - net (fo=9, routed) 0.891 21.334 storage_generate[1].storage/O76[5] - RAMB36_X3Y36 RAMB36E1 r storage_generate[1].storage/memory_reg_7/ADDRBWRADDR[9] + RAMB36_X3Y12 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[9]) + 2.080 2.752 r storage_generate[1].storage/memory_reg_2/DOBDO[9] + net (fo=1, routed) 1.081 3.833 storage_generate[1].storage/memory_rule[1][45] + SLICE_X61Y79 LUT6 (Prop_lut6_I5_O) 0.053 3.886 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122/O + net (fo=1, routed) 0.000 3.886 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122_n_0 + SLICE_X61Y79 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 4.210 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_104/CO[3] + net (fo=1, routed) 0.000 4.210 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_104_n_0 + SLICE_X61Y80 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.268 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_89/CO[3] + net (fo=1, routed) 0.000 4.268 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_89_n_0 + SLICE_X61Y81 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.326 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_74/CO[3] + net (fo=1, routed) 0.000 4.326 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_74_n_0 + SLICE_X61Y82 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.384 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_59/CO[3] + net (fo=1, routed) 0.000 4.384 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_59_n_0 + SLICE_X61Y83 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.442 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_44/CO[3] + net (fo=1, routed) 0.000 4.442 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_44_n_0 + SLICE_X61Y84 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.500 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_29/CO[3] + net (fo=1, routed) 0.000 4.500 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_29_n_0 + SLICE_X61Y85 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.558 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_15/CO[3] + net (fo=1, routed) 0.000 4.558 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_15_n_0 + SLICE_X61Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.616 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_6/CO[3] + net (fo=1, routed) 0.000 4.616 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_6_n_0 + SLICE_X61Y87 CARRY4 (Prop_carry4_CI_CO[2]) + 0.132 4.748 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_2/CO[2] + net (fo=17, routed) 0.430 5.178 storage_generate[1].storage/out_key_found13_out + SLICE_X58Y88 LUT6 (Prop_lut6_I3_O) 0.161 5.339 r storage_generate[1].storage/registered_output.OUTPUT_DATA[3]_i_2/O + net (fo=1, routed) 0.231 5.570 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[3] + SLICE_X57Y88 LUT6 (Prop_lut6_I5_O) 0.053 5.623 r storage_generate[2].storage/registered_output.OUTPUT_DATA[3]_i_1/O + net (fo=1, routed) 0.000 5.623 out_data[3] + SLICE_X57Y88 FDRE r registered_output.OUTPUT_DATA_reg[3]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 4.000 4.000 r 0.000 4.000 r CLK (IN) - net (fo=668, unset) 0.638 4.638 storage_generate[1].storage/CLK - RAMB36_X3Y36 RAMB36E1 r storage_generate[1].storage/memory_reg_7/CLKBWRCLK + net (fo=5071, unset) 0.638 4.638 CLK + SLICE_X57Y88 FDRE r registered_output.OUTPUT_DATA_reg[3]/C clock pessimism 0.000 4.638 clock uncertainty -0.035 4.603 - RAMB36_X3Y36 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[9]) - -0.578 4.025 storage_generate[1].storage/memory_reg_7 + SLICE_X57Y88 FDRE (Setup_fdre_C_D) 0.035 4.638 registered_output.OUTPUT_DATA_reg[3] ------------------------------------------------------------------- - required time 4.025 - arrival time -21.334 + required time 4.638 + arrival time -5.623 ------------------------------------------------------------------- - slack -17.309 + slack -0.985 -Slack (VIOLATED) : -17.298ns (required time - arrival time) - Source: registered_input.in_key_reg[65]/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[14] +Slack (VIOLATED) : -0.982ns (required time - arrival time) + Source: storage_generate[1].storage/memory_reg_2/CLKBWRCLK (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: registered_output.OUTPUT_DATA_reg[0]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Setup (Max at Slow Process Corner) Requirement: 4.000ns (CLK rise@4.000ns - CLK rise@0.000ns) - Data Path Delay: 20.651ns (logic 9.316ns (45.111%) route 11.335ns (54.889%)) - Logic Levels: 52 (CARRY4=37 LUT2=1 LUT3=8 LUT5=4 LUT6=2) + Data Path Delay: 4.948ns (logic 3.209ns (64.857%) route 1.739ns (35.143%)) + Logic Levels: 12 (CARRY4=9 LUT6=3) Clock Path Skew: -0.034ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 0.638ns = ( 4.638 - 4.000 ) Source Clock Delay (SCD): 0.672ns @@ -2023,168 +952,60 @@ Slack (VIOLATED) : -17.298ns (required time - arrival time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.672 0.672 CLK - SLICE_X40Y170 FDRE r registered_input.in_key_reg[65]/C + net (fo=5071, unset) 0.672 0.672 storage_generate[1].storage/CLK + RAMB36_X3Y12 RAMB36E1 r storage_generate[1].storage/memory_reg_2/CLKBWRCLK ------------------------------------------------------------------- ------------------- - SLICE_X40Y170 FDRE (Prop_fdre_C_Q) 0.308 0.980 r registered_input.in_key_reg[65]/Q - net (fo=4, routed) 0.474 1.454 hash_generate[2].hash/mix_pipeline[0].mix/Q[61] - SLICE_X40Y172 CARRY4 (Prop_carry4_DI[1]_O[2]) - 0.326 1.780 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_419__0/O[2] - net (fo=18, routed) 0.571 2.351 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_419__0_n_5 - SLICE_X43Y175 LUT2 (Prop_lut2_I1_O) 0.152 2.503 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_900__2/O - net (fo=1, routed) 0.000 2.503 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_900__2_n_0 - SLICE_X43Y175 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.235 2.738 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_594/CO[3] - net (fo=1, routed) 0.000 2.738 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_594_n_0 - SLICE_X43Y176 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 2.951 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_591/O[1] - net (fo=11, routed) 0.626 3.577 hash_generate[2].hash/mix_pipeline[0].mix/minusOp14_out[5] - SLICE_X47Y179 LUT3 (Prop_lut3_I1_O) 0.152 3.729 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_896__0/O - net (fo=1, routed) 0.000 3.729 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_896__0_n_0 - SLICE_X47Y179 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 4.053 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_593/CO[3] - net (fo=1, routed) 0.000 4.053 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_593_n_0 - SLICE_X47Y180 CARRY4 (Prop_carry4_CI_O[0]) - 0.139 4.192 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_641/O[0] - net (fo=9, routed) 0.578 4.771 hash_generate[2].hash/mix_pipeline[0].mix/minusOp12_out[8] - SLICE_X48Y180 LUT3 (Prop_lut3_I0_O) 0.155 4.926 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_682/O - net (fo=11, routed) 0.487 5.413 hash_generate[2].hash/mix_pipeline[0].mix/registered_input.in_key_reg[94] - SLICE_X49Y180 LUT6 (Prop_lut6_I0_O) 0.053 5.466 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_823/O - net (fo=1, routed) 0.000 5.466 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_823_n_0 - SLICE_X49Y180 CARRY4 (Prop_carry4_S[1]_O[2]) - 0.345 5.811 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_568/O[2] - net (fo=8, routed) 0.601 6.411 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[9] - SLICE_X50Y181 LUT5 (Prop_lut5_I4_O) 0.152 6.563 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_546__1/O - net (fo=1, routed) 0.000 6.563 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_546__1_n_0 - SLICE_X50Y181 CARRY4 (Prop_carry4_S[2]_CO[3]) - 0.219 6.782 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_306/CO[3] - net (fo=1, routed) 0.000 6.782 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_306_n_0 - SLICE_X50Y182 CARRY4 (Prop_carry4_CI_O[2]) - 0.137 6.919 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_291/O[2] - net (fo=5, routed) 0.402 7.322 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1012__1_0[13] - SLICE_X48Y180 LUT5 (Prop_lut5_I4_O) 0.152 7.474 f hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_298__1/O - net (fo=4, routed) 0.382 7.856 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_298__1_n_0 - SLICE_X53Y180 LUT5 (Prop_lut5_I4_O) 0.053 7.909 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1062__1/O - net (fo=1, routed) 0.778 8.687 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1062__1_n_0 - SLICE_X51Y183 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.230 8.917 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_741/CO[3] - net (fo=1, routed) 0.000 8.917 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_741_n_0 - SLICE_X51Y184 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 9.130 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_681/O[1] - net (fo=4, routed) 0.734 9.864 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[17] - SLICE_X56Y185 LUT5 (Prop_lut5_I1_O) 0.152 10.016 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1147__1/O - net (fo=1, routed) 0.000 10.016 hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1147__1_n_0 - SLICE_X56Y185 CARRY4 (Prop_carry4_S[1]_O[3]) - 0.379 10.395 r hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1099/O[3] - net (fo=2, routed) 0.550 10.945 hash_generate[2].hash/final/minusOp1_out[19] - SLICE_X55Y185 LUT6 (Prop_lut6_I5_O) 0.142 11.087 r hash_generate[2].hash/final/memory_reg_0_i_829/O - net (fo=1, routed) 0.501 11.588 hash_generate[2].hash/final/L8_out[19] - SLICE_X54Y188 CARRY4 (Prop_carry4_DI[3]_CO[3]) - 0.234 11.822 r hash_generate[2].hash/final/memory_reg_0_i_573/CO[3] - net (fo=1, routed) 0.000 11.822 hash_generate[2].hash/final/memory_reg_0_i_573_n_0 - SLICE_X54Y189 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 12.034 r hash_generate[2].hash/final/memory_reg_0_i_579/O[1] - net (fo=5, routed) 0.696 12.730 hash_generate[2].hash/final/minusOp12_out[21] - SLICE_X55Y186 LUT3 (Prop_lut3_I2_O) 0.155 12.885 r hash_generate[2].hash/final/memory_reg_0_i_444__0/O - net (fo=1, routed) 0.000 12.885 hash_generate[2].hash/final/memory_reg_0_i_444__0_n_0 - SLICE_X55Y186 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.313 13.198 r hash_generate[2].hash/final/memory_reg_0_i_281/CO[3] - net (fo=1, routed) 0.000 13.198 hash_generate[2].hash/final/memory_reg_0_i_281_n_0 - SLICE_X55Y187 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 13.256 r hash_generate[2].hash/final/memory_reg_0_i_286/CO[3] - net (fo=1, routed) 0.000 13.256 hash_generate[2].hash/final/memory_reg_0_i_286_n_0 - SLICE_X55Y188 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 13.469 r hash_generate[2].hash/final/memory_reg_0_i_256/O[1] - net (fo=5, routed) 0.695 14.164 hash_generate[2].hash/final/minusOp10_out_0[9] - SLICE_X52Y190 LUT3 (Prop_lut3_I1_O) 0.152 14.316 r hash_generate[2].hash/final/memory_reg_0_i_127__1/O - net (fo=1, routed) 0.000 14.316 hash_generate[2].hash/final/memory_reg_0_i_127__1_n_0 - SLICE_X52Y190 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 14.640 r hash_generate[2].hash/final/memory_reg_0_i_96/CO[3] - net (fo=1, routed) 0.000 14.640 hash_generate[2].hash/final/memory_reg_0_i_96_n_0 - SLICE_X52Y191 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 14.698 r hash_generate[2].hash/final/memory_reg_0_i_110/CO[3] - net (fo=1, routed) 0.000 14.698 hash_generate[2].hash/final/memory_reg_0_i_110_n_0 - SLICE_X52Y192 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 14.911 r hash_generate[2].hash/final/memory_reg_0_i_102/O[1] - net (fo=5, routed) 0.643 15.554 hash_generate[2].hash/final/minusOp8_out[17] - SLICE_X49Y189 LUT3 (Prop_lut3_I2_O) 0.152 15.706 r hash_generate[2].hash/final/memory_reg_0_i_93__1/O - net (fo=1, routed) 0.000 15.706 hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0 - SLICE_X49Y189 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 16.030 r hash_generate[2].hash/final/memory_reg_0_i_33/CO[3] - net (fo=1, routed) 0.000 16.030 hash_generate[2].hash/final/memory_reg_0_i_33_n_0 - SLICE_X49Y190 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 16.088 r hash_generate[2].hash/final/memory_reg_0_i_30/CO[3] - net (fo=1, routed) 0.000 16.088 hash_generate[2].hash/final/memory_reg_0_i_30_n_0 - SLICE_X49Y191 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 16.146 r hash_generate[2].hash/final/memory_reg_0_i_27/CO[3] - net (fo=1, routed) 0.000 16.146 hash_generate[2].hash/final/memory_reg_0_i_27_n_0 - SLICE_X49Y192 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 16.204 r hash_generate[2].hash/final/memory_reg_0_i_283/CO[3] - net (fo=1, routed) 0.000 16.204 hash_generate[2].hash/final/memory_reg_0_i_283_n_0 - SLICE_X49Y193 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 16.262 r hash_generate[2].hash/final/memory_reg_0_i_282/CO[3] - net (fo=1, routed) 0.000 16.262 hash_generate[2].hash/final/memory_reg_0_i_282_n_0 - SLICE_X49Y194 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 16.320 r hash_generate[2].hash/final/memory_reg_0_i_264/CO[3] - net (fo=1, routed) 0.000 16.320 hash_generate[2].hash/final/memory_reg_0_i_264_n_0 - SLICE_X49Y195 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 16.378 r hash_generate[2].hash/final/memory_reg_0_i_262/CO[3] - net (fo=1, routed) 0.000 16.378 hash_generate[2].hash/final/memory_reg_0_i_262_n_0 - SLICE_X49Y196 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 16.591 r hash_generate[2].hash/final/memory_reg_0_i_260/O[1] - net (fo=3, routed) 0.582 17.172 hash_generate[2].hash/final/memory_reg_0_i_350__1[5] - SLICE_X51Y192 LUT3 (Prop_lut3_I2_O) 0.152 17.324 r hash_generate[2].hash/final/memory_reg_0_i_190__1/O - net (fo=1, routed) 0.000 17.324 hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0 - SLICE_X51Y192 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 17.648 r hash_generate[2].hash/final/memory_reg_0_i_104/CO[3] - net (fo=1, routed) 0.000 17.648 hash_generate[2].hash/final/memory_reg_0_i_104_n_0 - SLICE_X51Y193 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.706 r hash_generate[2].hash/final/memory_reg_0_i_103/CO[3] - net (fo=1, routed) 0.000 17.706 hash_generate[2].hash/final/memory_reg_0_i_103_n_0 - SLICE_X51Y194 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.764 r hash_generate[2].hash/final/memory_reg_0_i_95/CO[3] - net (fo=1, routed) 0.000 17.764 hash_generate[2].hash/final/memory_reg_0_i_95_n_0 - SLICE_X51Y195 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.822 r hash_generate[2].hash/final/memory_reg_0_i_109/CO[3] - net (fo=1, routed) 0.000 17.822 hash_generate[2].hash/final/memory_reg_0_i_109_n_0 - SLICE_X51Y196 CARRY4 (Prop_carry4_CI_CO[3]) - 0.058 17.880 r hash_generate[2].hash/final/memory_reg_0_i_101/CO[3] - net (fo=1, routed) 0.000 17.880 hash_generate[2].hash/final/memory_reg_0_i_101_n_0 - SLICE_X51Y197 CARRY4 (Prop_carry4_CI_O[1]) - 0.213 18.093 r hash_generate[2].hash/final/memory_reg_0_i_106/O[1] - net (fo=1, routed) 0.426 18.519 hash_generate[2].hash/final/memory_reg_0_i_106_n_6 - SLICE_X50Y194 LUT3 (Prop_lut3_I2_O) 0.152 18.671 r hash_generate[2].hash/final/memory_reg_0_i_83__1/O - net (fo=1, routed) 0.000 18.671 hash_generate[2].hash/final/memory_reg_0_i_83__1_n_0 - SLICE_X50Y194 CARRY4 (Prop_carry4_S[3]_CO[3]) - 0.216 18.887 r hash_generate[2].hash/final/memory_reg_0_i_32/CO[3] - net (fo=1, routed) 0.000 18.887 hash_generate[2].hash/final/memory_reg_0_i_32_n_0 - SLICE_X50Y195 CARRY4 (Prop_carry4_CI_O[1]) - 0.212 19.099 r hash_generate[2].hash/final/memory_reg_0_i_29/O[1] - net (fo=2, routed) 0.655 19.754 hash_generate[2].hash/final/memory_reg_0_i_29_n_6 - SLICE_X49Y198 LUT3 (Prop_lut3_I1_O) 0.155 19.909 r hash_generate[2].hash/final/memory_reg_0_i_16__1/O - net (fo=1, routed) 0.000 19.909 hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0 - SLICE_X49Y198 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.324 20.233 r hash_generate[2].hash/final/memory_reg_0_i_3/CO[3] - net (fo=1, routed) 0.000 20.233 hash_generate[2].hash/final/memory_reg_0_i_3_n_0 - SLICE_X49Y199 CARRY4 (Prop_carry4_CI_O[2]) - 0.136 20.369 r hash_generate[2].hash/final/memory_reg_0_i_2/O[2] - net (fo=9, routed) 0.954 21.323 storage_generate[2].storage/O76[10] - RAMB36_X2Y42 RAMB36E1 r storage_generate[2].storage/memory_reg_6/ADDRBWRADDR[14] + RAMB36_X3Y12 RAMB36E1 (Prop_ramb36e1_CLKBWRCLK_DOBDO[9]) + 2.080 2.752 r storage_generate[1].storage/memory_reg_2/DOBDO[9] + net (fo=1, routed) 1.081 3.833 storage_generate[1].storage/memory_rule[1][45] + SLICE_X61Y79 LUT6 (Prop_lut6_I5_O) 0.053 3.886 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122/O + net (fo=1, routed) 0.000 3.886 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122_n_0 + SLICE_X61Y79 CARRY4 (Prop_carry4_S[1]_CO[3]) + 0.324 4.210 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_104/CO[3] + net (fo=1, routed) 0.000 4.210 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_104_n_0 + SLICE_X61Y80 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.268 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_89/CO[3] + net (fo=1, routed) 0.000 4.268 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_89_n_0 + SLICE_X61Y81 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.326 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_74/CO[3] + net (fo=1, routed) 0.000 4.326 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_74_n_0 + SLICE_X61Y82 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.384 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_59/CO[3] + net (fo=1, routed) 0.000 4.384 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_59_n_0 + SLICE_X61Y83 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.442 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_44/CO[3] + net (fo=1, routed) 0.000 4.442 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_44_n_0 + SLICE_X61Y84 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.500 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_29/CO[3] + net (fo=1, routed) 0.000 4.500 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_29_n_0 + SLICE_X61Y85 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.558 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_15/CO[3] + net (fo=1, routed) 0.000 4.558 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_15_n_0 + SLICE_X61Y86 CARRY4 (Prop_carry4_CI_CO[3]) + 0.058 4.616 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_6/CO[3] + net (fo=1, routed) 0.000 4.616 storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_6_n_0 + SLICE_X61Y87 CARRY4 (Prop_carry4_CI_CO[2]) + 0.132 4.748 r storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_2/CO[2] + net (fo=17, routed) 0.407 5.155 storage_generate[1].storage/out_key_found13_out + SLICE_X59Y86 LUT6 (Prop_lut6_I3_O) 0.161 5.316 r storage_generate[1].storage/registered_output.OUTPUT_DATA[0]_i_2/O + net (fo=1, routed) 0.250 5.567 storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[0]_0 + SLICE_X56Y87 LUT6 (Prop_lut6_I5_O) 0.053 5.620 r storage_generate[2].storage/registered_output.OUTPUT_DATA[0]_i_1/O + net (fo=1, routed) 0.000 5.620 out_data[0] + SLICE_X56Y87 FDRE r registered_output.OUTPUT_DATA_reg[0]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 4.000 4.000 r 0.000 4.000 r CLK (IN) - net (fo=668, unset) 0.638 4.638 storage_generate[2].storage/CLK - RAMB36_X2Y42 RAMB36E1 r storage_generate[2].storage/memory_reg_6/CLKBWRCLK + net (fo=5071, unset) 0.638 4.638 CLK + SLICE_X56Y87 FDRE r registered_output.OUTPUT_DATA_reg[0]/C clock pessimism 0.000 4.638 clock uncertainty -0.035 4.603 - RAMB36_X2Y42 RAMB36E1 (Setup_ramb36e1_CLKBWRCLK_ADDRBWRADDR[14]) - -0.578 4.025 storage_generate[2].storage/memory_reg_6 + SLICE_X56Y87 FDRE (Setup_fdre_C_D) 0.035 4.638 registered_output.OUTPUT_DATA_reg[0] ------------------------------------------------------------------- - required time 4.025 - arrival time -21.323 + required time 4.638 + arrival time -5.620 ------------------------------------------------------------------- - slack -17.298 + slack -0.982 @@ -2192,15 +1013,15 @@ Slack (VIOLATED) : -17.298ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.081ns (arrival time - required time) - Source: registered_config.cfg_record_reg[2]/C +Slack (MET) : 0.038ns (arrival time - required time) + Source: registered_input.in_valid_reg/C (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[3].storage/memory_reg_0/DIADI[2] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[0].hash/final/s_reg[7][valid]_srl13/D + (rising edge-triggered cell SRL16E clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.251ns (logic 0.100ns (39.889%) route 0.151ns (60.111%)) + Data Path Delay: 0.155ns (logic 0.100ns (64.432%) route 0.055ns (35.568%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2211,36 +1032,36 @@ Slack (MET) : 0.081ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.283 0.283 CLK - SLICE_X26Y200 FDRE r registered_config.cfg_record_reg[2]/C + net (fo=5071, unset) 0.283 0.283 CLK + SLICE_X59Y125 FDRE r registered_input.in_valid_reg/C ------------------------------------------------------------------- ------------------- - SLICE_X26Y200 FDRE (Prop_fdre_C_Q) 0.100 0.383 r registered_config.cfg_record_reg[2]/Q - net (fo=4, routed) 0.151 0.534 storage_generate[3].storage/memory_reg_8_1[2] - RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/DIADI[2] + SLICE_X59Y125 FDRE (Prop_fdre_C_Q) 0.100 0.383 r registered_input.in_valid_reg/Q + net (fo=1, routed) 0.055 0.438 hash_generate[0].hash/final/in_valid + SLICE_X58Y125 SRL16E r hash_generate[0].hash/final/s_reg[7][valid]_srl13/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK - RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/CLKARDCLK + net (fo=5071, unset) 0.298 0.298 hash_generate[0].hash/final/CLK + SLICE_X58Y125 SRL16E r hash_generate[0].hash/final/s_reg[7][valid]_srl13/CLK clock pessimism 0.000 0.298 - RAMB36_X1Y40 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[2]) - 0.155 0.453 storage_generate[3].storage/memory_reg_0 + SLICE_X58Y125 SRL16E (Hold_srl16e_CLK_D) + 0.102 0.400 hash_generate[0].hash/final/s_reg[7][valid]_srl13 ------------------------------------------------------------------- - required time -0.453 - arrival time 0.534 + required time -0.400 + arrival time 0.438 ------------------------------------------------------------------- - slack 0.081 + slack 0.038 -Slack (MET) : 0.092ns (arrival time - required time) - Source: registered_config.cfg_record_reg[3]/C +Slack (MET) : 0.038ns (arrival time - required time) + Source: registered_input.in_key_reg[100]__0/C (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[3].storage/memory_reg_0/DIADI[3] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][100]_srl5/D + (rising edge-triggered cell SRL16E clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.262ns (logic 0.100ns (38.194%) route 0.162ns (61.806%)) + Data Path Delay: 0.155ns (logic 0.100ns (64.432%) route 0.055ns (35.568%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2251,36 +1072,36 @@ Slack (MET) : 0.092ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.283 0.283 CLK - SLICE_X24Y202 FDRE r registered_config.cfg_record_reg[3]/C + net (fo=5071, unset) 0.283 0.283 CLK + SLICE_X41Y87 FDRE r registered_input.in_key_reg[100]__0/C ------------------------------------------------------------------- ------------------- - SLICE_X24Y202 FDRE (Prop_fdre_C_Q) 0.100 0.383 r registered_config.cfg_record_reg[3]/Q - net (fo=4, routed) 0.162 0.545 storage_generate[3].storage/memory_reg_8_1[3] - RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/DIADI[3] + SLICE_X41Y87 FDRE (Prop_fdre_C_Q) 0.100 0.383 r registered_input.in_key_reg[100]__0/Q + net (fo=1, routed) 0.055 0.438 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[6][key][100]__0_0 + SLICE_X40Y87 SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][100]_srl5/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK - RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/CLKARDCLK + net (fo=5071, unset) 0.298 0.298 hash_generate[0].hash/mix_pipeline[0].mix/CLK + SLICE_X40Y87 SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][100]_srl5/CLK clock pessimism 0.000 0.298 - RAMB36_X1Y40 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[3]) - 0.155 0.453 storage_generate[3].storage/memory_reg_0 + SLICE_X40Y87 SRL16E (Hold_srl16e_CLK_D) + 0.102 0.400 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][100]_srl5 ------------------------------------------------------------------- - required time -0.453 - arrival time 0.545 + required time -0.400 + arrival time 0.438 ------------------------------------------------------------------- - slack 0.092 + slack 0.038 -Slack (MET) : 0.119ns (arrival time - required time) - Source: registered_config.cfg_record_reg[26]/C +Slack (MET) : 0.057ns (arrival time - required time) + Source: registered_input.in_key_reg[111]__0/C (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[3].storage/memory_reg_1/DIADI[8] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][111]_srl5/D + (rising edge-triggered cell SRL16E clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.289ns (logic 0.118ns (40.800%) route 0.171ns (59.200%)) + Data Path Delay: 0.190ns (logic 0.091ns (47.978%) route 0.099ns (52.022%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2291,36 +1112,36 @@ Slack (MET) : 0.119ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.283 0.283 CLK - SLICE_X10Y196 FDRE r registered_config.cfg_record_reg[26]/C + net (fo=5071, unset) 0.283 0.283 CLK + SLICE_X39Y90 FDRE r registered_input.in_key_reg[111]__0/C ------------------------------------------------------------------- ------------------- - SLICE_X10Y196 FDRE (Prop_fdre_C_Q) 0.118 0.401 r registered_config.cfg_record_reg[26]/Q - net (fo=4, routed) 0.171 0.572 storage_generate[3].storage/memory_reg_8_1[26] - RAMB36_X0Y39 RAMB36E1 r storage_generate[3].storage/memory_reg_1/DIADI[8] + SLICE_X39Y90 FDRE (Prop_fdre_C_Q) 0.091 0.374 r registered_input.in_key_reg[111]__0/Q + net (fo=1, routed) 0.099 0.473 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[6][key][111]__0_0 + SLICE_X38Y90 SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][111]_srl5/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK - RAMB36_X0Y39 RAMB36E1 r storage_generate[3].storage/memory_reg_1/CLKARDCLK + net (fo=5071, unset) 0.298 0.298 hash_generate[0].hash/mix_pipeline[0].mix/CLK + SLICE_X38Y90 SRL16E r hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][111]_srl5/CLK clock pessimism 0.000 0.298 - RAMB36_X0Y39 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[8]) - 0.155 0.453 storage_generate[3].storage/memory_reg_1 + SLICE_X38Y90 SRL16E (Hold_srl16e_CLK_D) + 0.118 0.416 hash_generate[0].hash/mix_pipeline[0].mix/s_reg[5][key][111]_srl5 ------------------------------------------------------------------- - required time -0.453 - arrival time 0.572 + required time -0.416 + arrival time 0.473 ------------------------------------------------------------------- - slack 0.119 + slack 0.057 -Slack (MET) : 0.121ns (arrival time - required time) - Source: registered_config.cfg_record_reg[30]/C +Slack (MET) : 0.091ns (arrival time - required time) + Source: hash_generate[1].hash/final/s_reg[1][b][29]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[1].hash/final/s_reg[2][b][29]/D (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[3].storage/memory_reg_1/DIADI[12] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.291ns (logic 0.118ns (40.578%) route 0.173ns (59.422%)) + Data Path Delay: 0.155ns (logic 0.100ns (64.432%) route 0.055ns (35.568%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2331,36 +1152,35 @@ Slack (MET) : 0.121ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.283 0.283 CLK - SLICE_X10Y196 FDRE r registered_config.cfg_record_reg[30]/C + net (fo=5071, unset) 0.283 0.283 hash_generate[1].hash/final/CLK + SLICE_X5Y109 FDRE r hash_generate[1].hash/final/s_reg[1][b][29]/C ------------------------------------------------------------------- ------------------- - SLICE_X10Y196 FDRE (Prop_fdre_C_Q) 0.118 0.401 r registered_config.cfg_record_reg[30]/Q - net (fo=4, routed) 0.173 0.574 storage_generate[3].storage/memory_reg_8_1[30] - RAMB36_X0Y39 RAMB36E1 r storage_generate[3].storage/memory_reg_1/DIADI[12] + SLICE_X5Y109 FDRE (Prop_fdre_C_Q) 0.100 0.383 r hash_generate[1].hash/final/s_reg[1][b][29]/Q + net (fo=1, routed) 0.055 0.438 hash_generate[1].hash/final/s_reg[1][b][29] + SLICE_X5Y109 FDRE r hash_generate[1].hash/final/s_reg[2][b][29]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK - RAMB36_X0Y39 RAMB36E1 r storage_generate[3].storage/memory_reg_1/CLKARDCLK + net (fo=5071, unset) 0.298 0.298 hash_generate[1].hash/final/CLK + SLICE_X5Y109 FDRE r hash_generate[1].hash/final/s_reg[2][b][29]/C clock pessimism 0.000 0.298 - RAMB36_X0Y39 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[12]) - 0.155 0.453 storage_generate[3].storage/memory_reg_1 + SLICE_X5Y109 FDRE (Hold_fdre_C_D) 0.049 0.347 hash_generate[1].hash/final/s_reg[2][b][29] ------------------------------------------------------------------- - required time -0.453 - arrival time 0.574 + required time -0.347 + arrival time 0.438 ------------------------------------------------------------------- - slack 0.121 + slack 0.091 -Slack (MET) : 0.122ns (arrival time - required time) - Source: registered_config.cfg_record_reg[5]/C +Slack (MET) : 0.091ns (arrival time - required time) + Source: hash_generate[3].hash/final/s_reg[3][a][3]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[3].hash/final/s_reg[4][a][3]/D (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[3].storage/memory_reg_0/DIADI[5] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.292ns (logic 0.100ns (34.221%) route 0.192ns (65.779%)) + Data Path Delay: 0.155ns (logic 0.100ns (64.432%) route 0.055ns (35.568%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2371,36 +1191,76 @@ Slack (MET) : 0.122ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.283 0.283 CLK - SLICE_X24Y202 FDRE r registered_config.cfg_record_reg[5]/C + net (fo=5071, unset) 0.283 0.283 hash_generate[3].hash/final/CLK + SLICE_X1Y75 FDRE r hash_generate[3].hash/final/s_reg[3][a][3]/C ------------------------------------------------------------------- ------------------- - SLICE_X24Y202 FDRE (Prop_fdre_C_Q) 0.100 0.383 r registered_config.cfg_record_reg[5]/Q - net (fo=4, routed) 0.192 0.575 storage_generate[3].storage/memory_reg_8_1[5] - RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/DIADI[5] + SLICE_X1Y75 FDRE (Prop_fdre_C_Q) 0.100 0.383 r hash_generate[3].hash/final/s_reg[3][a][3]/Q + net (fo=1, routed) 0.055 0.438 hash_generate[3].hash/final/s_reg[3][a][3] + SLICE_X1Y75 FDRE r hash_generate[3].hash/final/s_reg[4][a][3]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK - RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/CLKARDCLK + net (fo=5071, unset) 0.298 0.298 hash_generate[3].hash/final/CLK + SLICE_X1Y75 FDRE r hash_generate[3].hash/final/s_reg[4][a][3]/C clock pessimism 0.000 0.298 - RAMB36_X1Y40 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[5]) - 0.155 0.453 storage_generate[3].storage/memory_reg_0 + SLICE_X1Y75 FDRE (Hold_fdre_C_D) 0.049 0.347 hash_generate[3].hash/final/s_reg[4][a][3] ------------------------------------------------------------------- - required time -0.453 - arrival time 0.575 + required time -0.347 + arrival time 0.438 ------------------------------------------------------------------- - slack 0.122 + slack 0.091 -Slack (MET) : 0.124ns (arrival time - required time) - Source: registered_config.cfg_record_reg[101]/C +Slack (MET) : 0.093ns (arrival time - required time) + Source: hash_generate[3].hash/mix_pipeline[0].mix/s_reg[4][a][31]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[3].hash/mix_pipeline[0].mix/s_reg[5][b][18]/D (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[3].storage/memory_reg_5/DIADI[11] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.294ns (logic 0.100ns (34.020%) route 0.194ns (65.980%)) + Data Path Delay: 0.194ns (logic 0.128ns (65.840%) route 0.066ns (34.160%)) + Logic Levels: 1 (LUT2=1) + Clock Path Skew: 0.015ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 0.298ns + Source Clock Delay (SCD): 0.283ns + Clock Pessimism Removal (CPR): -0.000ns + + Location Delay type Incr(ns) Path(ns) Netlist Resource(s) + ------------------------------------------------------------------- ------------------- + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=5071, unset) 0.283 0.283 hash_generate[3].hash/mix_pipeline[0].mix/CLK + SLICE_X9Y88 FDRE r hash_generate[3].hash/mix_pipeline[0].mix/s_reg[4][a][31]/C + ------------------------------------------------------------------- ------------------- + SLICE_X9Y88 FDRE (Prop_fdre_C_Q) 0.100 0.383 r hash_generate[3].hash/mix_pipeline[0].mix/s_reg[4][a][31]/Q + net (fo=3, routed) 0.066 0.450 hash_generate[3].hash/mix_pipeline[0].mix/rot0_in[13] + SLICE_X8Y88 LUT2 (Prop_lut2_I0_O) 0.028 0.478 r hash_generate[3].hash/mix_pipeline[0].mix/s[5][b][18]_i_1__2/O + net (fo=1, routed) 0.000 0.478 hash_generate[3].hash/mix_pipeline[0].mix/s_reg[5][b]0[18] + SLICE_X8Y88 FDRE r hash_generate[3].hash/mix_pipeline[0].mix/s_reg[5][b][18]/D + ------------------------------------------------------------------- ------------------- + + (clock CLK rise edge) 0.000 0.000 r + 0.000 0.000 r CLK (IN) + net (fo=5071, unset) 0.298 0.298 hash_generate[3].hash/mix_pipeline[0].mix/CLK + SLICE_X8Y88 FDRE r hash_generate[3].hash/mix_pipeline[0].mix/s_reg[5][b][18]/C + clock pessimism 0.000 0.298 + SLICE_X8Y88 FDRE (Hold_fdre_C_D) 0.087 0.385 hash_generate[3].hash/mix_pipeline[0].mix/s_reg[5][b][18] + ------------------------------------------------------------------- + required time -0.385 + arrival time 0.478 + ------------------------------------------------------------------- + slack 0.093 + +Slack (MET) : 0.093ns (arrival time - required time) + Source: hash_generate[0].hash/final/s_reg[1][b][30]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[0].hash/final/s_reg[2][b][30]/D + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Path Group: CLK + Path Type: Hold (Min at Fast Process Corner) + Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) + Data Path Delay: 0.155ns (logic 0.100ns (64.432%) route 0.055ns (35.568%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2411,36 +1271,35 @@ Slack (MET) : 0.124ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.283 0.283 CLK - SLICE_X25Y208 FDRE r registered_config.cfg_record_reg[101]/C + net (fo=5071, unset) 0.283 0.283 hash_generate[0].hash/final/CLK + SLICE_X17Y111 FDRE r hash_generate[0].hash/final/s_reg[1][b][30]/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y208 FDRE (Prop_fdre_C_Q) 0.100 0.383 r registered_config.cfg_record_reg[101]/Q - net (fo=4, routed) 0.194 0.577 storage_generate[3].storage/memory_reg_8_1[101] - RAMB36_X1Y41 RAMB36E1 r storage_generate[3].storage/memory_reg_5/DIADI[11] + SLICE_X17Y111 FDRE (Prop_fdre_C_Q) 0.100 0.383 r hash_generate[0].hash/final/s_reg[1][b][30]/Q + net (fo=1, routed) 0.055 0.438 hash_generate[0].hash/final/s_reg[1][b][30] + SLICE_X17Y111 FDRE r hash_generate[0].hash/final/s_reg[2][b][30]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK - RAMB36_X1Y41 RAMB36E1 r storage_generate[3].storage/memory_reg_5/CLKARDCLK + net (fo=5071, unset) 0.298 0.298 hash_generate[0].hash/final/CLK + SLICE_X17Y111 FDRE r hash_generate[0].hash/final/s_reg[2][b][30]/C clock pessimism 0.000 0.298 - RAMB36_X1Y41 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[11]) - 0.155 0.453 storage_generate[3].storage/memory_reg_5 + SLICE_X17Y111 FDRE (Hold_fdre_C_D) 0.047 0.345 hash_generate[0].hash/final/s_reg[2][b][30] ------------------------------------------------------------------- - required time -0.453 - arrival time 0.577 + required time -0.345 + arrival time 0.438 ------------------------------------------------------------------- - slack 0.124 + slack 0.093 -Slack (MET) : 0.125ns (arrival time - required time) - Source: registered_config.cfg_record_reg[103]/C +Slack (MET) : 0.093ns (arrival time - required time) + Source: hash_generate[1].hash/final/s_reg[1][b][10]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[1].hash/final/s_reg[2][b][10]/D (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[3].storage/memory_reg_5/DIADI[13] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.295ns (logic 0.100ns (33.917%) route 0.195ns (66.083%)) + Data Path Delay: 0.155ns (logic 0.100ns (64.432%) route 0.055ns (35.568%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2451,36 +1310,35 @@ Slack (MET) : 0.125ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.283 0.283 CLK - SLICE_X25Y208 FDRE r registered_config.cfg_record_reg[103]/C + net (fo=5071, unset) 0.283 0.283 hash_generate[1].hash/final/CLK + SLICE_X5Y105 FDRE r hash_generate[1].hash/final/s_reg[1][b][10]/C ------------------------------------------------------------------- ------------------- - SLICE_X25Y208 FDRE (Prop_fdre_C_Q) 0.100 0.383 r registered_config.cfg_record_reg[103]/Q - net (fo=4, routed) 0.195 0.578 storage_generate[3].storage/memory_reg_8_1[103] - RAMB36_X1Y41 RAMB36E1 r storage_generate[3].storage/memory_reg_5/DIADI[13] + SLICE_X5Y105 FDRE (Prop_fdre_C_Q) 0.100 0.383 r hash_generate[1].hash/final/s_reg[1][b][10]/Q + net (fo=1, routed) 0.055 0.438 hash_generate[1].hash/final/s_reg[1][b][10] + SLICE_X5Y105 FDRE r hash_generate[1].hash/final/s_reg[2][b][10]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK - RAMB36_X1Y41 RAMB36E1 r storage_generate[3].storage/memory_reg_5/CLKARDCLK + net (fo=5071, unset) 0.298 0.298 hash_generate[1].hash/final/CLK + SLICE_X5Y105 FDRE r hash_generate[1].hash/final/s_reg[2][b][10]/C clock pessimism 0.000 0.298 - RAMB36_X1Y41 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[13]) - 0.155 0.453 storage_generate[3].storage/memory_reg_5 + SLICE_X5Y105 FDRE (Hold_fdre_C_D) 0.047 0.345 hash_generate[1].hash/final/s_reg[2][b][10] ------------------------------------------------------------------- - required time -0.453 - arrival time 0.578 + required time -0.345 + arrival time 0.438 ------------------------------------------------------------------- - slack 0.125 + slack 0.093 -Slack (MET) : 0.132ns (arrival time - required time) - Source: registered_config.cfg_record_reg[93]/C +Slack (MET) : 0.093ns (arrival time - required time) + Source: hash_generate[1].hash/final/s_reg[1][b][20]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[1].hash/final/s_reg[2][b][20]/D (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[3].storage/memory_reg_5/DIADI[3] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.302ns (logic 0.100ns (33.081%) route 0.202ns (66.919%)) + Data Path Delay: 0.155ns (logic 0.100ns (64.432%) route 0.055ns (35.568%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2491,36 +1349,35 @@ Slack (MET) : 0.132ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.283 0.283 CLK - SLICE_X24Y205 FDRE r registered_config.cfg_record_reg[93]/C + net (fo=5071, unset) 0.283 0.283 hash_generate[1].hash/final/CLK + SLICE_X5Y109 FDRE r hash_generate[1].hash/final/s_reg[1][b][20]/C ------------------------------------------------------------------- ------------------- - SLICE_X24Y205 FDRE (Prop_fdre_C_Q) 0.100 0.383 r registered_config.cfg_record_reg[93]/Q - net (fo=4, routed) 0.202 0.586 storage_generate[3].storage/memory_reg_8_1[93] - RAMB36_X1Y41 RAMB36E1 r storage_generate[3].storage/memory_reg_5/DIADI[3] + SLICE_X5Y109 FDRE (Prop_fdre_C_Q) 0.100 0.383 r hash_generate[1].hash/final/s_reg[1][b][20]/Q + net (fo=1, routed) 0.055 0.438 hash_generate[1].hash/final/s_reg[1][b][20] + SLICE_X5Y109 FDRE r hash_generate[1].hash/final/s_reg[2][b][20]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK - RAMB36_X1Y41 RAMB36E1 r storage_generate[3].storage/memory_reg_5/CLKARDCLK + net (fo=5071, unset) 0.298 0.298 hash_generate[1].hash/final/CLK + SLICE_X5Y109 FDRE r hash_generate[1].hash/final/s_reg[2][b][20]/C clock pessimism 0.000 0.298 - RAMB36_X1Y41 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[3]) - 0.155 0.453 storage_generate[3].storage/memory_reg_5 + SLICE_X5Y109 FDRE (Hold_fdre_C_D) 0.047 0.345 hash_generate[1].hash/final/s_reg[2][b][20] ------------------------------------------------------------------- - required time -0.453 - arrival time 0.586 + required time -0.345 + arrival time 0.438 ------------------------------------------------------------------- - slack 0.132 + slack 0.093 -Slack (MET) : 0.138ns (arrival time - required time) - Source: registered_config.cfg_record_reg[14]/C +Slack (MET) : 0.093ns (arrival time - required time) + Source: hash_generate[1].hash/final/s_reg[1][b][27]/C + (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) + Destination: hash_generate[1].hash/final/s_reg[2][b][27]/D (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[3].storage/memory_reg_0/DIADI[14] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) Path Group: CLK Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.307ns (logic 0.100ns (32.526%) route 0.207ns (67.474%)) + Data Path Delay: 0.155ns (logic 0.100ns (64.432%) route 0.055ns (35.568%)) Logic Levels: 0 Clock Path Skew: 0.015ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 0.298ns @@ -2531,66 +1388,25 @@ Slack (MET) : 0.138ns (arrival time - required time) ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.283 0.283 CLK - SLICE_X29Y202 FDRE r registered_config.cfg_record_reg[14]/C + net (fo=5071, unset) 0.283 0.283 hash_generate[1].hash/final/CLK + SLICE_X5Y109 FDRE r hash_generate[1].hash/final/s_reg[1][b][27]/C ------------------------------------------------------------------- ------------------- - SLICE_X29Y202 FDRE (Prop_fdre_C_Q) 0.100 0.383 r registered_config.cfg_record_reg[14]/Q - net (fo=4, routed) 0.207 0.591 storage_generate[3].storage/memory_reg_8_1[14] - RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/DIADI[14] + SLICE_X5Y109 FDRE (Prop_fdre_C_Q) 0.100 0.383 r hash_generate[1].hash/final/s_reg[1][b][27]/Q + net (fo=1, routed) 0.055 0.438 hash_generate[1].hash/final/s_reg[1][b][27] + SLICE_X5Y109 FDRE r hash_generate[1].hash/final/s_reg[2][b][27]/D ------------------------------------------------------------------- ------------------- (clock CLK rise edge) 0.000 0.000 r 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK - RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/CLKARDCLK + net (fo=5071, unset) 0.298 0.298 hash_generate[1].hash/final/CLK + SLICE_X5Y109 FDRE r hash_generate[1].hash/final/s_reg[2][b][27]/C clock pessimism 0.000 0.298 - RAMB36_X1Y40 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[14]) - 0.155 0.453 storage_generate[3].storage/memory_reg_0 + SLICE_X5Y109 FDRE (Hold_fdre_C_D) 0.047 0.345 hash_generate[1].hash/final/s_reg[2][b][27] ------------------------------------------------------------------- - required time -0.453 - arrival time 0.591 + required time -0.345 + arrival time 0.438 ------------------------------------------------------------------- - slack 0.138 - -Slack (MET) : 0.140ns (arrival time - required time) - Source: registered_config.cfg_record_reg[9]/C - (rising edge-triggered cell FDRE clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Destination: storage_generate[3].storage/memory_reg_0/DIADI[9] - (rising edge-triggered cell RAMB36E1 clocked by CLK {rise@0.000ns fall@2.000ns period=4.000ns}) - Path Group: CLK - Path Type: Hold (Min at Fast Process Corner) - Requirement: 0.000ns (CLK rise@0.000ns - CLK rise@0.000ns) - Data Path Delay: 0.309ns (logic 0.100ns (32.319%) route 0.209ns (67.681%)) - Logic Levels: 0 - Clock Path Skew: 0.015ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 0.298ns - Source Clock Delay (SCD): 0.283ns - Clock Pessimism Removal (CPR): -0.000ns - - Location Delay type Incr(ns) Path(ns) Netlist Resource(s) - ------------------------------------------------------------------- ------------------- - (clock CLK rise edge) 0.000 0.000 r - 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.283 0.283 CLK - SLICE_X28Y202 FDRE r registered_config.cfg_record_reg[9]/C - ------------------------------------------------------------------- ------------------- - SLICE_X28Y202 FDRE (Prop_fdre_C_Q) 0.100 0.383 r registered_config.cfg_record_reg[9]/Q - net (fo=4, routed) 0.209 0.593 storage_generate[3].storage/memory_reg_8_1[9] - RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/DIADI[9] - ------------------------------------------------------------------- ------------------- - - (clock CLK rise edge) 0.000 0.000 r - 0.000 0.000 r CLK (IN) - net (fo=668, unset) 0.298 0.298 storage_generate[3].storage/CLK - RAMB36_X1Y40 RAMB36E1 r storage_generate[3].storage/memory_reg_0/CLKARDCLK - clock pessimism 0.000 0.298 - RAMB36_X1Y40 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[9]) - 0.155 0.453 storage_generate[3].storage/memory_reg_0 - ------------------------------------------------------------------- - required time -0.453 - arrival time 0.593 - ------------------------------------------------------------------- - slack 0.140 + slack 0.093 @@ -2603,37 +1419,37 @@ Waveform(ns): { 0.000 2.000 } Period(ns): 4.000 Sources: { CLK } -Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X1Y35 storage_generate[0].storage/memory_reg_0/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X0Y34 storage_generate[0].storage/memory_reg_1/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X0Y32 storage_generate[0].storage/memory_reg_2/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X0Y36 storage_generate[0].storage/memory_reg_3/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X0Y38 storage_generate[0].storage/memory_reg_4/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X0Y33 storage_generate[0].storage/memory_reg_5/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X0Y37 storage_generate[0].storage/memory_reg_6/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X1Y36 storage_generate[0].storage/memory_reg_7/CLKARDCLK -Min Period n/a RAMB18E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB18_X0Y70 storage_generate[0].storage/memory_reg_8/CLKARDCLK -Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X2Y33 storage_generate[1].storage/memory_reg_0/CLKARDCLK -Low Pulse Width Slow FDRE/C n/a 0.400 2.000 1.600 SLICE_X17Y189 memory_key_reg[118]/C -Low Pulse Width Fast FDRE/C n/a 0.400 2.000 1.600 SLICE_X17Y189 memory_key_reg[118]/C -Low Pulse Width Slow FDRE/C n/a 0.400 2.000 1.600 SLICE_X21Y208 registered_config.cfg_record_reg[125]/C -Low Pulse Width Fast FDRE/C n/a 0.400 2.000 1.600 SLICE_X21Y208 registered_config.cfg_record_reg[125]/C -Low Pulse Width Slow FDRE/C n/a 0.400 2.000 1.600 SLICE_X21Y208 registered_config.cfg_record_reg[131]/C -Low Pulse Width Fast FDRE/C n/a 0.400 2.000 1.600 SLICE_X21Y208 registered_config.cfg_record_reg[131]/C -Low Pulse Width Slow FDRE/C n/a 0.400 2.000 1.600 SLICE_X21Y208 registered_config.cfg_record_reg[133]/C -Low Pulse Width Fast FDRE/C n/a 0.400 2.000 1.600 SLICE_X21Y208 registered_config.cfg_record_reg[133]/C -Low Pulse Width Slow FDRE/C n/a 0.400 2.000 1.600 SLICE_X21Y208 registered_config.cfg_record_reg[47]/C -Low Pulse Width Fast FDRE/C n/a 0.400 2.000 1.600 SLICE_X21Y208 registered_config.cfg_record_reg[47]/C -High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 SLICE_X37Y182 memory_key_reg[0]/C -High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 SLICE_X37Y182 memory_key_reg[0]/C -High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 SLICE_X17Y186 memory_key_reg[100]/C -High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 SLICE_X17Y186 memory_key_reg[100]/C -High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 SLICE_X16Y186 memory_key_reg[101]/C -High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 SLICE_X16Y186 memory_key_reg[101]/C -High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 SLICE_X16Y189 memory_key_reg[102]/C -High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 SLICE_X16Y189 memory_key_reg[102]/C -High Pulse Width Slow FDRE/C n/a 0.350 2.000 1.650 SLICE_X17Y186 memory_key_reg[103]/C -High Pulse Width Fast FDRE/C n/a 0.350 2.000 1.650 SLICE_X17Y186 memory_key_reg[103]/C +Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X1Y13 storage_generate[0].storage/memory_reg_0/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X1Y16 storage_generate[0].storage/memory_reg_1/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X1Y15 storage_generate[0].storage/memory_reg_2/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X1Y17 storage_generate[0].storage/memory_reg_3/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X1Y18 storage_generate[0].storage/memory_reg_4/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X1Y14 storage_generate[0].storage/memory_reg_5/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X1Y20 storage_generate[0].storage/memory_reg_6/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X1Y19 storage_generate[0].storage/memory_reg_7/CLKARDCLK +Min Period n/a RAMB18E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB18_X1Y42 storage_generate[0].storage/memory_reg_8/CLKARDCLK +Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 4.000 1.505 RAMB36_X4Y14 storage_generate[1].storage/memory_reg_0/CLKARDCLK +Low Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X22Y78 hash_generate[0].hash/final/s_reg[7][key][0]_srl13/CLK +Low Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X22Y78 hash_generate[0].hash/final/s_reg[7][key][0]_srl13/CLK +Low Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X40Y86 hash_generate[0].hash/final/s_reg[7][key][100]_srl7/CLK +Low Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X40Y86 hash_generate[0].hash/final/s_reg[7][key][100]_srl7/CLK +Low Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X40Y86 hash_generate[0].hash/final/s_reg[7][key][101]_srl7/CLK +Low Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X40Y86 hash_generate[0].hash/final/s_reg[7][key][101]_srl7/CLK +Low Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X40Y86 hash_generate[0].hash/final/s_reg[7][key][102]_srl7/CLK +Low Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X40Y86 hash_generate[0].hash/final/s_reg[7][key][102]_srl7/CLK +Low Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X40Y86 hash_generate[0].hash/final/s_reg[7][key][103]_srl7/CLK +Low Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X40Y86 hash_generate[0].hash/final/s_reg[7][key][103]_srl7/CLK +High Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X22Y78 hash_generate[0].hash/final/s_reg[7][key][0]_srl13/CLK +High Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X22Y78 hash_generate[0].hash/final/s_reg[7][key][0]_srl13/CLK +High Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X40Y86 hash_generate[0].hash/final/s_reg[7][key][100]_srl7/CLK +High Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X40Y86 hash_generate[0].hash/final/s_reg[7][key][100]_srl7/CLK +High Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X40Y86 hash_generate[0].hash/final/s_reg[7][key][101]_srl7/CLK +High Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X40Y86 hash_generate[0].hash/final/s_reg[7][key][101]_srl7/CLK +High Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X40Y86 hash_generate[0].hash/final/s_reg[7][key][102]_srl7/CLK +High Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X40Y86 hash_generate[0].hash/final/s_reg[7][key][102]_srl7/CLK +High Pulse Width Slow SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X40Y86 hash_generate[0].hash/final/s_reg[7][key][103]_srl7/CLK +High Pulse Width Fast SRL16E/CLK n/a 0.780 2.000 1.220 SLICE_X40Y86 hash_generate[0].hash/final/s_reg[7][key][103]_srl7/CLK diff --git a/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.rpx b/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.rpx index 133a998..2b1b910 100644 Binary files a/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.rpx and b/synth/filter_vivado.runs/impl_1/filter_timing_summary_routed.rpx differ diff --git a/synth/filter_vivado.runs/impl_1/filter_utilization_placed.pb b/synth/filter_vivado.runs/impl_1/filter_utilization_placed.pb index d0831f5..2735fc4 100644 Binary files a/synth/filter_vivado.runs/impl_1/filter_utilization_placed.pb and b/synth/filter_vivado.runs/impl_1/filter_utilization_placed.pb differ diff --git a/synth/filter_vivado.runs/impl_1/filter_utilization_placed.rpt b/synth/filter_vivado.runs/impl_1/filter_utilization_placed.rpt index fdf26d2..e7b56a9 100644 --- a/synth/filter_vivado.runs/impl_1/filter_utilization_placed.rpt +++ b/synth/filter_vivado.runs/impl_1/filter_utilization_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 -| Date : Sun Dec 3 18:54:00 2023 +| Date : Sun Dec 3 21:18:40 2023 | Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux | Command : report_utilization -file filter_utilization_placed.rpt -pb filter_utilization_placed.pb | Design : filter @@ -29,18 +29,20 @@ Table of Contents 1. Slice Logic -------------- -+-------------------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+-------------------------+------+-------+------------+-----------+-------+ -| Slice LUTs | 3503 | 0 | 0 | 101400 | 3.45 | -| LUT as Logic | 3503 | 0 | 0 | 101400 | 3.45 | -| LUT as Memory | 0 | 0 | 0 | 35000 | 0.00 | -| Slice Registers | 563 | 0 | 0 | 202800 | 0.28 | -| Register as Flip Flop | 563 | 0 | 0 | 202800 | 0.28 | -| Register as Latch | 0 | 0 | 0 | 202800 | 0.00 | -| F7 Muxes | 0 | 0 | 0 | 50700 | 0.00 | -| F8 Muxes | 0 | 0 | 0 | 25350 | 0.00 | -+-------------------------+------+-------+------------+-----------+-------+ ++----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------------------+------+-------+------------+-----------+-------+ +| Slice LUTs | 3706 | 0 | 0 | 101400 | 3.65 | +| LUT as Logic | 3624 | 0 | 0 | 101400 | 3.57 | +| LUT as Memory | 82 | 0 | 0 | 35000 | 0.23 | +| LUT as Distributed RAM | 0 | 0 | | | | +| LUT as Shift Register | 82 | 0 | | | | +| Slice Registers | 4839 | 0 | 0 | 202800 | 2.39 | +| Register as Flip Flop | 4839 | 0 | 0 | 202800 | 2.39 | +| Register as Latch | 0 | 0 | 0 | 202800 | 0.00 | +| F7 Muxes | 0 | 0 | 0 | 50700 | 0.00 | +| F8 Muxes | 0 | 0 | 0 | 25350 | 0.00 | ++----------------------------+------+-------+------------+-----------+-------+ * Warning! LUT value is adjusted to account for LUT combining. @@ -59,7 +61,7 @@ Table of Contents | 0 | Yes | - | Set | | 0 | Yes | - | Reset | | 0 | Yes | Set | - | -| 563 | Yes | Reset | - | +| 4839 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -69,21 +71,24 @@ Table of Contents +--------------------------------------------+------+-------+------------+-----------+-------+ | Site Type | Used | Fixed | Prohibited | Available | Util% | +--------------------------------------------+------+-------+------------+-----------+-------+ -| Slice | 1066 | 0 | 0 | 25350 | 4.21 | -| SLICEL | 659 | 0 | | | | -| SLICEM | 407 | 0 | | | | -| LUT as Logic | 3503 | 0 | 0 | 101400 | 3.45 | +| Slice | 1259 | 0 | 0 | 25350 | 4.97 | +| SLICEL | 823 | 0 | | | | +| SLICEM | 436 | 0 | | | | +| LUT as Logic | 3624 | 0 | 0 | 101400 | 3.57 | | using O5 output only | 0 | | | | | -| using O6 output only | 2799 | | | | | -| using O5 and O6 | 704 | | | | | -| LUT as Memory | 0 | 0 | 0 | 35000 | 0.00 | +| using O6 output only | 2886 | | | | | +| using O5 and O6 | 738 | | | | | +| LUT as Memory | 82 | 0 | 0 | 35000 | 0.23 | | LUT as Distributed RAM | 0 | 0 | | | | -| LUT as Shift Register | 0 | 0 | | | | -| Slice Registers | 563 | 0 | 0 | 202800 | 0.28 | -| Register driven from within the Slice | 19 | | | | | -| Register driven from outside the Slice | 544 | | | | | -| LUT in front of the register is unused | 298 | | | | | -| LUT in front of the register is used | 246 | | | | | +| LUT as Shift Register | 82 | 0 | | | | +| using O5 output only | 1 | | | | | +| using O6 output only | 2 | | | | | +| using O5 and O6 | 79 | | | | | +| Slice Registers | 4839 | 0 | 0 | 202800 | 2.39 | +| Register driven from within the Slice | 2898 | | | | | +| Register driven from outside the Slice | 1941 | | | | | +| LUT in front of the register is unused | 862 | | | | | +| LUT in front of the register is used | 1079 | | | | | | Unique Control Sets | 2 | | 0 | 25350 | <0.01 | +--------------------------------------------+------+-------+------------+-----------+-------+ * * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets. @@ -181,16 +186,16 @@ Table of Contents +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| LUT5 | 995 | LUT | -| LUT6 | 950 | LUT | -| LUT3 | 900 | LUT | -| LUT2 | 874 | LUT | -| CARRY4 | 681 | CarryLogic | -| FDRE | 563 | Flop & Latch | -| LUT4 | 260 | LUT | -| LUT1 | 228 | LUT | +| FDRE | 4839 | Flop & Latch | +| LUT2 | 3166 | LUT | +| LUT3 | 764 | LUT | +| CARRY4 | 745 | CarryLogic | +| LUT1 | 227 | LUT | +| LUT6 | 201 | LUT | +| SRL16E | 161 | Distributed Memory | | RAMB36E1 | 32 | Block Memory | | RAMB18E1 | 4 | Block Memory | +| LUT4 | 4 | LUT | +----------+------+---------------------+ diff --git a/synth/filter_vivado.runs/impl_1/gen_run.xml b/synth/filter_vivado.runs/impl_1/gen_run.xml index 467eff5..3ea6ddc 100644 --- a/synth/filter_vivado.runs/impl_1/gen_run.xml +++ b/synth/filter_vivado.runs/impl_1/gen_run.xml @@ -1,5 +1,5 @@ - + @@ -25,12 +25,12 @@ - - - - - - + + + + + + diff --git a/synth/filter_vivado.runs/impl_1/init_design.pb b/synth/filter_vivado.runs/impl_1/init_design.pb index 4af5cfe..120a11d 100644 Binary files a/synth/filter_vivado.runs/impl_1/init_design.pb and b/synth/filter_vivado.runs/impl_1/init_design.pb differ diff --git a/synth/filter_vivado.runs/impl_1/opt_design.pb b/synth/filter_vivado.runs/impl_1/opt_design.pb index 121acc1..6d53da4 100644 Binary files a/synth/filter_vivado.runs/impl_1/opt_design.pb and b/synth/filter_vivado.runs/impl_1/opt_design.pb differ diff --git a/synth/filter_vivado.runs/impl_1/opt_design_reports.log b/synth/filter_vivado.runs/impl_1/opt_design_reports.log deleted file mode 100644 index 1318f22..0000000 --- a/synth/filter_vivado.runs/impl_1/opt_design_reports.log +++ /dev/null @@ -1,41 +0,0 @@ - -*** Running vivado - with args -m64 -nolog -nojournal -notrace -mode batch -product Vivado -source filter_reports.tcl -tclargs opt_design - - -****** Vivado v2023.2 (64-bit) - **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 - **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 - **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 - ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. - ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. - -source filter_reports.tcl -notrace -Command: open_checkpoint filter_opt.dcp - -Starting open_checkpoint Task - -Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1242.316 ; gain = 0.000 ; free physical = 206 ; free virtual = 6416 -INFO: [Device 21-403] Loading part xc7k160tffv676-1 -Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1629.965 ; gain = 0.000 ; free physical = 208 ; free virtual = 7125 -INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement -INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds -INFO: [Project 1-479] Netlist was created with Vivado 2023.2 -INFO: [Project 1-570] Preparing netlist for logic optimization -Read ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1706.652 ; gain = 1.000 ; free physical = 224 ; free virtual = 7060 -INFO: [Timing 38-478] Restoring timing data from binary archive. -INFO: [Timing 38-479] Binary timing data restore complete. -INFO: [Project 1-856] Restoring constraints from binary archive. -INFO: [Project 1-853] Binary constraint restore complete. -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.262 ; gain = 0.000 ; free physical = 124 ; free virtual = 6613 -INFO: [Project 1-111] Unisim Transformation Summary: -No Unisim elements were transformed. - -INFO: [Project 1-604] Checkpoint was created with Vivado v2023.2 (64-bit) build 4029153 -open_checkpoint: Time (s): cpu = 00:00:33 ; elapsed = 00:00:35 . Memory (MB): peak = 2311.297 ; gain = 1068.980 ; free physical = 119 ; free virtual = 6616 -INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_opted.rpt -pb filter_timing_summary_opted.pb -rpx filter_timing_summary_opted.rpx -INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. -INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs -WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew -Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design -INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 19:06:34 2023... diff --git a/synth/filter_vivado.runs/impl_1/phys_opt_design.pb b/synth/filter_vivado.runs/impl_1/phys_opt_design.pb index 17e46dc..241ad64 100644 Binary files a/synth/filter_vivado.runs/impl_1/phys_opt_design.pb and b/synth/filter_vivado.runs/impl_1/phys_opt_design.pb differ diff --git a/synth/filter_vivado.runs/impl_1/place_design.pb b/synth/filter_vivado.runs/impl_1/place_design.pb index 54c71ec..8081bc5 100644 Binary files a/synth/filter_vivado.runs/impl_1/place_design.pb and b/synth/filter_vivado.runs/impl_1/place_design.pb differ diff --git a/synth/filter_vivado.runs/impl_1/route_design.pb b/synth/filter_vivado.runs/impl_1/route_design.pb index 6c05e76..4ad4a62 100644 Binary files a/synth/filter_vivado.runs/impl_1/route_design.pb and b/synth/filter_vivado.runs/impl_1/route_design.pb differ diff --git a/synth/filter_vivado.runs/impl_1/route_design_reports.bat b/synth/filter_vivado.runs/impl_1/route_design_reports.bat deleted file mode 100644 index ffdb67f..0000000 --- a/synth/filter_vivado.runs/impl_1/route_design_reports.bat +++ /dev/null @@ -1,12 +0,0 @@ -@echo off - -rem Vivado (TM) -rem route_design_reports.bat: a Vivado-generated Script -rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. - - -set HD_SDIR=%~dp0 -cd /d "%HD_SDIR%" -set PATH=%SYSTEMROOT%\system32;%PATH% -cscript /nologo /E:JScript "%HD_SDIR%\route_design_reports.js" %* diff --git a/synth/filter_vivado.runs/impl_1/route_design_reports.js b/synth/filter_vivado.runs/impl_1/route_design_reports.js deleted file mode 100644 index 32e7621..0000000 --- a/synth/filter_vivado.runs/impl_1/route_design_reports.js +++ /dev/null @@ -1,41 +0,0 @@ -// -// Vivado(TM) -// route_design_reports.js: a Vivado-generated reports generation script for WSH 5.1/5.6 -// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -// - -echo "This script was generated under a different operating system." -echo "Please update the PATH variable below, before executing this script" -exit - -var WshShell = new ActiveXObject( "WScript.Shell" ); -var ProcEnv = WshShell.Environment( "Process" ); -var PathVal = ProcEnv("PATH"); -if ( PathVal.length == 0 ) { - PathVal = "/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2023.2/bin;"; -} else { - PathVal = "/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2023.2/bin;" + PathVal; -} - -ProcEnv("PATH") = PathVal; - -var RDScrFP = WScript.ScriptFullName; -var RDScrN = WScript.ScriptName; -var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 ); -var ISEJScriptLib = RDScrDir + "/ISEWrapReports.js"; -eval( EAInclude(ISEJScriptLib) ); - - -ISEStep( "vivado", - " -m64 -nolog -nojournal -notrace -mode batch -product Vivado -source filter_reports.tcl -tclargs route_design" ); - - - -function EAInclude( EAInclFilename ) { - var EAFso = new ActiveXObject( "Scripting.FileSystemObject" ); - var EAInclFile = EAFso.OpenTextFile( EAInclFilename ); - var EAIFContents = EAInclFile.ReadAll(); - EAInclFile.Close(); - return EAIFContents; -} diff --git a/synth/filter_vivado.runs/impl_1/route_design_reports.sh b/synth/filter_vivado.runs/impl_1/route_design_reports.sh deleted file mode 100755 index b5ca98b..0000000 --- a/synth/filter_vivado.runs/impl_1/route_design_reports.sh +++ /dev/null @@ -1,40 +0,0 @@ -#!/bin/sh - -# -# Vivado(TM) -# route_design_reports.sh: a Vivado-generated reports generation script for UNIX -# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -# - -if [ -z "$PATH" ]; then - PATH=/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2023.2/bin -else - PATH=/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2023.2/bin:$PATH -fi -export PATH - -if [ -z "$LD_LIBRARY_PATH" ]; then - LD_LIBRARY_PATH= -else - LD_LIBRARY_PATH=:$LD_LIBRARY_PATH -fi -export LD_LIBRARY_PATH - -HD_PWD='/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1' -cd "$HD_PWD" - -HD_LOG=route_design_reports.log -/bin/touch $HD_LOG - -ISEStep="./ISEWrapReports.sh" -EAStep() -{ - $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1 - if [ $? -ne 0 ] - then - exit - fi -} - -EAStep vivado -m64 -nolog -nojournal -notrace -mode batch -product Vivado -source filter_reports.tcl -tclargs route_design \ No newline at end of file diff --git a/synth/filter_vivado.runs/impl_1/runme.log b/synth/filter_vivado.runs/impl_1/runme.log index acf5508..ad5661b 100644 --- a/synth/filter_vivado.runs/impl_1/runme.log +++ b/synth/filter_vivado.runs/impl_1/runme.log @@ -11,13 +11,13 @@ ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source filter.tcl -notrace -create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1308.508 ; gain = 0.023 ; free physical = 106 ; free virtual = 6598 -Command: link_design -top filter -part xc7k160tffv676-1 -mode out_of_context +create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1271.086 ; gain = 13.898 ; free physical = 453 ; free virtual = 4400 +Command: link_design -top filter -part xc7k160tffv676-1 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 INFO: [Device 21-403] Loading part xc7k160tffv676-1 -Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1630.383 ; gain = 0.000 ; free physical = 131 ; free virtual = 6415 -INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement +Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1630.898 ; gain = 0.000 ; free physical = 245 ; free virtual = 4101 +INFO: [Netlist 29-17] Analyzing 781 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2023.2 INFO: [Project 1-570] Preparing netlist for logic optimization @@ -25,13 +25,13 @@ Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1767.770 ; gain = 0.000 ; free physical = 122 ; free virtual = 6282 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1749.242 ; gain = 0.000 ; free physical = 141 ; free virtual = 4005 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. 7 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully -link_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:10 . Memory (MB): peak = 1773.742 ; gain = 465.234 ; free physical = 114 ; free virtual = 6277 +link_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 1752.246 ; gain = 481.160 ; free physical = 201 ; free virtual = 4001 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t' @@ -42,111 +42,111 @@ INFO: [DRC 23-27] Running DRC with 4 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1824.535 ; gain = 50.793 ; free physical = 205 ; free virtual = 6272 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1801.070 ; gain = 48.824 ; free physical = 184 ; free virtual = 3988 Starting Cache Timing Information Task WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] INFO: [Timing 38-35] Done setting XDC timing constraints. -Ending Cache Timing Information Task | Checksum: 10236edc4 +Ending Cache Timing Information Task | Checksum: b84391e5 -Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 2345.418 ; gain = 520.883 ; free physical = 117 ; free virtual = 5807 +Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2321.945 ; gain = 520.875 ; free physical = 131 ; free virtual = 3537 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup -Phase 1.1 Core Generation And Design Setup | Checksum: 10236edc4 +Phase 1.1 Core Generation And Design Setup | Checksum: b84391e5 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 146 ; free virtual = 5487 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2627.750 ; gain = 0.000 ; free physical = 138 ; free virtual = 3239 Phase 1.2 Setup Constraints And Sort Netlist -Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 10236edc4 +Phase 1.2 Setup Constraints And Sort Netlist | Checksum: b84391e5 -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 145 ; free virtual = 5487 -Phase 1 Initialization | Checksum: 10236edc4 +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2627.750 ; gain = 0.000 ; free physical = 139 ; free virtual = 3239 +Phase 1 Initialization | Checksum: b84391e5 -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 145 ; free virtual = 5487 +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2627.750 ; gain = 0.000 ; free physical = 139 ; free virtual = 3239 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update -Phase 2.1 Timer Update | Checksum: 10236edc4 +Phase 2.1 Timer Update | Checksum: b84391e5 -Time (s): cpu = 00:00:00.4 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 138 ; free virtual = 5486 +Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2627.750 ; gain = 0.000 ; free physical = 144 ; free virtual = 3235 Phase 2.2 Timing Data Collection -Phase 2.2 Timing Data Collection | Checksum: 10236edc4 +Phase 2.2 Timing Data Collection | Checksum: b84391e5 -Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 137 ; free virtual = 5486 -Phase 2 Timer Update And Timing Data Collection | Checksum: 10236edc4 +Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2627.750 ; gain = 0.000 ; free physical = 139 ; free virtual = 3233 +Phase 2 Timer Update And Timing Data Collection | Checksum: b84391e5 -Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 137 ; free virtual = 5486 +Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.37 . Memory (MB): peak = 2627.750 ; gain = 0.000 ; free physical = 139 ; free virtual = 3233 Phase 3 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 3 Retarget | Checksum: 10c3daf90 +Phase 3 Retarget | Checksum: 9b15171f -Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 134 ; free virtual = 5484 -Retarget | Checksum: 10c3daf90 +Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.61 . Memory (MB): peak = 2627.750 ; gain = 0.000 ; free physical = 122 ; free virtual = 3229 +Retarget | Checksum: 9b15171f INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 4 Constant propagation | Checksum: 9bde81ac +Phase 4 Constant propagation | Checksum: 11aad8966 -Time (s): cpu = 00:00:00.63 ; elapsed = 00:00:00.46 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 132 ; free virtual = 5484 -Constant propagation | Checksum: 9bde81ac +Time (s): cpu = 00:00:00.87 ; elapsed = 00:00:00.73 . Memory (MB): peak = 2627.750 ; gain = 0.000 ; free physical = 130 ; free virtual = 3228 +Constant propagation | Checksum: 11aad8966 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep -Phase 5 Sweep | Checksum: f9b192b3 +Phase 5 Sweep | Checksum: 90bb4c32 -Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2647.285 ; gain = 0.000 ; free physical = 115 ; free virtual = 5482 -Sweep | Checksum: f9b192b3 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.96 . Memory (MB): peak = 2627.750 ; gain = 0.000 ; free physical = 133 ; free virtual = 3226 +Sweep | Checksum: 90bb4c32 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells Phase 6 BUFG optimization -Phase 6 BUFG optimization | Checksum: f9b192b3 +Phase 6 BUFG optimization | Checksum: 90bb4c32 -Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.66 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 115 ; free virtual = 5482 -BUFG optimization | Checksum: f9b192b3 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2659.766 ; gain = 32.016 ; free physical = 133 ; free virtual = 3226 +BUFG optimization | Checksum: 90bb4c32 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs -Phase 7 Shift Register Optimization | Checksum: f9b192b3 +Phase 7 Shift Register Optimization | Checksum: 90bb4c32 -Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 115 ; free virtual = 5482 -Shift Register Optimization | Checksum: f9b192b3 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2659.766 ; gain = 32.016 ; free physical = 133 ; free virtual = 3226 +Shift Register Optimization | Checksum: 90bb4c32 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist -Phase 8 Post Processing Netlist | Checksum: f9b192b3 +Phase 8 Post Processing Netlist | Checksum: 90bb4c32 -Time (s): cpu = 00:00:00.84 ; elapsed = 00:00:00.69 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 115 ; free virtual = 5482 -Post Processing Netlist | Checksum: f9b192b3 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2659.766 ; gain = 32.016 ; free physical = 133 ; free virtual = 3226 +Post Processing Netlist | Checksum: 90bb4c32 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes -Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: d19459d4 +Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 7c6f4f97 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 112 ; free virtual = 5479 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2659.766 ; gain = 32.016 ; free physical = 129 ; free virtual = 3224 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task -Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2679.301 ; gain = 0.000 ; free physical = 111 ; free virtual = 5479 -Phase 9.2 Verifying Netlist Connectivity | Checksum: d19459d4 +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2659.766 ; gain = 0.000 ; free physical = 129 ; free virtual = 3224 +Phase 9.2 Verifying Netlist Connectivity | Checksum: 7c6f4f97 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 111 ; free virtual = 5479 -Phase 9 Finalization | Checksum: d19459d4 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2659.766 ; gain = 32.016 ; free physical = 129 ; free virtual = 3224 +Phase 9 Finalization | Checksum: 7c6f4f97 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 111 ; free virtual = 5479 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2659.766 ; gain = 32.016 ; free physical = 129 ; free virtual = 3224 Opt_design Change Summary ========================= @@ -163,11 +163,11 @@ Opt_design Change Summary ------------------------------------------------------------------------------------------------------------------------- -Ending Logic Optimization Task | Checksum: d19459d4 +Ending Logic Optimization Task | Checksum: 7c6f4f97 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2679.301 ; gain = 32.016 ; free physical = 109 ; free virtual = 5479 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2659.766 ; gain = 32.016 ; free physical = 124 ; free virtual = 3223 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 -Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2679.301 ; gain = 0.000 ; free physical = 105 ; free virtual = 5477 +Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2659.766 ; gain = 0.000 ; free physical = 122 ; free virtual = 3223 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. @@ -184,27 +184,27 @@ Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 36 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 72 -Ending PowerOpt Patch Enables Task | Checksum: d19459d4 +Ending PowerOpt Patch Enables Task | Checksum: 7c6f4f97 -Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.22 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 192 ; free virtual = 5341 -Ending Power Optimization Task | Checksum: d19459d4 +Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 253 ; free virtual = 3103 +Ending Power Optimization Task | Checksum: 7c6f4f97 -Time (s): cpu = 00:00:20 ; elapsed = 00:00:19 . Memory (MB): peak = 2817.184 ; gain = 137.883 ; free physical = 172 ; free virtual = 5341 +Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 2799.641 ; gain = 139.875 ; free physical = 247 ; free virtual = 3101 Starting Final Cleanup Task -Ending Final Cleanup Task | Checksum: d19459d4 +Ending Final Cleanup Task | Checksum: 7c6f4f97 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 172 ; free virtual = 5341 +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 247 ; free virtual = 3101 Starting Netlist Obfuscation Task -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 171 ; free virtual = 5343 -Ending Netlist Obfuscation Task | Checksum: d19459d4 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 246 ; free virtual = 3101 +Ending Netlist Obfuscation Task | Checksum: 7c6f4f97 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 171 ; free virtual = 5343 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 246 ; free virtual = 3101 INFO: [Common 17-83] Releasing license: Implementation 30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully -opt_design: Time (s): cpu = 00:00:39 ; elapsed = 00:00:39 . Memory (MB): peak = 2817.184 ; gain = 1043.441 ; free physical = 171 ; free virtual = 5343 +opt_design: Time (s): cpu = 00:00:43 ; elapsed = 00:00:41 . Memory (MB): peak = 2799.641 ; gain = 1047.395 ; free physical = 244 ; free virtual = 3100 INFO: [runtcl-4] Executing : report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx Command: report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx INFO: [IP_Flow 19-234] Refreshing IP repositories @@ -213,10 +213,15 @@ INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2023.2 INFO: [DRC 23-27] Running DRC with 4 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_drc_opted.rpt. report_drc completed successfully +INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_opted.rpt -pb filter_timing_summary_opted.pb -rpx filter_timing_summary_opted.rpx WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs +WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew +Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 111 ; free virtual = 5315 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 190 ; free virtual = 3050 INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_opt.dcp' has been generated. Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' @@ -236,58 +241,58 @@ Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 142 ; free virtual = 5289 -Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3583ee0c +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 127 ; free virtual = 3034 +Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 3c0b3cc1 -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 142 ; free virtual = 5289 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 142 ; free virtual = 5289 +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 127 ; free virtual = 3034 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 127 ; free virtual = 3034 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 3d558abc +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 8ad34538 -Time (s): cpu = 00:00:00.67 ; elapsed = 00:00:00.45 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 132 ; free virtual = 5293 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 168 ; free virtual = 3029 Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 8cce5483 +Phase 1.3 Build Placer Netlist Model | Checksum: b07d1e41 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 111 ; free virtual = 5288 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 143 ; free virtual = 3025 Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 8cce5483 +Phase 1.4 Constrain Clocks/Macros | Checksum: b07d1e41 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 111 ; free virtual = 5288 -Phase 1 Placer Initialization | Checksum: 8cce5483 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 143 ; free virtual = 3025 +Phase 1 Placer Initialization | Checksum: b07d1e41 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 111 ; free virtual = 5288 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 138 ; free virtual = 3024 Phase 2 Global Placement Phase 2.1 Floorplanning -Phase 2.1 Floorplanning | Checksum: 47fa083f +Phase 2.1 Floorplanning | Checksum: 9cf052e5 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 109 ; free virtual = 5287 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 128 ; free virtual = 3026 Phase 2.2 Update Timing before SLR Path Opt -Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1275ad596 +Phase 2.2 Update Timing before SLR Path Opt | Checksum: c73f8a70 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 109 ; free virtual = 5286 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 127 ; free virtual = 3026 Phase 2.3 Post-Processing in Floorplanning -Phase 2.3 Post-Processing in Floorplanning | Checksum: 1275ad596 +Phase 2.3 Post-Processing in Floorplanning | Checksum: c73f8a70 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 109 ; free virtual = 5287 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 127 ; free virtual = 3026 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis -Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1457cd503 +Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 19a874187 -Time (s): cpu = 00:00:43 ; elapsed = 00:00:17 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 169 ; free virtual = 5289 +Time (s): cpu = 00:00:27 ; elapsed = 00:00:12 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 197 ; free virtual = 3029 Phase 2.4.2 Physical Synthesis In Placer -INFO: [Physopt 32-1035] Found 10 LUTNM shape to break, 4 LUT instances to create LUTNM shape -INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 10, total 10, new lutff created 0 -INFO: [Physopt 32-1138] End 1 Pass. Optimized 12 nets or LUTs. Breaked 10 LUTs, combined 2 existing LUTs and moved 0 existing LUT +INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 4 LUT instances to create LUTNM shape +INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 +INFO: [Physopt 32-1138] End 1 Pass. Optimized 2 nets or LUTs. Breaked 0 LUT, combined 2 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell @@ -295,9 +300,9 @@ INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -INFO: [Physopt 32-1401] No candidate cells found for Shift Register optimization. -INFO: [Physopt 32-677] No candidate cells for Shift Register optimization found in the design -INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell +INFO: [Physopt 32-1402] Pass 1: Identified 40 candidate cells for Shift Register optimization. +INFO: [Physopt 32-775] End 1 Pass. Optimized 23 nets or cells. Created 45 new cells, deleted 0 existing cell and moved 0 existing cell +Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 168 ; free virtual = 3029 INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design @@ -306,7 +311,7 @@ INFO: [Physopt 32-846] No candidate cells for URAM register optimization found i INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 144 ; free virtual = 5284 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 168 ; free virtual = 3029 Summary of Physical Synthesis Optimizations ============================================ @@ -315,78 +320,78 @@ Summary of Physical Synthesis Optimizations ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- -| LUT Combining | 10 | 2 | 12 | 0 | 1 | 00:00:00 | +| LUT Combining | 0 | 2 | 2 | 0 | 1 | 00:00:00 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Shift Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | +| Shift Register | 45 | 0 | 23 | 0 | 1 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Total | 10 | 2 | 12 | 0 | 9 | 00:00:00 | +| Total | 45 | 2 | 25 | 0 | 9 | 00:00:00 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- -Phase 2.4.2 Physical Synthesis In Placer | Checksum: 19c5c57a6 +Phase 2.4.2 Physical Synthesis In Placer | Checksum: 20b107fd7 -Time (s): cpu = 00:00:45 ; elapsed = 00:00:18 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 144 ; free virtual = 5284 -Phase 2.4 Global Placement Core | Checksum: 1b40ef446 +Time (s): cpu = 00:00:29 ; elapsed = 00:00:13 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 164 ; free virtual = 3027 +Phase 2.4 Global Placement Core | Checksum: 1f000dffd -Time (s): cpu = 00:00:47 ; elapsed = 00:00:18 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 143 ; free virtual = 5284 -Phase 2 Global Placement | Checksum: 1b40ef446 +Time (s): cpu = 00:00:31 ; elapsed = 00:00:14 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 163 ; free virtual = 3026 +Phase 2 Global Placement | Checksum: 1f000dffd -Time (s): cpu = 00:00:47 ; elapsed = 00:00:19 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 143 ; free virtual = 5284 +Time (s): cpu = 00:00:31 ; elapsed = 00:00:14 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 162 ; free virtual = 3027 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 11f4d2582 +Phase 3.1 Commit Multi Column Macros | Checksum: 1ec652ec9 -Time (s): cpu = 00:00:48 ; elapsed = 00:00:19 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 142 ; free virtual = 5283 +Time (s): cpu = 00:00:33 ; elapsed = 00:00:14 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 154 ; free virtual = 3025 Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 12b805f00 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 13458fbed -Time (s): cpu = 00:00:53 ; elapsed = 00:00:21 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 137 ; free virtual = 5282 +Time (s): cpu = 00:00:36 ; elapsed = 00:00:16 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 139 ; free virtual = 3023 Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 157230410 +Phase 3.3 Area Swap Optimization | Checksum: 10277a41b -Time (s): cpu = 00:00:53 ; elapsed = 00:00:22 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 136 ; free virtual = 5282 +Time (s): cpu = 00:00:36 ; elapsed = 00:00:16 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 138 ; free virtual = 3023 Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 128b350f2 +Phase 3.4 Pipeline Register Optimization | Checksum: d226fbde -Time (s): cpu = 00:00:53 ; elapsed = 00:00:22 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 136 ; free virtual = 5282 +Time (s): cpu = 00:00:36 ; elapsed = 00:00:16 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 138 ; free virtual = 3023 Phase 3.5 Fast Optimization -Phase 3.5 Fast Optimization | Checksum: 1632181f8 +Phase 3.5 Fast Optimization | Checksum: 132b21e47 -Time (s): cpu = 00:00:58 ; elapsed = 00:00:24 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 130 ; free virtual = 5276 +Time (s): cpu = 00:00:41 ; elapsed = 00:00:18 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 134 ; free virtual = 3022 Phase 3.6 Small Shape Detail Placement -Phase 3.6 Small Shape Detail Placement | Checksum: f844008a +Phase 3.6 Small Shape Detail Placement | Checksum: 18283862c -Time (s): cpu = 00:01:00 ; elapsed = 00:00:26 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5275 +Time (s): cpu = 00:00:43 ; elapsed = 00:00:20 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 118 ; free virtual = 3014 Phase 3.7 Re-assign LUT pins -Phase 3.7 Re-assign LUT pins | Checksum: 14d2456fe +Phase 3.7 Re-assign LUT pins | Checksum: 19d13be25 -Time (s): cpu = 00:01:01 ; elapsed = 00:00:26 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5273 +Time (s): cpu = 00:00:44 ; elapsed = 00:00:20 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 117 ; free virtual = 3014 Phase 3.8 Pipeline Register Optimization -Phase 3.8 Pipeline Register Optimization | Checksum: 17ad421e0 +Phase 3.8 Pipeline Register Optimization | Checksum: 16d448768 -Time (s): cpu = 00:01:01 ; elapsed = 00:00:26 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5273 +Time (s): cpu = 00:00:44 ; elapsed = 00:00:20 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 117 ; free virtual = 3014 Phase 3.9 Fast Optimization -Phase 3.9 Fast Optimization | Checksum: 17f4b35b0 +Phase 3.9 Fast Optimization | Checksum: 150dbd156 -Time (s): cpu = 00:01:06 ; elapsed = 00:00:29 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 110 ; free virtual = 5267 -Phase 3 Detail Placement | Checksum: 17f4b35b0 +Time (s): cpu = 00:00:50 ; elapsed = 00:00:23 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 113 ; free virtual = 3012 +Phase 3 Detail Placement | Checksum: 150dbd156 -Time (s): cpu = 00:01:06 ; elapsed = 00:00:29 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 110 ; free virtual = 5267 +Time (s): cpu = 00:00:50 ; elapsed = 00:00:23 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 113 ; free virtual = 3012 Phase 4 Post Placement Optimization and Clean-Up @@ -395,7 +400,7 @@ WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 1caaa20ca +Post Placement Optimization Initialization | Checksum: 151f3014f Phase 4.1.1.1 BUFG Insertion @@ -403,33 +408,33 @@ Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.908 | TNS=-6490.125 | -Phase 1 Physical Synthesis Initialization | Checksum: 179e6ab06 +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.433 | TNS=-22.659 | +Phase 1 Physical Synthesis Initialization | Checksum: 1b42db68e -Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.23 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 153 ; free virtual = 5299 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.55 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 221 ; free virtual = 3024 INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. -Ending Physical Synthesis Task | Checksum: 179e6ab06 +Ending Physical Synthesis Task | Checksum: 1b42db68e -Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.34 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 151 ; free virtual = 5296 -Phase 4.1.1.1 BUFG Insertion | Checksum: 1caaa20ca +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.7 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 221 ; free virtual = 3024 +Phase 4.1.1.1 BUFG Insertion | Checksum: 151f3014f -Time (s): cpu = 00:01:11 ; elapsed = 00:00:31 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 151 ; free virtual = 5296 +Time (s): cpu = 00:00:58 ; elapsed = 00:00:27 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 221 ; free virtual = 3024 Phase 4.1.1.2 Post Placement Timing Optimization -INFO: [Place 30-746] Post Placement Timing Summary WNS=-16.162. For the most accurate timing information please run report_timing. -Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 186ecb07f +INFO: [Place 30-746] Post Placement Timing Summary WNS=-1.198. For the most accurate timing information please run report_timing. +Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: dd4b4bc1 -Time (s): cpu = 00:01:54 ; elapsed = 00:01:11 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 122 ; free virtual = 5294 +Time (s): cpu = 00:01:40 ; elapsed = 00:01:07 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 130 ; free virtual = 3003 -Time (s): cpu = 00:01:54 ; elapsed = 00:01:11 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 122 ; free virtual = 5294 -Phase 4.1 Post Commit Optimization | Checksum: 186ecb07f +Time (s): cpu = 00:01:41 ; elapsed = 00:01:07 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 130 ; free virtual = 3003 +Phase 4.1 Post Commit Optimization | Checksum: dd4b4bc1 -Time (s): cpu = 00:01:54 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 122 ; free virtual = 5295 +Time (s): cpu = 00:01:41 ; elapsed = 00:01:07 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 130 ; free virtual = 3003 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 186ecb07f +Phase 4.2 Post Placement Cleanup | Checksum: dd4b4bc1 -Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 +Time (s): cpu = 00:01:41 ; elapsed = 00:01:08 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 128 ; free virtual = 3002 Phase 4.3 Placer Reporting @@ -439,51 +444,51 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| -| North| 4x4| 8x8| +| North| 1x1| 4x4| |___________|___________________|___________________| -| South| 2x2| 4x4| +| South| 1x1| 4x4| |___________|___________________|___________________| -| East| 4x4| 8x8| +| East| 1x1| 1x1| |___________|___________________|___________________| -| West| 4x4| 4x4| +| West| 1x1| 1x1| |___________|___________________|___________________| -Phase 4.3.1 Print Estimated Congestion | Checksum: 186ecb07f +Phase 4.3.1 Print Estimated Congestion | Checksum: dd4b4bc1 -Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 -Phase 4.3 Placer Reporting | Checksum: 186ecb07f +Time (s): cpu = 00:01:41 ; elapsed = 00:01:08 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 128 ; free virtual = 3002 +Phase 4.3 Placer Reporting | Checksum: dd4b4bc1 -Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 +Time (s): cpu = 00:01:41 ; elapsed = 00:01:08 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 128 ; free virtual = 3002 Phase 4.4 Final Placement Cleanup -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 128 ; free virtual = 3003 -Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 2313e4908 +Time (s): cpu = 00:01:41 ; elapsed = 00:01:08 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 128 ; free virtual = 3003 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 8d98dd64 -Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 -Ending Placer Task | Checksum: 1402e79b2 +Time (s): cpu = 00:01:41 ; elapsed = 00:01:08 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 128 ; free virtual = 3003 +Ending Placer Task | Checksum: 46adcee8 -Time (s): cpu = 00:01:55 ; elapsed = 00:01:12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 -75 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered. +Time (s): cpu = 00:01:41 ; elapsed = 00:01:08 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 128 ; free virtual = 3003 +77 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully -place_design: Time (s): cpu = 00:01:57 ; elapsed = 00:01:13 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 117 ; free virtual = 5294 +place_design: Time (s): cpu = 00:01:45 ; elapsed = 00:01:09 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 117 ; free virtual = 3001 INFO: [runtcl-4] Executing : report_io -file filter_io_placed.rpt -report_io: Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 123 ; free virtual = 5306 +report_io: Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.44 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 225 ; free virtual = 3021 INFO: [runtcl-4] Executing : report_utilization -file filter_utilization_placed.rpt -pb filter_utilization_placed.pb INFO: [runtcl-4] Executing : report_control_sets -verbose -file filter_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 129 ; free virtual = 5308 +report_control_sets: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 207 ; free virtual = 3007 INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 133 ; free virtual = 5307 -Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 201 ; free virtual = 5303 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 201 ; free virtual = 5303 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 206 ; free virtual = 3008 +Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.67 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 198 ; free virtual = 3008 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 196 ; free virtual = 3008 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 191 ; free virtual = 5293 -Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 190 ; free virtual = 5293 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 190 ; free virtual = 5293 -Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.76 . Memory (MB): peak = 2817.184 ; gain = 0.000 ; free physical = 190 ; free virtual = 5293 +Wrote RouteStorage: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 185 ; free virtual = 3005 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 184 ; free virtual = 3005 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 184 ; free virtual = 3005 +Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2799.641 ; gain = 0.000 ; free physical = 184 ; free virtual = 3005 INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_placed.dcp' has been generated. Command: phys_opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' @@ -493,366 +498,225 @@ Starting Initial Update Timing Task WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 168 ; free virtual = 5274 -INFO: [Vivado_Tcl 4-1435] PhysOpt_Tcl_Interface Runtime Before Starting Physical Synthesis Task | CPU: 2.64s | WALL: 1.05s -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 168 ; free virtual = 5274 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 172 ; free virtual = 2990 +INFO: [Vivado_Tcl 4-1435] PhysOpt_Tcl_Interface Runtime Before Starting Physical Synthesis Task | CPU: 3.88s | WALL: 1.78s +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 172 ; free virtual = 2990 Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.162 | TNS=-6269.708 | -Phase 1 Physical Synthesis Initialization | Checksum: 1c58d1c6b +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.198 | TNS=-18.999 | +Phase 1 Physical Synthesis Initialization | Checksum: eda825fd -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.93 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 156 ; free virtual = 5268 -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.162 | TNS=-6269.708 | +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 162 ; free virtual = 2992 +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.198 | TNS=-18.999 | Phase 2 DSP Register Optimization INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design. INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell -Phase 2 DSP Register Optimization | Checksum: 1c58d1c6b +Phase 2 DSP Register Optimization | Checksum: eda825fd -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.98 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 156 ; free virtual = 5269 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 162 ; free virtual = 2992 Phase 3 Critical Path Optimization -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.162 | TNS=-6269.708 | -INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][52]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-663] Processed net in_key[8]. Re-placed instance registered_input.in_key_reg[8] -INFO: [Physopt 32-735] Processed net in_key[8]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.142 | TNS=-6267.728 | -INFO: [Physopt 32-81] Processed net in_key[72]. Replicated 2 times. -INFO: [Physopt 32-735] Processed net in_key[72]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.119 | TNS=-6265.451 | -INFO: [Physopt 32-702] Processed net in_key[72]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_4_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_24_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_26_n_6. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_29_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_59_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_98_n_6. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_106_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_101_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_109_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_95_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_103_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_104_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_190_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_350[5]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_262_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_264_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_282_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_283_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_27_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_30_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_33_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_93_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_110_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_96_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_127_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/minusOp10_out_0[9]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_286_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_479_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/minusOp12_out[25]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_577_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_571_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_573_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/final/memory_reg_0_i_99_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_276_0[3]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_429_0[29]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_279_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_434_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_535_0[24]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_725_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1046_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-710] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1046_n_0. Critical path length was reduced through logic transformation on cell hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1046_comp. -INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1100__0_n_0. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.103 | TNS=-6263.768 | -INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][34]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-663] Processed net in_key[0]. Re-placed instance registered_input.in_key_reg[0] -INFO: [Physopt 32-735] Processed net in_key[0]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.102 | TNS=-6259.511 | -INFO: [Physopt 32-81] Processed net in_key[8]. Replicated 2 times. -INFO: [Physopt 32-735] Processed net in_key[8]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.099 | TNS=-6259.214 | -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1047_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-710] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1047_n_0. Critical path length was reduced through logic transformation on cell hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1047_comp. -INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]13_out[21]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.072 | TNS=-6256.541 | -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_433_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/mix_stage[1][a][25]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_513_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_721_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][a][23]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1044_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-710] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1044_n_0. Critical path length was reduced through logic transformation on cell hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1044_comp. -INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]7_out[20]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.060 | TNS=-6253.472 | -INFO: [Physopt 32-81] Processed net in_key[2]. Replicated 3 times. -INFO: [Physopt 32-735] Processed net in_key[2]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.059 | TNS=-6252.086 | -INFO: [Physopt 32-702] Processed net storage_generate[2].storage/memory_rule[2][124]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-81] Processed net in_key[65]. Replicated 2 times. -INFO: [Physopt 32-735] Processed net in_key[65]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.046 | TNS=-6250.701 | -INFO: [Physopt 32-81] Processed net in_key[64]. Replicated 5 times. -INFO: [Physopt 32-735] Processed net in_key[64]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.045 | TNS=-6250.502 | -INFO: [Physopt 32-663] Processed net in_key[9]. Re-placed instance registered_input.in_key_reg[9] -INFO: [Physopt 32-735] Processed net in_key[9]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.045 | TNS=-6250.502 | -INFO: [Physopt 32-81] Processed net in_key[68]. Replicated 1 times. -INFO: [Physopt 32-735] Processed net in_key[68]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.045 | TNS=-6250.007 | -INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][88]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-81] Processed net in_key[1]. Replicated 3 times. -INFO: [Physopt 32-735] Processed net in_key[1]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.043 | TNS=-6248.027 | -INFO: [Physopt 32-663] Processed net in_key[5]. Re-placed instance registered_input.in_key_reg[5] -INFO: [Physopt 32-735] Processed net in_key[5]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.041 | TNS=-6247.730 | -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_431_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/minusOp4_out[27]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_741_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-710] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_741_n_0. Critical path length was reduced through logic transformation on cell hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_741_comp. -INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]13_out[25]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.040 | TNS=-6247.631 | -INFO: [Physopt 32-702] Processed net hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1052_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-663] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]13_out[21]. Re-placed instance hash_generate[0].hash/mix_pipeline[0].mix/memory_reg_0_i_1101 -INFO: [Physopt 32-735] Processed net hash_generate[0].hash/mix_pipeline[0].mix/s[0][c]13_out[21]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.040 | TNS=-6245.453 | -INFO: [Physopt 32-663] Processed net in_key[74]. Re-placed instance registered_input.in_key_reg[74] -INFO: [Physopt 32-735] Processed net in_key[74]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.038 | TNS=-6245.057 | -INFO: [Physopt 32-663] Processed net in_key[9]. Re-placed instance registered_input.in_key_reg[9] -INFO: [Physopt 32-735] Processed net in_key[9]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.038 | TNS=-6245.255 | -INFO: [Physopt 32-81] Processed net in_key[69]. Replicated 1 times. -INFO: [Physopt 32-735] Processed net in_key[69]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.036 | TNS=-6244.364 | -INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][34]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-663] Processed net in_key[66]. Re-placed instance registered_input.in_key_reg[66] -INFO: [Physopt 32-735] Processed net in_key[66]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.030 | TNS=-6243.770 | -INFO: [Physopt 32-702] Processed net in_key[66]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_26_n_6. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_98_n_7. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_350__0[5]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/minusOp10_out_0[20]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_810__0[5]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_276_0[3]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/O75[29]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_435_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/mix_stage[1][a][25]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_730_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][a][21]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.198 | TNS=-18.999 | +INFO: [Physopt 32-702] Processed net OUTPUT_KEY_FOUND. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][40]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/out_key_found13_out. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_6_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_15_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_29_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_44_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_59_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_74_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_89_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_104_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_119_n_0. Optimizations did not improve timing on the net. INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. -INFO: [Physopt 32-735] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1066_n_0. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.029 | TNS=-6243.275 | -INFO: [Physopt 32-702] Processed net storage_generate[2].storage/memory_rule[2][124]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net in_key[0]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_16__1_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_29_n_6. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_85__1_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_101_n_4. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_190__1_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_350__1[5]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_93__1_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_238__1_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/minusOp10_out_0[13]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_322__1_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/memory_reg_0_i_808__1[5]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/L8_out[17]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1144__1_0[17]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-608] Optimized 1 net. Swapped 22 pins. -INFO: [Physopt 32-735] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1151__1_n_0. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.028 | TNS=-6243.176 | -INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][88]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net in_key[7]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_16__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_29_n_6. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_85__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_101_n_4. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_191__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_350__2[4]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_93__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_238__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/minusOp10_out_1[13]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_322__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_780__1[5]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_302_0[1]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/mix_stage[1][b][31]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_428_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_534_0[28]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_724_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-663] Processed net hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[27]. Re-placed instance hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_732 -INFO: [Physopt 32-735] Processed net hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[27]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.028 | TNS=-6241.592 | -INFO: [Physopt 32-702] Processed net in_key[65]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/final/L8_out[25]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1144__1_0[25]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_1155__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_537_0[21]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-663] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0. Re-placed instance hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1 -INFO: [Physopt 32-735] Processed net hash_generate[2].hash/mix_pipeline[0].mix/memory_reg_0_i_997__1_n_0. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.025 | TNS=-6240.800 | -INFO: [Physopt 32-663] Processed net in_key[10]. Re-placed instance registered_input.in_key_reg[10] -INFO: [Physopt 32-735] Processed net in_key[10]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.025 | TNS=-6240.800 | -INFO: [Physopt 32-702] Processed net in_key[71]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_302_0[0]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/O75[30]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_430_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/mix_stage[1][a][29]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_670_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][a][25]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1052_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]7_out[20]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_511_0[19]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_962_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/registered_input.in_key_reg[72]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/minusOp12_out[15]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_889__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/minusOp14_out[13]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_797__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_513_n_6. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/O76[9]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.025 | TNS=-6240.800 | -Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 137 ; free virtual = 5271 -Phase 3 Critical Path Optimization | Checksum: 17af5ebfb +INFO: [Physopt 32-735] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_135_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.188 | TNS=-18.837 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][31]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/CO[0]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_10_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_20_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_34_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_49_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_64_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_79_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_94_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_109_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_124_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_i_143_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.179 | TNS=-18.828 | +INFO: [Physopt 32-702] Processed net OUTPUT_DATA[13]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][58]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-710] Processed net storage_generate[2].storage/D[13]. Critical path length was reduced through logic transformation on cell storage_generate[2].storage/registered_output.OUTPUT_DATA[13]_i_1_comp. +INFO: [Physopt 32-735] Processed net storage_generate[3].storage/memory_reg_0_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.179 | TNS=-18.809 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][37]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_136_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.177 | TNS=-18.754 | +INFO: [Physopt 32-702] Processed net OUTPUT_DATA[10]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_reg_0_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/out_key_found1. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_25_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_39_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_54_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_69_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_84_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_99_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_114_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_132_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.164 | TNS=-18.128 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][25]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_139_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_i_154_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.144 | TNS=-18.108 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][58]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_107_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.144 | TNS=-18.108 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][46]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.136 | TNS=-18.053 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][22]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_i_155_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.136 | TNS=-18.053 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][42]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_123_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.133 | TNS=-18.027 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][46]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_i_127_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.132 | TNS=-18.017 | +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][37]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_129_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_144_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_159_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.123 | TNS=-17.883 | +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][76]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_115_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.123 | TNS=-17.789 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][73]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_91_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.121 | TNS=-17.735 | +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/memory_rule[2][22]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/memory_reg_0_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/CO[0]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_4_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_8_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_13_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_18_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_23_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_28_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_33_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_38_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_43_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA_reg[15]_i_48_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_55_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.115 | TNS=-17.724 | +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][78]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_103_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.110 | TNS=-17.419 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][18]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_i_156_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.101 | TNS=-17.410 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][40]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_i_140_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.098 | TNS=-17.407 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][81]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_77_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.097 | TNS=-17.376 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][81]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_i_82_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.094 | TNS=-17.369 | +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][22]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_157_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_164_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.090 | TNS=-17.264 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][27]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_i_153_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.087 | TNS=-17.260 | +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][40]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_158_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.086 | TNS=-17.215 | +INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][94]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[0].storage/registered_output.OUTPUT_KEY_FOUND_i_67_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.084 | TNS=-17.213 | +INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][25]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[3].storage/registered_output.OUTPUT_KEY_FOUND_i_163_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.084 | TNS=-16.983 | +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/memory_rule[2][17]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[2].storage/registered_output.OUTPUT_DATA[15]_i_56_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 6 pins. +INFO: [Physopt 32-735] Processed net storage_generate[1].storage/memory_reg_0_16. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.078 | TNS=-16.977 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][48]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-608] Optimized 1 net. Swapped 26 pins. +INFO: [Physopt 32-735] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_121_n_0. Optimization improves timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.072 | TNS=-16.932 | +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_reg_0_16. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net OUTPUT_KEY_FOUND. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][46]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/out_key_found13_out. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_reg_0_16. Optimizations did not improve timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.072 | TNS=-16.932 | +Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 143 ; free virtual = 2984 +Phase 3 Critical Path Optimization | Checksum: eda825fd -Time (s): cpu = 00:00:41 ; elapsed = 00:00:21 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 131 ; free virtual = 5271 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 139 ; free virtual = 2984 Phase 4 Critical Path Optimization -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.025 | TNS=-6240.800 | -INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][34]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-81] Processed net in_key[71]. Replicated 3 times. -INFO: [Physopt 32-735] Processed net in_key[71]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.023 | TNS=-6240.602 | -INFO: [Physopt 32-81] Processed net in_key[66]. Replicated 2 times. -INFO: [Physopt 32-735] Processed net in_key[66]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.021 | TNS=-6240.404 | -INFO: [Physopt 32-81] Processed net in_key[64]_repN. Replicated 1 times. -INFO: [Physopt 32-735] Processed net in_key[64]_repN. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.020 | TNS=-6240.008 | -INFO: [Physopt 32-702] Processed net storage_generate[0].storage/memory_rule[0][52]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-81] Processed net in_key[9]. Replicated 3 times. -INFO: [Physopt 32-735] Processed net in_key[9]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.020 | TNS=-6239.810 | -INFO: [Physopt 32-702] Processed net storage_generate[2].storage/memory_rule[2][124]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-81] Processed net in_key[0]. Replicated 5 times. -INFO: [Physopt 32-735] Processed net in_key[0]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.018 | TNS=-6239.316 | -INFO: [Physopt 32-663] Processed net in_key[72]. Re-placed instance registered_input.in_key_reg[72] -INFO: [Physopt 32-735] Processed net in_key[72]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.017 | TNS=-6238.820 | -INFO: [Physopt 32-702] Processed net in_key[2]_repN. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_3_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_4_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_24__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_26_n_6. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_29_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_60__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_98_n_7. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_106_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_101_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_109_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_95_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_103_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_104_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_190__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_350__0[5]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_262_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_264_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_282_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_283_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_27_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_30_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_33_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_93__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_110_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_238__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/minusOp10_out_0[20]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_258_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_259_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_256_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_322__0_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_810__0[5]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_580_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_579_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_573_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_575_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/final/memory_reg_0_i_99_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_276_0[3]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/O75[29]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_279_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_435_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/mix_stage[1][a][25]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_515_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_730_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][a][21]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_677_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1002_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-710] Processed net hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1002_n_0. Critical path length was reduced through logic transformation on cell hash_generate[1].hash/mix_pipeline[0].mix/memory_reg_0_i_1002_comp. -INFO: [Physopt 32-735] Processed net hash_generate[1].hash/mix_pipeline[0].mix/s[0][c]7_out[16]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.015 | TNS=-6237.929 | -INFO: [Physopt 32-81] Processed net in_key[65]. Replicated 1 times. -INFO: [Physopt 32-735] Processed net in_key[65]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.013 | TNS=-6237.732 | -INFO: [Physopt 32-663] Processed net in_key[78]. Re-placed instance registered_input.in_key_reg[78] -INFO: [Physopt 32-735] Processed net in_key[78]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.013 | TNS=-6237.533 | -INFO: [Physopt 32-663] Processed net in_key[13]. Re-placed instance registered_input.in_key_reg[13] -INFO: [Physopt 32-735] Processed net in_key[13]. Optimization improves timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.012 | TNS=-6236.939 | -INFO: [Physopt 32-702] Processed net storage_generate[3].storage/memory_rule[3][88]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net in_key[7]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_16__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_29_n_6. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_85__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_101_n_4. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_191__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_350__2[4]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_93__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/minusOp8_out[17]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_238__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/minusOp10_out_1[13]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_322__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/memory_reg_0_i_780__1[5]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_302_0[1]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/mix_stage[1][b][31]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_428_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_534_0[28]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_722_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/s[0][c]13_out[24]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_960[22]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_385__2_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_509_0[20]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_912_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/registered_input.in_key_reg[72]_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/minusOp12_out[17]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_858__1_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/minusOp14_out[13]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/mix_pipeline[0].mix/memory_reg_0_i_768__1_n_0. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/plusOp_inferred__0/i__carry__1_n_7. Optimizations did not improve timing on the net. -INFO: [Physopt 32-702] Processed net hash_generate[3].hash/final/O76[9]. Optimizations did not improve timing on the net. -INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-16.012 | TNS=-6236.939 | -Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 111 ; free virtual = 5273 -Phase 4 Critical Path Optimization | Checksum: 17af5ebfb +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.072 | TNS=-16.932 | +INFO: [Physopt 32-702] Processed net OUTPUT_KEY_FOUND. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][46]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/out_key_found13_out. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_6_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_15_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_29_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_44_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_59_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_74_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_89_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_reg_i_104_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_reg_0_16. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net OUTPUT_KEY_FOUND. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_rule[1][46]. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/out_key_found13_out. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/registered_output.OUTPUT_KEY_FOUND_i_122_n_0. Optimizations did not improve timing on the net. +INFO: [Physopt 32-702] Processed net storage_generate[1].storage/memory_reg_0_16. Optimizations did not improve timing on the net. +INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.072 | TNS=-16.932 | +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 139 ; free virtual = 2983 +Phase 4 Critical Path Optimization | Checksum: eda825fd -Time (s): cpu = 00:01:03 ; elapsed = 00:00:32 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 111 ; free virtual = 5273 -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 111 ; free virtual = 5274 -INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-16.012 | TNS=-6236.939 | +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 139 ; free virtual = 2983 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 139 ; free virtual = 2983 +INFO: [Physopt 32-603] Post Physical Optimization Timing Summary | WNS=-1.072 | TNS=-16.932 | Summary of Physical Synthesis Optimizations ============================================ @@ -862,30 +726,30 @@ Summary of Physical Synthesis Optimizations | Optimization | WNS Gain (ns) | TNS Gain (ns) | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ------------------------------------------------------------------------------------------------------------------------------------------------------------- | DSP Register | 0.000 | 0.000 | 0 | 0 | 0 | 0 | 1 | 00:00:00 | -| Critical Path | 0.150 | 32.769 | 34 | 0 | 35 | 0 | 2 | 00:00:31 | -| Total | 0.150 | 32.769 | 34 | 0 | 35 | 0 | 3 | 00:00:31 | +| Critical Path | 0.126 | 2.067 | 0 | 0 | 27 | 0 | 2 | 00:00:05 | +| Total | 0.126 | 2.067 | 0 | 0 | 27 | 0 | 3 | 00:00:05 | ------------------------------------------------------------------------------------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 111 ; free virtual = 5274 -Ending Physical Synthesis Task | Checksum: 27673438e +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 139 ; free virtual = 2983 +Ending Physical Synthesis Task | Checksum: a12a07e7 -Time (s): cpu = 00:01:03 ; elapsed = 00:00:32 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 110 ; free virtual = 5273 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 139 ; free virtual = 2983 INFO: [Common 17-83] Releasing license: Implementation -415 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. +276 Infos, 7 Warnings, 0 Critical Warnings and 0 Errors encountered. phys_opt_design completed successfully -phys_opt_design: Time (s): cpu = 00:01:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 110 ; free virtual = 5273 +phys_opt_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 139 ; free virtual = 2983 INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 109 ; free virtual = 5273 -Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.71 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 5257 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 5257 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 134 ; free virtual = 2984 +Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.73 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 120 ; free virtual = 2976 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 120 ; free virtual = 2976 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 5257 -Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 189 ; free virtual = 5257 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 188 ; free virtual = 5257 -Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.76 . Memory (MB): peak = 2836.203 ; gain = 0.000 ; free physical = 188 ; free virtual = 5257 +Wrote RouteStorage: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 120 ; free virtual = 2976 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 119 ; free virtual = 2977 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 119 ; free virtual = 2977 +Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.8 . Memory (MB): peak = 2842.672 ; gain = 0.000 ; free physical = 119 ; free virtual = 2977 INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_physopt.dcp' has been generated. Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t' @@ -903,133 +767,133 @@ Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs Phase 1 Build RT Design -Checksum: PlaceDB: a88baaee ConstDB: 0 ShapeSum: d8eec616 RouteDB: 0 +Checksum: PlaceDB: 578213a9 ConstDB: 0 ShapeSum: 2223e39e RouteDB: 0 WARNING: [Route 35-197] Clock port "CLK" does not have an associated HD.CLK_SRC. Without this constraint, timing analysis may not be accurate and upstream checks cannot be done to ensure correct clock placement. -WARNING: [Route 35-198] Port "CONFIG_KEY[117]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[117]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[120]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[120]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "RESET" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "RESET". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_VALID" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_VALID". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[102]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[102]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[98]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[98]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[100]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[100]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "CONFIG_KEY[94]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[94]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[32]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[32]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[28]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[28]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[106]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[106]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[107]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[107]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[104]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[104]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[113]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[113]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[108]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[108]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[105]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[105]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[124]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[124]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[125]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[125]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[126]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[126]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[127]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[127]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[120]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[120]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[121]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[121]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[122]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[122]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[123]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[123]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[116]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[116]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[118]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[118]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[117]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[117]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[119]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[119]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[112]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[112]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[114]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[114]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[91]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[91]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[115]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[115]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[96]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[96]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[101]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[101]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[93]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[93]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[99]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[99]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[92]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[92]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[103]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[103]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[63]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[63]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[127]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[127]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[95]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[95]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[97]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[97]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[118]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[118]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[112]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[112]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[122]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[122]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[120]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[120]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[124]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[124]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[60]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[60]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[31]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[31]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[30]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[30]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[57]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[57]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[52]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[52]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[94]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[94]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[62]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[62]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[61]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[61]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[56]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[56]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "CONFIG_KEY[116]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[116]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "CONFIG_KEY[114]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[114]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[108]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[108]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[102]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[102]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[100]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[100]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[98]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[98]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[96]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[96]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[30]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[30]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[86]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[86]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[84]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[84]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[122]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[122]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[118]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[118]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[106]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[106]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[70]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[70]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[121]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[121]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[103]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[103]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[57]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[57]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[35]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[35]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[66]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[66]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[60]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[60]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[33]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[33]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[25]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[25]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[119]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[119]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[111]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[111]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[104]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[104]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[125]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[125]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[64]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[64]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[105]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[105]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[90]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[90]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[89]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[89]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[124]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[124]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[110]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[110]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[76]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[76]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[34]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[34]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[50]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[50]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[20]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[20]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[88]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[88]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[44]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[44]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[48]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[48]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[72]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[72]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[54]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[54]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[21]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[21]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[46]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[46]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[42]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[42]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[91]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[91]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[36]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[36]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[26]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[26]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[24]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[24]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[113]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[113]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[82]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[82]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[22]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[22]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[40]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[40]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_DATA[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_DATA[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_DATA[13]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[13]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_DATA[12]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[12]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[77]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[77]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[62]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[62]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[52]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[52]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_DATA[8]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[8]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[69]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[69]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[47]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[47]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_WRITE" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_WRITE". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "RESET" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "RESET". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_ADDRESS_TABLE[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_TABLE[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_ADDRESS_TABLE[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_TABLE[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[78]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[78]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[75]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[75]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[74]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[74]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[68]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[68]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[123]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[123]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. WARNING: [Route 35-198] Port "CONFIG_KEY[126]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[126]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_DATA[14]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[14]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_DATA[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[53]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[53]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[73]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[73]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[16]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[16]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_DATA[1]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[1]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[43]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[43]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[41]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[41]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_DATA[11]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_DATA[11]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_EMPTY" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_EMPTY". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[38]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[38]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[19]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[19]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[37]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[37]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[97]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[97]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[29]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[29]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[10]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[10]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_ADDRESS_ITEM[4]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_ITEM[4]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_ADDRESS_ITEM[0]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_ITEM[0]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_ADDRESS_ITEM[9]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_ITEM[9]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[55]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[55]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_KEY[31]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[31]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. -WARNING: [Route 35-198] Port "CONFIG_ADDRESS_ITEM[2]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_ADDRESS_ITEM[2]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[125]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[125]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[59]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[59]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[58]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[58]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[121]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[121]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[110]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[110]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[119]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[119]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[117]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[117]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[109]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[109]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[55]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[55]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[95]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[95]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[29]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[29]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[28]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[28]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[27]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[27]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[53]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[53]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[88]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[88]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[93]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[93]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[91]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[91]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[108]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[108]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[109]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[109]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[110]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[110]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[111]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[111]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[104]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[104]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[105]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[105]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[106]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[106]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[107]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[107]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[115]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[115]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[113]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[113]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[111]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[111]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[70]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[70]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[68]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[68]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[60]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[60]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[58]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[58]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[66]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[66]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[64]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[64]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[86]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[86]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[72]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[72]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[69]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[69]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[65]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[65]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[62]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[62]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[92]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[92]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[89]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[89]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[87]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[87]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "CONFIG_KEY[71]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "CONFIG_KEY[71]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. +WARNING: [Route 35-198] Port "INPUT_KEY[100]" does not have an associated HD.PARTPIN_LOCS, which will prevent the partial routing of the signal "INPUT_KEY[100]". Without this partial route, timing analysis to/from this port will not be accurate, and no routing information for this port can be exported. INFO: [Common 17-14] Message 'Route 35-198' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. WARNING: [Constraints 18-8777] Unable to split tiles. All required files are not available. -Post Restoration Checksum: NetGraph: f5668f66 | NumContArr: ae2b9928 | Constraints: c2a8fa9d | Timing: c2a8fa9d -Phase 1 Build RT Design | Checksum: 328e41dc8 +Post Restoration Checksum: NetGraph: f8c3490f | NumContArr: f1ba4717 | Constraints: c2a8fa9d | Timing: c2a8fa9d +Phase 1 Build RT Design | Checksum: 36fcf8560 -Time (s): cpu = 00:00:52 ; elapsed = 00:00:35 . Memory (MB): peak = 2949.961 ; gain = 113.758 ; free physical = 97 ; free virtual = 5070 +Time (s): cpu = 00:00:54 ; elapsed = 00:00:37 . Memory (MB): peak = 2959.430 ; gain = 116.758 ; free physical = 110 ; free virtual = 2852 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 328e41dc8 +Phase 2.1 Fix Topology Constraints | Checksum: 36fcf8560 -Time (s): cpu = 00:00:52 ; elapsed = 00:00:36 . Memory (MB): peak = 2949.961 ; gain = 113.758 ; free physical = 117 ; free virtual = 5073 +Time (s): cpu = 00:00:54 ; elapsed = 00:00:37 . Memory (MB): peak = 2959.430 ; gain = 116.758 ; free physical = 110 ; free virtual = 2852 Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 328e41dc8 +Phase 2.2 Pre Route Cleanup | Checksum: 36fcf8560 -Time (s): cpu = 00:00:52 ; elapsed = 00:00:36 . Memory (MB): peak = 2949.961 ; gain = 113.758 ; free physical = 119 ; free virtual = 5075 +Time (s): cpu = 00:00:54 ; elapsed = 00:00:37 . Memory (MB): peak = 2959.430 ; gain = 116.758 ; free physical = 110 ; free virtual = 2852 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing -Phase 2.3 Update Timing | Checksum: 242e0954c +Phase 2.3 Update Timing | Checksum: 25dc24139 -Time (s): cpu = 00:00:58 ; elapsed = 00:00:38 . Memory (MB): peak = 2979.195 ; gain = 142.992 ; free physical = 163 ; free virtual = 5036 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=-15.599| TNS=-6066.110| WHS=0.033 | THS=0.000 | +Time (s): cpu = 00:01:02 ; elapsed = 00:00:41 . Memory (MB): peak = 2987.664 ; gain = 144.992 ; free physical = 151 ; free virtual = 2802 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.064 | TNS=-15.944| WHS=-0.016 | THS=-0.032 | Router Utilization Summary @@ -1038,155 +902,108 @@ Router Utilization Summary Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. - Number of Failed Nets = 5168 + Number of Failed Nets = 7074 (Failed Nets is the sum of unrouted and partially routed nets) - Number of Unrouted Nets = 5168 + Number of Unrouted Nets = 7074 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 2 Router Initialization | Checksum: 1d6088a45 +Phase 2 Router Initialization | Checksum: 20e1bf80c -Time (s): cpu = 00:01:01 ; elapsed = 00:00:40 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 151 ; free virtual = 5026 +Time (s): cpu = 00:01:07 ; elapsed = 00:00:42 . Memory (MB): peak = 2992.961 ; gain = 150.289 ; free physical = 145 ; free virtual = 2798 Phase 3 Initial Routing Phase 3.1 Global Routing -Phase 3.1 Global Routing | Checksum: 1d6088a45 +Phase 3.1 Global Routing | Checksum: 20e1bf80c -Time (s): cpu = 00:01:01 ; elapsed = 00:00:40 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 151 ; free virtual = 5026 +Time (s): cpu = 00:01:07 ; elapsed = 00:00:42 . Memory (MB): peak = 2992.961 ; gain = 150.289 ; free physical = 145 ; free virtual = 2798 Phase 3.2 Initial Net Routing -Phase 3.2 Initial Net Routing | Checksum: 2130f4a2f +Phase 3.2 Initial Net Routing | Checksum: 2312d3ca6 -Time (s): cpu = 00:01:32 ; elapsed = 00:00:51 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 231 ; free virtual = 5021 -Phase 3 Initial Routing | Checksum: 2130f4a2f +Time (s): cpu = 00:01:13 ; elapsed = 00:00:44 . Memory (MB): peak = 2992.961 ; gain = 150.289 ; free physical = 145 ; free virtual = 2797 +Phase 3 Initial Routing | Checksum: 2312d3ca6 -Time (s): cpu = 00:01:33 ; elapsed = 00:00:51 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 231 ; free virtual = 5021 +Time (s): cpu = 00:01:13 ; elapsed = 00:00:44 . Memory (MB): peak = 2992.961 ; gain = 150.289 ; free physical = 145 ; free virtual = 2797 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 4441 - Number of Nodes with overlaps = 1719 - Number of Nodes with overlaps = 1028 - Number of Nodes with overlaps = 514 - Number of Nodes with overlaps = 269 - Number of Nodes with overlaps = 127 - Number of Nodes with overlaps = 70 - Number of Nodes with overlaps = 32 - Number of Nodes with overlaps = 19 - Number of Nodes with overlaps = 5 - Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 206 + Number of Nodes with overlaps = 74 + Number of Nodes with overlaps = 9 + Number of Nodes with overlaps = 6 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.774| TNS=-6851.693| WHS=N/A | THS=N/A | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.252 | TNS=-31.493| WHS=N/A | THS=N/A | -Phase 4.1 Global Iteration 0 | Checksum: 225940652 +Phase 4.1 Global Iteration 0 | Checksum: 2cac37e0d -Time (s): cpu = 00:04:22 ; elapsed = 00:02:04 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 215 ; free virtual = 5156 +Time (s): cpu = 00:01:24 ; elapsed = 00:00:52 . Memory (MB): peak = 2992.961 ; gain = 150.289 ; free physical = 204 ; free virtual = 2786 Phase 4.2 Global Iteration 1 - Number of Nodes with overlaps = 231 - Number of Nodes with overlaps = 180 - Number of Nodes with overlaps = 152 - Number of Nodes with overlaps = 92 - Number of Nodes with overlaps = 84 - Number of Nodes with overlaps = 60 - Number of Nodes with overlaps = 44 - Number of Nodes with overlaps = 35 - Number of Nodes with overlaps = 37 - Number of Nodes with overlaps = 28 - Number of Nodes with overlaps = 20 - Number of Nodes with overlaps = 13 - Number of Nodes with overlaps = 9 - Number of Nodes with overlaps = 7 - Number of Nodes with overlaps = 5 - Number of Nodes with overlaps = 4 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.494| TNS=-6783.227| WHS=N/A | THS=N/A | - -Phase 4.2 Global Iteration 1 | Checksum: 2cd491a74 - -Time (s): cpu = 00:05:31 ; elapsed = 00:02:59 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 325 ; free virtual = 5054 - -Phase 4.3 Global Iteration 2 - Number of Nodes with overlaps = 141 - Number of Nodes with overlaps = 144 - Number of Nodes with overlaps = 120 - Number of Nodes with overlaps = 105 - Number of Nodes with overlaps = 121 - Number of Nodes with overlaps = 78 - Number of Nodes with overlaps = 57 - Number of Nodes with overlaps = 48 - Number of Nodes with overlaps = 27 + Number of Nodes with overlaps = 95 + Number of Nodes with overlaps = 43 Number of Nodes with overlaps = 17 - Number of Nodes with overlaps = 12 Number of Nodes with overlaps = 9 - Number of Nodes with overlaps = 10 - Number of Nodes with overlaps = 6 - Number of Nodes with overlaps = 4 - Number of Nodes with overlaps = 4 - Number of Nodes with overlaps = 3 - Number of Nodes with overlaps = 1 - Number of Nodes with overlaps = 1 - Number of Nodes with overlaps = 1 - Number of Nodes with overlaps = 1 - Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 5 + Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.465| TNS=-6794.564| WHS=N/A | THS=N/A | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.255 | TNS=-31.100| WHS=N/A | THS=N/A | -Phase 4.3 Global Iteration 2 | Checksum: 18900c83b +Phase 4.2 Global Iteration 1 | Checksum: 2687e85da -Time (s): cpu = 00:06:35 ; elapsed = 00:03:45 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 242 ; free virtual = 5028 -Phase 4 Rip-up And Reroute | Checksum: 18900c83b +Time (s): cpu = 00:01:33 ; elapsed = 00:00:58 . Memory (MB): peak = 2992.961 ; gain = 150.289 ; free physical = 199 ; free virtual = 2783 +Phase 4 Rip-up And Reroute | Checksum: 2687e85da -Time (s): cpu = 00:06:35 ; elapsed = 00:03:45 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 242 ; free virtual = 5028 +Time (s): cpu = 00:01:33 ; elapsed = 00:00:59 . Memory (MB): peak = 2992.961 ; gain = 150.289 ; free physical = 199 ; free virtual = 2783 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1.1 Update Timing -Phase 5.1.1 Update Timing | Checksum: 18900c83b +Phase 5.1.1 Update Timing | Checksum: 2fe6ca81b -Time (s): cpu = 00:06:36 ; elapsed = 00:03:45 . Memory (MB): peak = 2981.844 ; gain = 145.641 ; free physical = 183 ; free virtual = 5022 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.465| TNS=-6794.564| WHS=N/A | THS=N/A | +Time (s): cpu = 00:01:34 ; elapsed = 00:00:59 . Memory (MB): peak = 2992.961 ; gain = 150.289 ; free physical = 199 ; free virtual = 2783 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.252 | TNS=-31.493| WHS=N/A | THS=N/A | Number of Nodes with overlaps = 0 -Phase 5.1 Delay CleanUp | Checksum: 1a7ad13b4 +Phase 5.1 Delay CleanUp | Checksum: 187ef8df4 -Time (s): cpu = 00:06:47 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 142 ; free virtual = 5020 +Time (s): cpu = 00:03:37 ; elapsed = 00:01:35 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 136 ; free virtual = 2607 Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 1a7ad13b4 +Phase 5.2 Clock Skew Optimization | Checksum: 187ef8df4 -Time (s): cpu = 00:06:47 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 142 ; free virtual = 5020 -Phase 5 Delay and Skew Optimization | Checksum: 1a7ad13b4 +Time (s): cpu = 00:03:37 ; elapsed = 00:01:35 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 136 ; free virtual = 2607 +Phase 5 Delay and Skew Optimization | Checksum: 187ef8df4 -Time (s): cpu = 00:06:47 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 142 ; free virtual = 5020 +Time (s): cpu = 00:03:37 ; elapsed = 00:01:35 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 136 ; free virtual = 2607 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 1e57763e0 +Phase 6.1.1 Update Timing | Checksum: 1ec99cbab -Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 141 ; free virtual = 5020 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=-17.396| TNS=-6762.388| WHS=0.081 | THS=0.000 | +Time (s): cpu = 00:03:38 ; elapsed = 00:01:36 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 136 ; free virtual = 2608 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=-1.240 | TNS=-22.556| WHS=0.038 | THS=0.000 | -Phase 6.1 Hold Fix Iter | Checksum: 1e57763e0 +Phase 6.1 Hold Fix Iter | Checksum: 23943ec6b -Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 141 ; free virtual = 5020 -Phase 6 Post Hold Fix | Checksum: 1e57763e0 +Time (s): cpu = 00:03:38 ; elapsed = 00:01:36 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 136 ; free virtual = 2608 +Phase 6 Post Hold Fix | Checksum: 23943ec6b -Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 141 ; free virtual = 5020 +Time (s): cpu = 00:03:38 ; elapsed = 00:01:36 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 136 ; free virtual = 2608 Phase 7 Route finalize Router Utilization Summary - Global Vertical Routing Utilization = 1.77316 % - Global Horizontal Routing Utilization = 2.02251 % + Global Vertical Routing Utilization = 0.939418 % + Global Horizontal Routing Utilization = 1.24595 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. @@ -1200,16 +1017,10 @@ Router Utilization Summary --GLOBAL Congestion: Utilization threshold used for congestion level computation: 0.85 Congestion Report -North Dir 1x1 Area, Max Cong = 67.5676%, No Congested Regions. -South Dir 1x1 Area, Max Cong = 80.1802%, No Congested Regions. -East Dir 2x2 Area, Max Cong = 91.5441%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): - INT_L_X32Y168 -> INT_R_X33Y169 -West Dir 1x1 Area, Max Cong = 94.1176%, Congestion bounded by tiles (Lower Left Tile -> Upper Right Tile): - INT_L_X28Y189 -> INT_L_X28Y189 - INT_L_X26Y188 -> INT_L_X26Y188 - INT_R_X27Y188 -> INT_R_X27Y188 - INT_L_X28Y187 -> INT_L_X28Y187 - INT_L_X14Y172 -> INT_L_X14Y172 +North Dir 1x1 Area, Max Cong = 50.4505%, No Congested Regions. +South Dir 1x1 Area, Max Cong = 60.3604%, No Congested Regions. +East Dir 1x1 Area, Max Cong = 63.2353%, No Congested Regions. +West Dir 1x1 Area, Max Cong = 52.9412%, No Congested Regions. ------------------------------ Reporting congestion hotspots @@ -1224,52 +1035,52 @@ Congested clusters found at Level 0 Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: East ---------------- -Congested clusters found at Level 1 -Effective congestion level: 2 Aspect Ratio: 0.5 Sparse Ratio: 0.5 +Congested clusters found at Level 0 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 Direction: West ---------------- Congested clusters found at Level 0 -Effective congestion level: 1 Aspect Ratio: 0.5 Sparse Ratio: 0.5 +Effective congestion level: 0 Aspect Ratio: 1 Sparse Ratio: 0 -Phase 7 Route finalize | Checksum: 1e57763e0 +Phase 7 Route finalize | Checksum: 23943ec6b -Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 133 ; free virtual = 5020 +Time (s): cpu = 00:03:38 ; elapsed = 00:01:36 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 136 ; free virtual = 2607 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 1e57763e0 +Phase 8 Verifying routed nets | Checksum: 23943ec6b -Time (s): cpu = 00:06:48 ; elapsed = 00:03:49 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 128 ; free virtual = 5019 +Time (s): cpu = 00:03:38 ; elapsed = 00:01:36 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 136 ; free virtual = 2607 Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 26293a506 +Phase 9 Depositing Routes | Checksum: 1ef2bc857 -Time (s): cpu = 00:06:50 ; elapsed = 00:03:50 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 243 ; free virtual = 5043 +Time (s): cpu = 00:03:39 ; elapsed = 00:01:37 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 128 ; free virtual = 2600 Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=-17.396| TNS=-6762.388| WHS=0.081 | THS=0.000 | +INFO: [Route 35-57] Estimated Timing Summary | WNS=-1.240 | TNS=-22.556| WHS=0.038 | THS=0.000 | WARNING: [Route 35-328] Router estimated timing not met. Resolution: For a complete and accurate timing signoff, report_timing_summary must be run after route_design. Alternatively, route_design can be run with the -timing_summary option to enable a complete timing signoff at the end of route_design. -Phase 10 Post Router Timing | Checksum: 26293a506 +Phase 10 Post Router Timing | Checksum: 1ef2bc857 -Time (s): cpu = 00:06:51 ; elapsed = 00:03:51 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 224 ; free virtual = 5039 +Time (s): cpu = 00:03:41 ; elapsed = 00:01:37 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 127 ; free virtual = 2599 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing -Phase 11 Post-Route Event Processing | Checksum: 123c431d6 +Phase 11 Post-Route Event Processing | Checksum: 105362d16 -Time (s): cpu = 00:06:51 ; elapsed = 00:03:51 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 193 ; free virtual = 5030 -Ending Routing Task | Checksum: 123c431d6 +Time (s): cpu = 00:03:41 ; elapsed = 00:01:38 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 125 ; free virtual = 2599 +Ending Routing Task | Checksum: 105362d16 -Time (s): cpu = 00:06:51 ; elapsed = 00:03:51 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 193 ; free virtual = 5030 +Time (s): cpu = 00:03:41 ; elapsed = 00:01:38 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 125 ; free virtual = 2599 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation -435 Infos, 109 Warnings, 0 Critical Warnings and 0 Errors encountered. +295 Infos, 110 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:06:55 ; elapsed = 00:03:53 . Memory (MB): peak = 2987.844 ; gain = 151.641 ; free physical = 137 ; free virtual = 5047 +route_design: Time (s): cpu = 00:03:46 ; elapsed = 00:01:40 . Memory (MB): peak = 3153.961 ; gain = 311.289 ; free physical = 109 ; free virtual = 2596 INFO: [runtcl-4] Executing : report_drc -file filter_drc_routed.rpt -pb filter_drc_routed.pb -rpx filter_drc_routed.rpx Command: report_drc -file filter_drc_routed.rpt -pb filter_drc_routed.pb -rpx filter_drc_routed.rpx INFO: [IP_Flow 19-1839] IP Catalog is up to date. @@ -1285,6 +1096,7 @@ Resolution: Set the HD.CLK_SRC property of the out-of-context port to the locati INFO: [DRC 23-133] Running Methodology with 4 threads INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_methodology_drc_routed.rpt. report_methodology completed successfully +report_methodology: Time (s): cpu = 00:00:12 ; elapsed = 00:00:05 . Memory (MB): peak = 3209.988 ; gain = 0.000 ; free physical = 197 ; free virtual = 2603 INFO: [runtcl-4] Executing : report_power -file filter_power_routed.rpt -pb filter_power_summary_routed.pb -rpx filter_power_routed.rpx Command: report_power -file filter_power_routed.rpt -pb filter_power_summary_routed.pb -rpx filter_power_routed.rpx WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] @@ -1292,7 +1104,7 @@ INFO: [Timing 38-35] Done setting XDC timing constraints. Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation -445 Infos, 112 Warnings, 0 Critical Warnings and 0 Errors encountered. +305 Infos, 113 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully INFO: [runtcl-4] Executing : report_route_status -file filter_route_status.rpt -pb filter_route_status.pb INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_routed.rpt -pb filter_timing_summary_routed.pb -rpx filter_timing_summary_routed.rpx -warn_on_violation @@ -1306,15 +1118,15 @@ INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file filter_bus INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs INFO: [Timing 38-480] Writing timing data to binary archive. -Write ShapeDB Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 154 ; free virtual = 4924 -Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.94 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 198 ; free virtual = 4894 -Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 199 ; free virtual = 4893 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3209.988 ; gain = 0.000 ; free physical = 129 ; free virtual = 2580 +Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.77 . Memory (MB): peak = 3209.988 ; gain = 0.000 ; free physical = 119 ; free virtual = 2577 +Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3209.988 ; gain = 0.000 ; free physical = 119 ; free virtual = 2577 Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Wrote RouteStorage: Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.36 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 183 ; free virtual = 4881 -Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 183 ; free virtual = 4881 -Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 182 ; free virtual = 4881 -Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 3043.871 ; gain = 0.000 ; free physical = 182 ; free virtual = 4881 +Wrote RouteStorage: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.16 . Memory (MB): peak = 3209.988 ; gain = 0.000 ; free physical = 118 ; free virtual = 2577 +Wrote Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 3209.988 ; gain = 0.000 ; free physical = 117 ; free virtual = 2577 +Wrote Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3209.988 ; gain = 0.000 ; free physical = 117 ; free virtual = 2577 +Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.96 . Memory (MB): peak = 3209.988 ; gain = 0.000 ; free physical = 117 ; free virtual = 2577 INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_routed.dcp' has been generated. -INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 18:58:43 2023... +INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 21:20:46 2023... diff --git a/synth/filter_vivado.runs/impl_1/vivado.jou b/synth/filter_vivado.runs/impl_1/vivado.jou index 2175164..b3a6b8f 100644 --- a/synth/filter_vivado.runs/impl_1/vivado.jou +++ b/synth/filter_vivado.runs/impl_1/vivado.jou @@ -3,12 +3,12 @@ # SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Sun Dec 3 18:51:36 2023 -# Process ID: 19329 +# Start of session at: Sun Dec 3 21:16:13 2023 +# Process ID: 50397 # Current directory: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1 # Command line: vivado -log filter.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source filter.tcl -notrace # Log file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter.vdi # Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/vivado.jou -# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2785.745 MHz, CPU Physical cores: 4, Host memory: 3903 MB +# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2785.806 MHz, CPU Physical cores: 4, Host memory: 3903 MB #----------------------------------------------------------- source filter.tcl -notrace diff --git a/synth/filter_vivado.runs/impl_1/vivado.pb b/synth/filter_vivado.runs/impl_1/vivado.pb index 00486df..26318fe 100644 Binary files a/synth/filter_vivado.runs/impl_1/vivado.pb and b/synth/filter_vivado.runs/impl_1/vivado.pb differ diff --git a/synth/filter_vivado.runs/synth_1/.vivado.begin.rst b/synth/filter_vivado.runs/synth_1/.vivado.begin.rst index a9ba09a..9cc8a7c 100644 --- a/synth/filter_vivado.runs/synth_1/.vivado.begin.rst +++ b/synth/filter_vivado.runs/synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/synth/filter_vivado.runs/synth_1/filter.dcp b/synth/filter_vivado.runs/synth_1/filter.dcp index e647b6e..209b7a6 100644 Binary files a/synth/filter_vivado.runs/synth_1/filter.dcp and b/synth/filter_vivado.runs/synth_1/filter.dcp differ diff --git a/synth/filter_vivado.runs/synth_1/filter.tcl b/synth/filter_vivado.runs/synth_1/filter.tcl index c31b414..e0d9766 100644 --- a/synth/filter_vivado.runs/synth_1/filter.tcl +++ b/synth/filter_vivado.runs/synth_1/filter.tcl @@ -70,6 +70,7 @@ proc create_report { reportName command } { } } OPTRACE "synth_1" START { ROLLUP_AUTO } +set_param chipscope.maxJobs 1 OPTRACE "Creating in-memory project" START { } create_project -in_memory -part xc7k160tffv676-1 diff --git a/synth/filter_vivado.runs/synth_1/filter.vds b/synth/filter_vivado.runs/synth_1/filter.vds index e06791e..ca06fbd 100644 --- a/synth/filter_vivado.runs/synth_1/filter.vds +++ b/synth/filter_vivado.runs/synth_1/filter.vds @@ -3,16 +3,16 @@ # SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Sun Dec 3 18:47:59 2023 -# Process ID: 18749 +# Start of session at: Sun Dec 3 21:14:16 2023 +# Process ID: 50094 # Current directory: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1 # Command line: vivado -log filter.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source filter.tcl # Log file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/filter.vds # Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/vivado.jou -# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 3075.336 MHz, CPU Physical cores: 4, Host memory: 3903 MB +# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2783.625 MHz, CPU Physical cores: 4, Host memory: 3903 MB #----------------------------------------------------------- source filter.tcl -notrace -create_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1275.312 ; gain = 39.836 ; free physical = 248 ; free virtual = 8095 +create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1291.613 ; gain = 39.836 ; free physical = 147 ; free virtual = 4464 Command: synth_design -top filter -part xc7k160tffv676-1 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t' @@ -20,9 +20,9 @@ INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160 INFO: [Device 21-403] Loading part xc7k160tffv676-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 18803 +INFO: [Synth 8-7075] Helper process launched with PID 50143 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2039.840 ; gain = 404.684 ; free physical = 155 ; free virtual = 6867 +Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2055.203 ; gain = 403.746 ; free physical = 123 ; free virtual = 3529 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'filter' [/home/veronikaplevacova/Plocha/PCS2/filter.vhd:17] INFO: [Synth 8-638] synthesizing module 'jenkins_hash' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] @@ -53,23 +53,21 @@ INFO: [Synth 8-638] synthesizing module 'block_memory' [/home/veronikaplevacova/ Parameter OUTPUT_REGISTER bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'block_memory' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:45] INFO: [Synth 8-256] done synthesizing module 'filter' (0#1) [/home/veronikaplevacova/Plocha/PCS2/filter.vhd:17] -WARNING: [Synth 8-7129] Port CLK in module jenkins_final is either unconnected or has no load WARNING: [Synth 8-7129] Port RESET in module jenkins_final is either unconnected or has no load -WARNING: [Synth 8-7129] Port CLK in module jenkins_mix is either unconnected or has no load WARNING: [Synth 8-7129] Port RESET in module jenkins_mix is either unconnected or has no load --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2119.777 ; gain = 484.621 ; free physical = 119 ; free virtual = 6746 +Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2138.141 ; gain = 486.684 ; free physical = 152 ; free virtual = 3299 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2137.590 ; gain = 502.434 ; free physical = 119 ; free virtual = 6727 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2155.953 ; gain = 504.496 ; free physical = 133 ; free virtual = 3292 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2137.590 ; gain = 502.434 ; free physical = 119 ; free virtual = 6727 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2155.953 ; gain = 504.496 ; free physical = 133 ; free virtual = 3292 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2137.590 ; gain = 0.000 ; free physical = 94 ; free virtual = 6678 +Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2155.953 ; gain = 0.000 ; free physical = 129 ; free virtual = 3282 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints @@ -79,47 +77,47 @@ WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2252.324 ; gain = 0.000 ; free physical = 115 ; free virtual = 6314 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2269.719 ; gain = 0.000 ; free physical = 117 ; free virtual = 3243 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.93 . Memory (MB): peak = 2252.359 ; gain = 0.000 ; free physical = 108 ; free virtual = 6278 +Constraint Validation Runtime : Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2269.754 ; gain = 0.000 ; free physical = 131 ; free virtual = 3246 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 106 ; free virtual = 5475 +Finished Constraint Validation : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 185 ; free virtual = 3230 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k160tffv676-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 162 ; free virtual = 5460 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 185 ; free virtual = 3230 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 125 ; free virtual = 5450 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 185 ; free virtual = 3231 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 120 ; free virtual = 5337 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 180 ; free virtual = 3229 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : + 2 Input 32 Bit Adders := 40 3 Input 32 Bit Adders := 52 - 4 Input 32 Bit Adders := 8 - 2 Input 32 Bit Adders := 24 +---XORs : 2 Input 32 Bit XORs := 52 +---Registers : 145 Bit Registers := 5 - 128 Bit Registers := 3 + 128 Bit Registers := 55 + 32 Bit Registers := 156 16 Bit Registers := 1 11 Bit Registers := 1 2 Bit Registers := 1 - 1 Bit Registers := 8 + 1 Bit Registers := 60 +---RAMs : 290K Bit (2048 X 145 bit) RAMs := 4 +---Muxes : @@ -141,12 +139,10 @@ Finished Part Resource Summary Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met -WARNING: [Synth 8-7129] Port CLK in module jenkins_final is either unconnected or has no load WARNING: [Synth 8-7129] Port RESET in module jenkins_final is either unconnected or has no load -WARNING: [Synth 8-7129] Port CLK in module jenkins_mix is either unconnected or has no load WARNING: [Synth 8-7129] Port RESET in module jenkins_mix is either unconnected or has no load --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:47 ; elapsed = 00:00:59 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 131 ; free virtual = 5310 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 178 ; free virtual = 3189 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting @@ -170,13 +166,13 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:56 ; elapsed = 00:01:09 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 175 ; free virtual = 5367 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 121 ; free virtual = 3182 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:01:03 ; elapsed = 00:01:17 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 243 ; free virtual = 5327 +Finished Timing Optimization : Time (s): cpu = 00:00:48 ; elapsed = 00:00:50 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 193 ; free virtual = 3161 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting @@ -235,7 +231,7 @@ INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/mem INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:01:07 ; elapsed = 00:01:21 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 381 ; free virtual = 5319 +Finished Technology Mapping : Time (s): cpu = 00:00:52 ; elapsed = 00:00:55 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 184 ; free virtual = 3158 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -253,37 +249,55 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:01:16 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +Finished IO Insertion : Time (s): cpu = 00:01:01 ; elapsed = 00:01:04 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:01:16 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +Finished Renaming Generated Instances : Time (s): cpu = 00:01:01 ; elapsed = 00:01:04 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:17 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:02 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:01:17 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +Finished Renaming Generated Ports : Time (s): cpu = 00:01:02 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:01:17 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +Finished Handling Custom Attributes : Time (s): cpu = 00:01:03 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:01:17 ; elapsed = 00:01:34 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +Finished Renaming Generated Nets : Time (s): cpu = 00:01:03 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++------------+--------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++------------+--------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|filter | hash_generate[0].hash/final/s_reg[7][valid] | 13 | 1 | NO | NO | NO | 1 | 0 | +|filter | memory_key_reg[127] | 8 | 32 | NO | NO | YES | 32 | 0 | +|filter | memory_key_reg[95] | 14 | 89 | NO | NO | YES | 89 | 0 | +|filter | memory_key_reg[38] | 13 | 7 | NO | NO | YES | 7 | 0 | +|filter | hash_generate[0].hash/mix_pipeline[0].mix/s_reg[6][key][100] | 7 | 32 | NO | YES | YES | 32 | 0 | ++------------+--------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -299,41 +313,41 @@ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ -|1 |CARRY4 | 681| -|2 |LUT1 | 228| -|3 |LUT2 | 874| -|4 |LUT3 | 900| -|5 |LUT4 | 260| -|6 |LUT5 | 995| -|7 |LUT6 | 950| -|8 |RAMB18E1 | 4| -|9 |RAMB36E1 | 32| -|10 |FDRE | 563| +|1 |CARRY4 | 745| +|2 |LUT1 | 227| +|3 |LUT2 | 3166| +|4 |LUT3 | 764| +|5 |LUT4 | 4| +|6 |LUT6 | 201| +|7 |RAMB18E1 | 4| +|8 |RAMB36E1 | 32| +|9 |SRL16E | 161| +|10 |FDRE | 4794| +------+---------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:01:17 ; elapsed = 00:01:34 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 164 ; free virtual = 5187 +Finished Writing Synthesis Report : Time (s): cpu = 00:01:03 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 5 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:01:11 ; elapsed = 00:01:26 . Memory (MB): peak = 2252.359 ; gain = 502.434 ; free physical = 148 ; free virtual = 5185 -Synthesis Optimization Complete : Time (s): cpu = 00:01:17 ; elapsed = 00:01:34 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 145 ; free virtual = 5184 +Synthesis finished with 0 errors, 0 critical warnings and 3 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:57 ; elapsed = 00:01:00 . Memory (MB): peak = 2269.754 ; gain = 504.496 ; free physical = 134 ; free virtual = 3152 +Synthesis Optimization Complete : Time (s): cpu = 00:01:03 ; elapsed = 00:01:06 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 134 ; free virtual = 3152 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2252.359 ; gain = 0.000 ; free physical = 115 ; free virtual = 5167 -INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement +Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2269.754 ; gain = 0.000 ; free physical = 384 ; free virtual = 3430 +INFO: [Netlist 29-17] Analyzing 781 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2252.359 ; gain = 0.000 ; free physical = 313 ; free virtual = 5535 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2269.754 ; gain = 0.000 ; free physical = 311 ; free virtual = 3423 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Synth Design complete | Checksum: d74e1ad3 +Synth Design complete | Checksum: 806ce973 INFO: [Common 17-83] Releasing license: Synthesis -66 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. +66 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:01:33 ; elapsed = 00:01:44 . Memory (MB): peak = 2252.359 ; gain = 977.047 ; free physical = 232 ; free virtual = 5481 -INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1724.537; main = 1326.676; forked = 397.861 -INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3235.051; main = 2252.328; forked = 982.723 -Write ShapeDB Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2276.336 ; gain = 0.000 ; free physical = 226 ; free virtual = 5482 +synth_design: Time (s): cpu = 00:01:18 ; elapsed = 00:01:16 . Memory (MB): peak = 2269.754 ; gain = 978.141 ; free physical = 301 ; free virtual = 3421 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1616.477; main = 1400.213; forked = 417.991 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3233.605; main = 2269.723; forked = 963.883 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2269.754 ; gain = 0.000 ; free physical = 297 ; free virtual = 3420 INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/filter.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file filter_utilization_synth.rpt -pb filter_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 18:50:06 2023... +INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 21:15:58 2023... diff --git a/synth/filter_vivado.runs/synth_1/filter_utilization_synth.pb b/synth/filter_vivado.runs/synth_1/filter_utilization_synth.pb index c2b972b..019656e 100644 Binary files a/synth/filter_vivado.runs/synth_1/filter_utilization_synth.pb and b/synth/filter_vivado.runs/synth_1/filter_utilization_synth.pb differ diff --git a/synth/filter_vivado.runs/synth_1/filter_utilization_synth.rpt b/synth/filter_vivado.runs/synth_1/filter_utilization_synth.rpt index 7bfe611..119a4ba 100644 --- a/synth/filter_vivado.runs/synth_1/filter_utilization_synth.rpt +++ b/synth/filter_vivado.runs/synth_1/filter_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023 -| Date : Sun Dec 3 18:50:06 2023 +| Date : Sun Dec 3 21:15:58 2023 | Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux | Command : report_utilization -file filter_utilization_synth.rpt -pb filter_utilization_synth.pb | Design : filter @@ -28,18 +28,20 @@ Table of Contents 1. Slice Logic -------------- -+-------------------------+------+-------+------------+-----------+-------+ -| Site Type | Used | Fixed | Prohibited | Available | Util% | -+-------------------------+------+-------+------------+-----------+-------+ -| Slice LUTs* | 3498 | 0 | 0 | 101400 | 3.45 | -| LUT as Logic | 3498 | 0 | 0 | 101400 | 3.45 | -| LUT as Memory | 0 | 0 | 0 | 35000 | 0.00 | -| Slice Registers | 563 | 0 | 0 | 202800 | 0.28 | -| Register as Flip Flop | 563 | 0 | 0 | 202800 | 0.28 | -| Register as Latch | 0 | 0 | 0 | 202800 | 0.00 | -| F7 Muxes | 0 | 0 | 0 | 50700 | 0.00 | -| F8 Muxes | 0 | 0 | 0 | 25350 | 0.00 | -+-------------------------+------+-------+------------+-----------+-------+ ++----------------------------+------+-------+------------+-----------+-------+ +| Site Type | Used | Fixed | Prohibited | Available | Util% | ++----------------------------+------+-------+------------+-----------+-------+ +| Slice LUTs* | 3787 | 0 | 0 | 101400 | 3.73 | +| LUT as Logic | 3626 | 0 | 0 | 101400 | 3.58 | +| LUT as Memory | 161 | 0 | 0 | 35000 | 0.46 | +| LUT as Distributed RAM | 0 | 0 | | | | +| LUT as Shift Register | 161 | 0 | | | | +| Slice Registers | 4794 | 0 | 0 | 202800 | 2.36 | +| Register as Flip Flop | 4794 | 0 | 0 | 202800 | 2.36 | +| Register as Latch | 0 | 0 | 0 | 202800 | 0.00 | +| F7 Muxes | 0 | 0 | 0 | 50700 | 0.00 | +| F8 Muxes | 0 | 0 | 0 | 25350 | 0.00 | ++----------------------------+------+-------+------------+-----------+-------+ * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count. Warning! LUT value is adjusted to account for LUT combining. @@ -59,7 +61,7 @@ Warning! LUT value is adjusted to account for LUT combining. | 0 | Yes | - | Set | | 0 | Yes | - | Reset | | 0 | Yes | Set | - | -| 563 | Yes | Reset | - | +| 4794 | Yes | Reset | - | +-------+--------------+-------------+--------------+ @@ -155,16 +157,16 @@ Warning! LUT value is adjusted to account for LUT combining. +----------+------+---------------------+ | Ref Name | Used | Functional Category | +----------+------+---------------------+ -| LUT5 | 995 | LUT | -| LUT6 | 950 | LUT | -| LUT3 | 900 | LUT | -| LUT2 | 874 | LUT | -| CARRY4 | 681 | CarryLogic | -| FDRE | 563 | Flop & Latch | -| LUT4 | 260 | LUT | -| LUT1 | 228 | LUT | +| FDRE | 4794 | Flop & Latch | +| LUT2 | 3166 | LUT | +| LUT3 | 764 | LUT | +| CARRY4 | 745 | CarryLogic | +| LUT1 | 227 | LUT | +| LUT6 | 201 | LUT | +| SRL16E | 161 | Distributed Memory | | RAMB36E1 | 32 | Block Memory | | RAMB18E1 | 4 | Block Memory | +| LUT4 | 4 | LUT | +----------+------+---------------------+ diff --git a/synth/filter_vivado.runs/synth_1/gen_run.xml b/synth/filter_vivado.runs/synth_1/gen_run.xml index 69c862f..f54d1c7 100644 --- a/synth/filter_vivado.runs/synth_1/gen_run.xml +++ b/synth/filter_vivado.runs/synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + diff --git a/synth/filter_vivado.runs/synth_1/project.wdf b/synth/filter_vivado.runs/synth_1/project.wdf deleted file mode 100644 index ca8c64f..0000000 --- a/synth/filter_vivado.runs/synth_1/project.wdf +++ /dev/null @@ -1,31 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00 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-70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00 -5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3566643632386632633138353432663961623136653661643866623536373363:506172656e742050412070726f6a656374204944:00 -eof:3523505476 diff --git a/synth/filter_vivado.runs/synth_1/runme.log b/synth/filter_vivado.runs/synth_1/runme.log index 6b937f1..d806b18 100644 --- a/synth/filter_vivado.runs/synth_1/runme.log +++ b/synth/filter_vivado.runs/synth_1/runme.log @@ -11,7 +11,7 @@ ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source filter.tcl -notrace -create_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1275.312 ; gain = 39.836 ; free physical = 248 ; free virtual = 8095 +create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1291.613 ; gain = 39.836 ; free physical = 147 ; free virtual = 4464 Command: synth_design -top filter -part xc7k160tffv676-1 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7k160t' @@ -19,9 +19,9 @@ INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k160 INFO: [Device 21-403] Loading part xc7k160tffv676-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes -INFO: [Synth 8-7075] Helper process launched with PID 18803 +INFO: [Synth 8-7075] Helper process launched with PID 50143 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 2039.840 ; gain = 404.684 ; free physical = 155 ; free virtual = 6867 +Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 2055.203 ; gain = 403.746 ; free physical = 123 ; free virtual = 3529 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'filter' [/home/veronikaplevacova/Plocha/PCS2/filter.vhd:17] INFO: [Synth 8-638] synthesizing module 'jenkins_hash' [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:40] @@ -52,23 +52,21 @@ INFO: [Synth 8-638] synthesizing module 'block_memory' [/home/veronikaplevacova/ Parameter OUTPUT_REGISTER bound to: 0 - type: bool INFO: [Synth 8-256] done synthesizing module 'block_memory' (0#1) [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:45] INFO: [Synth 8-256] done synthesizing module 'filter' (0#1) [/home/veronikaplevacova/Plocha/PCS2/filter.vhd:17] -WARNING: [Synth 8-7129] Port CLK in module jenkins_final is either unconnected or has no load WARNING: [Synth 8-7129] Port RESET in module jenkins_final is either unconnected or has no load -WARNING: [Synth 8-7129] Port CLK in module jenkins_mix is either unconnected or has no load WARNING: [Synth 8-7129] Port RESET in module jenkins_mix is either unconnected or has no load --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:13 ; elapsed = 00:00:15 . Memory (MB): peak = 2119.777 ; gain = 484.621 ; free physical = 119 ; free virtual = 6746 +Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2138.141 ; gain = 486.684 ; free physical = 152 ; free virtual = 3299 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2137.590 ; gain = 502.434 ; free physical = 119 ; free virtual = 6727 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2155.953 ; gain = 504.496 ; free physical = 133 ; free virtual = 3292 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2137.590 ; gain = 502.434 ; free physical = 119 ; free virtual = 6727 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:14 . Memory (MB): peak = 2155.953 ; gain = 504.496 ; free physical = 133 ; free virtual = 3292 --------------------------------------------------------------------------------- -Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2137.590 ; gain = 0.000 ; free physical = 94 ; free virtual = 6678 +Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2155.953 ; gain = 0.000 ; free physical = 129 ; free virtual = 3282 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints @@ -78,47 +76,47 @@ WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] Completed Processing XDC Constraints -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2252.324 ; gain = 0.000 ; free physical = 115 ; free virtual = 6314 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2269.719 ; gain = 0.000 ; free physical = 117 ; free virtual = 3243 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.93 . Memory (MB): peak = 2252.359 ; gain = 0.000 ; free physical = 108 ; free virtual = 6278 +Constraint Validation Runtime : Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.29 . Memory (MB): peak = 2269.754 ; gain = 0.000 ; free physical = 131 ; free virtual = 3246 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 106 ; free virtual = 5475 +Finished Constraint Validation : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 185 ; free virtual = 3230 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7k160tffv676-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 162 ; free virtual = 5460 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 185 ; free virtual = 3230 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:32 ; elapsed = 00:00:40 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 125 ; free virtual = 5450 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 185 ; free virtual = 3231 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:33 ; elapsed = 00:00:42 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 120 ; free virtual = 5337 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:27 ; elapsed = 00:00:29 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 180 ; free virtual = 3229 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : + 2 Input 32 Bit Adders := 40 3 Input 32 Bit Adders := 52 - 4 Input 32 Bit Adders := 8 - 2 Input 32 Bit Adders := 24 +---XORs : 2 Input 32 Bit XORs := 52 +---Registers : 145 Bit Registers := 5 - 128 Bit Registers := 3 + 128 Bit Registers := 55 + 32 Bit Registers := 156 16 Bit Registers := 1 11 Bit Registers := 1 2 Bit Registers := 1 - 1 Bit Registers := 8 + 1 Bit Registers := 60 +---RAMs : 290K Bit (2048 X 145 bit) RAMs := 4 +---Muxes : @@ -140,12 +138,10 @@ Finished Part Resource Summary Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met -WARNING: [Synth 8-7129] Port CLK in module jenkins_final is either unconnected or has no load WARNING: [Synth 8-7129] Port RESET in module jenkins_final is either unconnected or has no load -WARNING: [Synth 8-7129] Port CLK in module jenkins_mix is either unconnected or has no load WARNING: [Synth 8-7129] Port RESET in module jenkins_mix is either unconnected or has no load --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:47 ; elapsed = 00:00:59 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 131 ; free virtual = 5310 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 178 ; free virtual = 3189 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting @@ -169,13 +165,13 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:56 ; elapsed = 00:01:09 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 175 ; free virtual = 5367 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 121 ; free virtual = 3182 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:01:03 ; elapsed = 00:01:17 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 243 ; free virtual = 5327 +Finished Timing Optimization : Time (s): cpu = 00:00:48 ; elapsed = 00:00:50 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 193 ; free virtual = 3161 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting @@ -234,7 +230,7 @@ INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/mem INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_7 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. INFO: [Synth 8-7052] The timing for the instance storage_generate[3].storage/memory_reg_8 (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:01:07 ; elapsed = 00:01:21 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 381 ; free virtual = 5319 +Finished Technology Mapping : Time (s): cpu = 00:00:52 ; elapsed = 00:00:55 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 184 ; free virtual = 3158 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion @@ -252,37 +248,55 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:01:16 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +Finished IO Insertion : Time (s): cpu = 00:01:01 ; elapsed = 00:01:04 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:01:16 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +Finished Renaming Generated Instances : Time (s): cpu = 00:01:01 ; elapsed = 00:01:04 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:17 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:02 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:01:17 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +Finished Renaming Generated Ports : Time (s): cpu = 00:01:02 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:01:17 ; elapsed = 00:01:33 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +Finished Handling Custom Attributes : Time (s): cpu = 00:01:03 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:01:17 ; elapsed = 00:01:34 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 168 ; free virtual = 5189 +Finished Renaming Generated Nets : Time (s): cpu = 00:01:03 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152 +--------------------------------------------------------------------------------- +--------------------------------------------------------------------------------- +Start ROM, RAM, DSP, Shift Register and Retiming Reporting +--------------------------------------------------------------------------------- + +Static Shift Register Report: ++------------+--------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | ++------------+--------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ +|filter | hash_generate[0].hash/final/s_reg[7][valid] | 13 | 1 | NO | NO | NO | 1 | 0 | +|filter | memory_key_reg[127] | 8 | 32 | NO | NO | YES | 32 | 0 | +|filter | memory_key_reg[95] | 14 | 89 | NO | NO | YES | 89 | 0 | +|filter | memory_key_reg[38] | 13 | 7 | NO | NO | YES | 7 | 0 | +|filter | hash_generate[0].hash/mix_pipeline[0].mix/s_reg[6][key][100] | 7 | 32 | NO | YES | YES | 32 | 0 | ++------------+--------------------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ + +--------------------------------------------------------------------------------- +Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -298,41 +312,41 @@ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ -|1 |CARRY4 | 681| -|2 |LUT1 | 228| -|3 |LUT2 | 874| -|4 |LUT3 | 900| -|5 |LUT4 | 260| -|6 |LUT5 | 995| -|7 |LUT6 | 950| -|8 |RAMB18E1 | 4| -|9 |RAMB36E1 | 32| -|10 |FDRE | 563| +|1 |CARRY4 | 745| +|2 |LUT1 | 227| +|3 |LUT2 | 3166| +|4 |LUT3 | 764| +|5 |LUT4 | 4| +|6 |LUT6 | 201| +|7 |RAMB18E1 | 4| +|8 |RAMB36E1 | 32| +|9 |SRL16E | 161| +|10 |FDRE | 4794| +------+---------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:01:17 ; elapsed = 00:01:34 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 164 ; free virtual = 5187 +Finished Writing Synthesis Report : Time (s): cpu = 00:01:03 ; elapsed = 00:01:05 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 138 ; free virtual = 3152 --------------------------------------------------------------------------------- -Synthesis finished with 0 errors, 0 critical warnings and 5 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:01:11 ; elapsed = 00:01:26 . Memory (MB): peak = 2252.359 ; gain = 502.434 ; free physical = 148 ; free virtual = 5185 -Synthesis Optimization Complete : Time (s): cpu = 00:01:17 ; elapsed = 00:01:34 . Memory (MB): peak = 2252.359 ; gain = 617.203 ; free physical = 145 ; free virtual = 5184 +Synthesis finished with 0 errors, 0 critical warnings and 3 warnings. +Synthesis Optimization Runtime : Time (s): cpu = 00:00:57 ; elapsed = 00:01:00 . Memory (MB): peak = 2269.754 ; gain = 504.496 ; free physical = 134 ; free virtual = 3152 +Synthesis Optimization Complete : Time (s): cpu = 00:01:03 ; elapsed = 00:01:06 . Memory (MB): peak = 2269.754 ; gain = 618.297 ; free physical = 134 ; free virtual = 3152 INFO: [Project 1-571] Translating synthesized netlist -Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2252.359 ; gain = 0.000 ; free physical = 115 ; free virtual = 5167 -INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement +Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2269.754 ; gain = 0.000 ; free physical = 384 ; free virtual = 3430 +INFO: [Netlist 29-17] Analyzing 781 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2252.359 ; gain = 0.000 ; free physical = 313 ; free virtual = 5535 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2269.754 ; gain = 0.000 ; free physical = 311 ; free virtual = 3423 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Synth Design complete | Checksum: d74e1ad3 +Synth Design complete | Checksum: 806ce973 INFO: [Common 17-83] Releasing license: Synthesis -66 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. +66 Infos, 6 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:01:33 ; elapsed = 00:01:44 . Memory (MB): peak = 2252.359 ; gain = 977.047 ; free physical = 232 ; free virtual = 5481 -INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1724.537; main = 1326.676; forked = 397.861 -INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3235.051; main = 2252.328; forked = 982.723 -Write ShapeDB Complete: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2276.336 ; gain = 0.000 ; free physical = 226 ; free virtual = 5482 +synth_design: Time (s): cpu = 00:01:18 ; elapsed = 00:01:16 . Memory (MB): peak = 2269.754 ; gain = 978.141 ; free physical = 301 ; free virtual = 3421 +INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 1616.477; main = 1400.213; forked = 417.991 +INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3233.605; main = 2269.723; forked = 963.883 +Write ShapeDB Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2269.754 ; gain = 0.000 ; free physical = 297 ; free virtual = 3420 INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/filter.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file filter_utilization_synth.rpt -pb filter_utilization_synth.pb -INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 18:50:06 2023... +INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 21:15:58 2023... diff --git a/synth/filter_vivado.runs/synth_1/vivado.jou b/synth/filter_vivado.runs/synth_1/vivado.jou index 8ba0bf1..7906e5b 100644 --- a/synth/filter_vivado.runs/synth_1/vivado.jou +++ b/synth/filter_vivado.runs/synth_1/vivado.jou @@ -3,12 +3,12 @@ # SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 -# Start of session at: Sun Dec 3 18:47:59 2023 -# Process ID: 18749 +# Start of session at: Sun Dec 3 21:14:16 2023 +# Process ID: 50094 # Current directory: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1 # Command line: vivado -log filter.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source filter.tcl # Log file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/filter.vds # Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/vivado.jou -# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 3075.336 MHz, CPU Physical cores: 4, Host memory: 3903 MB +# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2783.625 MHz, CPU Physical cores: 4, Host memory: 3903 MB #----------------------------------------------------------- source filter.tcl -notrace diff --git a/synth/filter_vivado.runs/synth_1/vivado.pb b/synth/filter_vivado.runs/synth_1/vivado.pb index 9a1c851..6a5a69b 100644 Binary files a/synth/filter_vivado.runs/synth_1/vivado.pb and b/synth/filter_vivado.runs/synth_1/vivado.pb differ diff --git a/synth/filter_vivado.xpr b/synth/filter_vivado.xpr index 6410e57..5786b4a 100644 --- a/synth/filter_vivado.xpr +++ b/synth/filter_vivado.xpr @@ -223,7 +223,7 @@ - + @@ -240,7 +240,7 @@ - + @@ -256,25 +256,25 @@ - + - + - + - + - + @@ -319,19 +319,19 @@ - + - + - + diff --git a/vivado.jou b/vivado.jou new file mode 100644 index 0000000..8cf6be0 --- /dev/null +++ b/vivado.jou @@ -0,0 +1,50 @@ +#----------------------------------------------------------- +# Vivado v2023.2 (64-bit) +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 +# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 +# Start of session at: Sun Dec 3 19:35:56 2023 +# Process ID: 27830 +# Current directory: /home/veronikaplevacova/Plocha/PCS2 +# Command line: vivado +# Log file: /home/veronikaplevacova/Plocha/PCS2/vivado.log +# Journal file: /home/veronikaplevacova/Plocha/PCS2/vivado.jou +# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2785.863 MHz, CPU Physical cores: 4, Host memory: 3903 MB +#----------------------------------------------------------- +start_gui +open_project /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.xpr +update_compile_order -fileset sources_1 +open_run impl_1 +reset_run synth_1 +launch_runs synth_1 -jobs 2 +wait_on_run synth_1 +launch_runs impl_1 -jobs 2 +wait_on_run impl_1 +reset_run synth_1 +launch_runs impl_1 -jobs 2 +wait_on_run impl_1 +refresh_design +open_run synth_1 -name synth_1 +report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1 +current_design impl_1 +report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1 +reset_run synth_1 +launch_runs impl_1 -jobs 2 +wait_on_run impl_1 +current_design synth_1 +refresh_design +current_design impl_1 +current_design synth_1 +report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1 +reset_run synth_1 +launch_runs impl_1 -jobs 2 +wait_on_run impl_1 +reset_run synth_1 +launch_runs impl_1 -jobs 2 +wait_on_run impl_1 +report_power -name {power_1} +report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_2 +reset_run synth_1 +launch_runs impl_1 -jobs 2 +wait_on_run impl_1 +report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_3 diff --git a/vivado.log b/vivado.log new file mode 100644 index 0000000..63bbaea --- /dev/null +++ b/vivado.log @@ -0,0 +1,342 @@ +#----------------------------------------------------------- +# Vivado v2023.2 (64-bit) +# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 +# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 +# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 +# Start of session at: Sun Dec 3 19:35:56 2023 +# Process ID: 27830 +# Current directory: /home/veronikaplevacova/Plocha/PCS2 +# Command line: vivado +# Log file: /home/veronikaplevacova/Plocha/PCS2/vivado.log +# Journal file: /home/veronikaplevacova/Plocha/PCS2/vivado.jou +# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2785.863 MHz, CPU Physical cores: 4, Host memory: 3903 MB +#----------------------------------------------------------- +start_gui +open_project /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.xpr +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kc705:part0:1.6 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kc705/1.6/board.xml as part xc7k325tffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.6 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.6/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu105:part0:1.7 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu105/1.7/board.xml as part xcku040-ffva1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.4 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.4/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu116:part0:1.5 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu116/1.5/board.xml as part xcku5p-ffvb676-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:kcu1500:part0:1.2 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/kcu1500/1.2/board.xml as part xcku115-flvb2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc707:part0:1.4 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc707/1.4/board.xml as part xc7vx485tffg1761-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vc709:part0:1.8 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vc709/1.8/board.xml as part xc7vx690tffg1761-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:2.2 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/2.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.1/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190:part0:3.2 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190/production/3.2/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.0/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vck190_newl:part0:1.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vck190_newl/production/1.1/board.xml as part xcvc1902-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.6 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.6/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu108:part0:1.7 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu108/1.7/board.xml as part xcvu095-ffva2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu110:part0:1.4 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu110/1.4/board.xml as part xcvu190-flgc2104-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.0/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.3 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.3/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu118:part0:2.4 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu118/2.4/board.xml as part xcvu9p-flga2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu128:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu128/production/1.0/board.xml as part xcvu37p-fsvh2892-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu129:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu129/production/1.0/board.xml as part xcvu29p-fsga2577-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vcu1525:part0:1.3 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vcu1525/1.3/board.xml as part xcvu9p-fsgd2104-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/production/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.0/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es:part0:1.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_a/1.1/board.xml as part xcve2802-vsvh1760-2lp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.0/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vek280_es_revb:part0:1.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vek280/es/rev_b/1.1/board.xml as part xcve2802-vsvh1760-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_mpsoc:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml as part xczu19eg-ffvd1760-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vermeo_t1_rfsoc:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml as part xczu21dr-ffvd1156-2l-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158:part0:1.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/production/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.0/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vhk158_es:part0:1.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vhk158/es/1.1/board.xml as part xcvh1582-vsva3697-2mp-e-s-es1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:2.2 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/2.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180:part0:3.2 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180/production/3.2/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.0/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vmk180_newl:part0:1.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vmk180_newl/production/1.1/board.xml as part xcvm1802-vsva2197-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.0/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.1/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk120:part0:1.2 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk120/production/1.2/board.xml as part xcvp1202-vsva2785-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.0/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:vpk180:part0:1.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/vpk180/production/1.1/board.xml as part xcvp1802-lsvc4072-2mp-e-s specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc702:part0:1.4 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc702/1.4/board.xml as part xc7z020clg484-1 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zc706:part0:1.4 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zc706/1.4/board.xml as part xc7z045ffg900-2 specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.3 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.3/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu102:part0:3.4 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu102/3.4/board.xml as part xczu9eg-ffvb1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu104:part0:1.1 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu104/1.1/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu106:part0:2.4 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu106/2.4/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu106:part0:2.5 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu106/2.5/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu106:part0:2.6 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu106/2.6/board.xml as part xczu7ev-ffvc1156-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.2 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.2/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.3 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.3/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu111:part0:1.4 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu111/1.4/board.xml as part xczu28dr-ffvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1275:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1275/1.0/board.xml as part xczu29dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu1285:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu1285/1.0/board.xml as part xczu39dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208:part0:2.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208/production/2.0/board.xml as part xczu48dr-fsvg1517-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu208ld:part0:2.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu208ld/production/2.0/board.xml as part xczu58dr-fsvg1517-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216:part0:2.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216/production/2.0/board.xml as part xczu49dr-ffvf1760-2-e specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu216ld:part0:2.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670:part0:2.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available +WARNING: [Board 49-26] cannot add Board Part xilinx.com:zcu670ld:part0:1.0 available at /tools/Xilinx/Vivado/2023.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available +INFO: [filemgmt 56-3] Default IP Output Path : Could not find the directory '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.gen/sources_1'. +Scanning sources... +Finished scanning sources +INFO: [IP_Flow 19-234] Refreshing IP repositories +INFO: [IP_Flow 19-1704] No user IP repositories specified +INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2023.2/data/ip'. +open_project: Time (s): cpu = 00:00:33 ; elapsed = 00:00:18 . Memory (MB): peak = 7745.375 ; gain = 351.125 ; free physical = 110 ; free virtual = 9678 +update_compile_order -fileset sources_1 +open_run impl_1 +INFO: [Device 21-403] Loading part xc7k160tffv676-1 +Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 8166.188 ; gain = 0.000 ; free physical = 131 ; free virtual = 9488 +INFO: [Netlist 29-17] Analyzing 717 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2023.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Read ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 8235.938 ; gain = 0.000 ; free physical = 110 ; free virtual = 9407 +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +INFO: [Designutils 20-5722] Start Reading Physical Databases. +Reading placement. +Read Netlist Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 8819.555 ; gain = 0.000 ; free physical = 133 ; free virtual = 8851 +Reading placer database... +Read Device Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 8819.555 ; gain = 0.000 ; free physical = 132 ; free virtual = 8851 +Read PlaceDB: Time (s): cpu = 00:00:00.41 ; elapsed = 00:00:00.39 . Memory (MB): peak = 8819.555 ; gain = 0.000 ; free physical = 232 ; free virtual = 8852 +Read PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 8819.555 ; gain = 0.000 ; free physical = 232 ; free virtual = 8852 +Reading routing. +Read RouteStorage: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.26 . Memory (MB): peak = 8829.555 ; gain = 10.000 ; free physical = 230 ; free virtual = 8851 +Read Physdb Files: Time (s): cpu = 00:00:00.71 ; elapsed = 00:00:00.69 . Memory (MB): peak = 8829.555 ; gain = 10.000 ; free physical = 230 ; free virtual = 8851 +Restored from archive | CPU: 0.720000 secs | Memory: 7.179550 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00.71 ; elapsed = 00:00:00.69 . Memory (MB): peak = 8829.555 ; gain = 10.000 ; free physical = 230 ; free virtual = 8851 +Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 8829.555 ; gain = 0.000 ; free physical = 224 ; free virtual = 8849 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +open_run: Time (s): cpu = 00:00:38 ; elapsed = 00:00:27 . Memory (MB): peak = 9065.062 ; gain = 1229.688 ; free physical = 219 ; free virtual = 8715 +CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +reset_run synth_1 +launch_runs synth_1 -jobs 2 +WARNING: [Vivado 12-7122] Auto Incremental Compile:: No reference checkpoint was found in run synth_1. Auto-incremental flow will not be run, the standard flow will be run instead. +[Sun Dec 3 19:45:29 2023] Launched synth_1... +Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/runme.log +launch_runs impl_1 -jobs 2 +[Sun Dec 3 19:47:42 2023] Launched impl_1... +Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/runme.log +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +reset_run synth_1 +launch_runs impl_1 -jobs 2 +[Sun Dec 3 20:03:31 2023] Launched synth_1... +Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/runme.log +[Sun Dec 3 20:03:31 2023] Launched impl_1... +Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/runme.log +refresh_design +Netlist sorting complete. Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.06 . Memory (MB): peak = 9231.645 ; gain = 0.000 ; free physical = 1096 ; free virtual = 7869 +INFO: [Netlist 29-17] Analyzing 781 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2023.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Read ShapeDB Complete: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 9231.645 ; gain = 0.000 ; free physical = 1068 ; free virtual = 7860 +INFO: [Timing 38-478] Restoring timing data from binary archive. +INFO: [Timing 38-479] Binary timing data restore complete. +INFO: [Project 1-856] Restoring constraints from binary archive. +INFO: [Project 1-853] Binary constraint restore complete. +INFO: [Designutils 20-5722] Start Reading Physical Databases. +Reading placement. +Read Netlist Cache: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 9231.645 ; gain = 0.000 ; free physical = 1012 ; free virtual = 7830 +Reading placer database... +Read Device Cache: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 9231.645 ; gain = 0.000 ; free physical = 1012 ; free virtual = 7830 +Read PlaceDB: Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.45 . Memory (MB): peak = 9231.645 ; gain = 0.000 ; free physical = 1009 ; free virtual = 7827 +Read PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9231.645 ; gain = 0.000 ; free physical = 1009 ; free virtual = 7827 +Reading routing. +Read RouteStorage: Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.38 . Memory (MB): peak = 9231.645 ; gain = 0.000 ; free physical = 983 ; free virtual = 7801 +Read Physdb Files: Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.87 . Memory (MB): peak = 9231.645 ; gain = 0.000 ; free physical = 983 ; free virtual = 7801 +Restored from archive | CPU: 0.860000 secs | Memory: 7.690048 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00.72 ; elapsed = 00:00:00.87 . Memory (MB): peak = 9231.645 ; gain = 0.000 ; free physical = 983 ; free virtual = 7801 +refresh_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 9259.844 ; gain = 28.199 ; free physical = 832 ; free virtual = 7777 +CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. +open_run synth_1 -name synth_1 +Design is defaulting to impl run constrset: constrs_1 +Design is defaulting to synth run part: xc7k160tffv676-1 +Netlist sorting complete. Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 9262.000 ; gain = 0.000 ; free physical = 721 ; free virtual = 7688 +INFO: [Netlist 29-17] Analyzing 781 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2023.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 9262.000 ; gain = 0.000 ; free physical = 652 ; free virtual = 7618 +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1 +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs +WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew +Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design +current_design impl_1 +report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1 +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs +WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew +Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +reset_run synth_1 +launch_runs impl_1 -jobs 2 +WARNING: [Project 1-478] Design 'synth_1' is stale and will not be used when launching 'impl_1' +[Sun Dec 3 20:21:41 2023] Launched synth_1... +Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/runme.log +[Sun Dec 3 20:21:42 2023] Launched impl_1... +Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/runme.log +current_design synth_1 +refresh_design +Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 9646.148 ; gain = 0.000 ; free physical = 1181 ; free virtual = 7483 +INFO: [Netlist 29-17] Analyzing 781 Unisim elements for replacement +INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds +INFO: [Project 1-479] Netlist was created with Vivado 2023.2 +INFO: [Project 1-570] Preparing netlist for logic optimization +Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc] +INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). +refresh_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 9646.148 ; gain = 5.934 ; free physical = 1046 ; free virtual = 7480 +current_design impl_1 +CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations. +current_design synth_1 +report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1 +WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13] +INFO: [Timing 38-35] Done setting XDC timing constraints. +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs +WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew +Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +reset_run synth_1 +launch_runs impl_1 -jobs 2 +WARNING: [Project 1-478] Design 'synth_1' is stale and will not be used when launching 'impl_1' +[Sun Dec 3 20:41:40 2023] Launched synth_1... +Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/runme.log +[Sun Dec 3 20:41:40 2023] Launched impl_1... +Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/runme.log +reset_run synth_1 +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +launch_runs impl_1 -jobs 2 +WARNING: [Project 1-478] Design 'synth_1' is stale and will not be used when launching 'impl_1' +[Sun Dec 3 20:44:09 2023] Launched synth_1... +Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/runme.log +[Sun Dec 3 20:44:09 2023] Launched impl_1... +Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/runme.log +report_power -name {power_1} +Command: report_power -name power_1 +Running Vector-less Activity Propagation... + +Finished Running Vector-less Activity Propagation +0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. +report_power completed successfully +report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_2 +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_final.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_mix.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/block_memory.vhd:] +WARNING: [filemgmt 56-199] Attempt to get parsing info during refresh. "On-the-fly" syntax checking information may be incorrect. [/home/veronikaplevacova/Plocha/PCS2/comp/jenkins_hash.vhd:] +reset_run synth_1 +launch_runs impl_1 -jobs 2 +WARNING: [Project 1-478] Design 'synth_1' is stale and will not be used when launching 'impl_1' +[Sun Dec 3 21:14:11 2023] Launched synth_1... +Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/runme.log +[Sun Dec 3 21:14:12 2023] Launched impl_1... +Run output will be captured here: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/runme.log +report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_3 +INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. +INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs +exit +INFO: [Common 17-206] Exiting Vivado at Sun Dec 3 21:22:03 2023...