102 lines
3.8 KiB
VHDL
102 lines
3.8 KiB
VHDL
-- block_memory.vhd: General storage memory build from BlockRAMs or M20Ks with one read and one write port
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-- Copyright (C) 2019 FIT BUT
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-- Author(s): Lukas Kekely <ikekely@fit.vutbr.cz>
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--
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-- SPDX-License-Identifier: BSD-3-Clause
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_unsigned.all;
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use work.functions_package.clog2;
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entity block_memory is
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generic(
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-- Size of the memory.
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-- ITEMS individual records addressed from 0 to ITEMS-1, each ITEM_WIDTH bits wide.
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ITEM_WIDTH : natural := 32;
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ITEMS : natural := 1024;
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-- Enables output data register on read port for better frequency.
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-- Latency of reading data from the memory is 1 clock cycle when false, and 2 clock cycles when true.
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OUTPUT_REGISTER : boolean := true
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);
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port (
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-- Main clock signal and its synchronous reset.
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CLK : in std_logic;
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RESET : in std_logic;
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-- Read interface ----------------------------------------------------------
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READ_ADDRESS : in std_logic_vector(clog2(ITEMS)-1 downto 0); -- item address to read
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READ_VALID : in std_logic; -- read is valid
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READ_DATA : out std_logic_vector(ITEM_WIDTH-1 downto 0); -- read data (note: read latency!)
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READ_DATA_VALID : out std_logic; -- delayed read valid flag
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-- Write interface ---------------------------------------------------------
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WRITE_DATA : in std_logic_vector(ITEM_WIDTH-1 downto 0); -- data to write
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WRITE_ADDRESS : in std_logic_vector(clog2(ITEMS)-1 downto 0); -- item address to write
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WRITE_VALID : in std_logic -- perform write operation
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);
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end entity;
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architecture behavioral of block_memory is
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type memory_type is array(0 to ITEMS-1) of std_logic_vector(ITEM_WIDTH-1 downto 0);
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signal memory : memory_type;
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signal memory_data : std_logic_vector(ITEM_WIDTH-1 downto 0);
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signal memory_data_valid : std_logic;
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attribute ramstyle : string;
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attribute ramstyle of memory : signal is "M20K";
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begin
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-- Unsupported configurations checks -----------------------------------------
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assert ITEMS > 1 report "FAILURE: Block Memory must have at least two items!" severity failure;
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assert ITEM_WIDTH > 0 report "FAILURE: Block Memory item must be at least 1 bit wide!" severity failure;
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-- Runtime error checks ------------------------------------------------------
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assert conv_integer(READ_ADDRESS) < ITEMS or RESET/= '0' report "ERROR: Block Memory read out of bounds!" severity error;
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assert conv_integer(WRITE_ADDRESS) < ITEMS or RESET/= '0' report "ERROR: Block Memory write out of bounds!" severity error;
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-- Memory core implementation ------------------------------------------------
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storage_core: process(CLK)
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begin
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if rising_edge(CLK) then
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-- Write port
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if WRITE_VALID = '1' then
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memory(conv_integer(WRITE_ADDRESS)) <= WRITE_DATA;
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end if;
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-- Read port
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memory_data <= memory(conv_integer(READ_ADDRESS));
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if RESET = '1' then
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memory_data_valid <= '0';
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else
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memory_data_valid <= READ_VALID;
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end if;
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end if;
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end process;
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-- Optional output register on read port -------------------------------------
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registered_read: if OUTPUT_REGISTER generate
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read_register: process(CLK)
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begin
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if rising_edge(CLK) then
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READ_DATA <= memory_data;
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if RESET = '1' then
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READ_DATA_VALID <= '0';
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else
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READ_DATA_VALID <= memory_data_valid;
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end if;
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end if;
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end process;
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end generate;
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direct_read: if not OUTPUT_REGISTER generate
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READ_DATA <= memory_data;
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READ_DATA_VALID <= memory_data_valid;
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end generate;
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end architecture; |