honzastor
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6003886eb7
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Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later
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2024-04-14 16:29:10 +02:00 |
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Vojta Mrazek
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2e1694ccd5
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popcount and compare
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2024-03-22 14:19:23 +01:00 |
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Vojta Mrazek
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a4741db191
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connection checks (asserts)
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2023-03-28 11:16:55 +02:00 |
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honzastor
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d52e67bb25
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Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.
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2023-02-24 11:13:46 +01:00 |
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Vojta Mrazek
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6dd69c5aaa
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Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel
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2023-02-22 09:52:34 +01:00 |
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Vojta Mrazek
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43b3d65463
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workflow modification, bus indexing
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2023-02-22 09:52:06 +01:00 |
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Vojta Mrazek
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71a1d45045
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string description (#15)
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2023-02-22 09:45:14 +01:00 |
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Vojta Mrazek
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35240abc63
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fix bug in python interpretation
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2023-02-22 09:43:24 +01:00 |
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Honza
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c0dcf42499
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Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.
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2022-04-17 13:04:17 +02:00 |
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Honza
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6f05db002e
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Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup.
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2022-02-18 17:00:31 +01:00 |
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Honza
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c8ed08691f
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Updated functionality of the extend_bus method.
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2021-11-16 00:02:52 +01:00 |
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honzastor
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5d41997560
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Added assertion checks for the same input bus lengths when initializing arithmetic circuits.
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2021-10-24 18:48:00 +02:00 |
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honzastor
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d41c5f3c94
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Updated exportation of signed arithmetic circuits to python representation. Also unified some methods from arithmetic_circuit.py into general_circuit.py.
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2021-10-10 22:15:13 +02:00 |
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honzastor
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16c1757bc3
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Added signedness support for the output C code representation. Also modified the testing scripts and the chr2c.py converter accordingly and did some documentation changes (even made a small change in readme.md). Signedness support for the output python representation is TBD.
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2021-10-09 23:45:54 +02:00 |
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Vojta Mrazek
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152a6b1583
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Python eval (#4)
* #3 basic clean up arithmetic circuit and general circuit
* #3 implementation of python generator
* #3 pytest in actions
* #3 pytest in actions fix
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2021-10-04 11:58:28 +02:00 |
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honzastor
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e16de78c2b
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Updated logic behind generating export representations, mainly focused around circuit and its buses and subcomponents namings.
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2021-09-07 17:39:39 +02:00 |
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honzastor
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0f66c5a2e9
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Fixed proper connections in submodules instantiation in hierarchical Verilog generation. Sample generated circuits were also accordingly updated.
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2021-04-23 11:49:24 +02:00 |
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honzastor
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8e950fc51f
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Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.
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2021-04-21 11:33:07 +02:00 |
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honzastor
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a336a683e7
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Added some code documentation and updated git action to generate it.
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2021-03-31 04:40:54 +02:00 |
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honzastor
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69e2514852
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Updated project's structure. Renamed class names to properly fit Python naming convention. TBD: proper documentation.
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2021-03-30 03:04:48 +02:00 |
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