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dissertation_thesis
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ariths-gen-mig
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ariths-gen-mig
/
ariths_gen
/
multi_bit_circuits
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Lukáš Plevač
c476479827
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Fix mux with wrong gate ordering
2024-11-14 15:15:17 +01:00
..
adders
Fix mux with wrong gate ordering
2024-11-14 15:15:17 +01:00
approximate_adders
Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue.
2024-04-13 17:04:03 +02:00
approximate_multipliers
Fully working xorGateComponent
2024-10-10 13:33:09 +02:00
dividers
Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue.
2024-04-13 17:04:03 +02:00
multipliers
Fully working xorGateComponent
2024-10-10 13:33:09 +02:00
others
Fully working xorGateComponent
2024-10-10 13:33:09 +02:00
subtractors
Fully working xorGateComponent
2024-10-10 13:33:09 +02:00
__init__.py
Updated project's structure. Renamed class names to properly fit Python naming convention. TBD: proper documentation.
2021-03-30 03:04:48 +02:00
