4 Commits

Author	SHA1	Message	Date
honzastor	e8cffeca91	Generated and tested generated circuits.	2021-03-04 18:59:33 +01:00
honzastor	c9ddb834f7	Generated flat Verilog adder and gate circuits. Minor update to C code logic gates.	2021-02-16 10:38:36 +01:00
honzastor	193d504120	Generated hierarchical C code circuits and updated testing script correspondigly.	2021-02-12 01:45:26 +01:00
honzastor	f1142b51d9	Implemented basic tests for generated flat C code circuits.	2021-02-09 21:02:50 +01:00