8 Commits

Author SHA1 Message Date
Jan Klhůfek
56c86c13ca
New multipliers (#13)
* #10 CGP Circuits as inputs (#11)

* CGP Circuits as inputs

* #10 support of signed output in general circuit

* input as output works

* output connected to input (c)

* automated verilog testing

* output rename

* Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup.

* Typos fix and code cleanup.

* Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.

* Updated automated testing scripts.

* Small bugfix in python code generation (I initially thought this line is useless).

* Updated generated circuits folder.

Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
2022-04-17 16:00:00 +02:00
honzastor
16c1757bc3 Added signedness support for the output C code representation. Also modified the testing scripts and the chr2c.py converter accordingly and did some documentation changes (even made a small change in readme.md). Signedness support for the output python representation is TBD. 2021-10-09 23:45:54 +02:00
honzastor
eba0a7a938 Made some minor changes concerning proper exportation of multiplier circuits. 2021-09-09 13:57:36 +02:00
honzastor
e16de78c2b Updated logic behind generating export representations, mainly focused around circuit and its buses and subcomponents namings. 2021-09-07 17:39:39 +02:00
Vojta Mrazek
cfe0ca6b4b
Automated testing, preparing the package for publishing (#1)
* automated pandoc deploy

* automated pandoc deploy (v2)

* automated pandoc deploy (v2)

* automated pdoc deploy (v3)

* automated pdoc deploy (v4)

* automated pdoc deploy (v5)

* automated pdoc deploy (v5)

* prepare for python project

* 8-bit testing

* 8-bit testing

* 8-bit testing (v2)

* 8-bit testing (v3)

* update of sign
2021-06-18 12:38:11 +02:00
honzastor
8e950fc51f Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits. 2021-04-21 11:33:07 +02:00
honzastor
a336a683e7 Added some code documentation and updated git action to generate it. 2021-03-31 04:40:54 +02:00
honzastor
69e2514852 Updated project's structure. Renamed class names to properly fit Python naming convention. TBD: proper documentation. 2021-03-30 03:04:48 +02:00