From e662c52e7514c41a3b30dc1da3fabf07aa654bb4 Mon Sep 17 00:00:00 2001
From: Lukas Plevac <iplevac@fit.vutbr.cz>
Date: Sun, 19 Jan 2025 19:10:26 +0100
Subject: [PATCH] Static write FA to PGAdder

---
 .../three_input_one_bit_components.py           |  2 --
 .../two_input_one_bit_components.py             | 17 +++++++++++++----
 2 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py b/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
index 18f0e49..7c0ca37 100644
--- a/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
+++ b/ariths_gen/one_bit_circuits/one_bit_components/three_input_one_bit_components.py
@@ -26,8 +26,6 @@ class FullAdder(ThreeInputOneBitCircuit):
         name (str, optional): Name of full adder. Defaults to "fa".
     """
     use_verilog_instance = False
-    disable_generation   = False
-
     def __init__(self, a: Wire = Wire(name="a"), b: Wire = Wire(name="b"), c: Wire = Wire(name="cin"), prefix: str = "", name: str = "fa"):
         super().__init__(a, b, c, prefix=prefix, name=name)
         # 2 wires for component's bus output (sum, cout)
diff --git a/ariths_gen/one_bit_circuits/one_bit_components/two_input_one_bit_components.py b/ariths_gen/one_bit_circuits/one_bit_components/two_input_one_bit_components.py
index 1a43b84..6a91790 100644
--- a/ariths_gen/one_bit_circuits/one_bit_components/two_input_one_bit_components.py
+++ b/ariths_gen/one_bit_circuits/one_bit_components/two_input_one_bit_components.py
@@ -1,5 +1,4 @@
 from ariths_gen.core.one_bit_circuits import TwoInputOneBitCircuit
-from .three_input_one_bit_components import FullAdder
 from ariths_gen.one_bit_circuits.logic_gates import AndGate, NandGate, OrGate, NorGate, NotGate
 from ariths_gen.one_bit_circuits import Maji
 from ariths_gen.wire_components import Wire, Bus
@@ -209,12 +208,22 @@ class partialAdder(TwoInputOneBitCircuit):
         generate_and = AndGate(a, b, prefix=self.prefix+"_and"+str(self.get_instance_num(cls=AndGate)), outid=1, parent_component=self)
         self.add_component(generate_and)
 
-        fa = FullAdder(a, b, cin, prefix=self.prefix+"_fa" +str(self.get_instance_num(cls=FullAdder)))
-        self.add_component(fa)
+        ##
+        # FA
+        obj_maji1 = Maji(cin, a, b, [True, False, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=2, parent_component=self)
+        self.add_component(obj_maji1)
+        
+        # cout
+        obj_maji2 = Maji(cin, a, b, [False, False, False], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=2, parent_component=self)
+        self.add_component(obj_maji2)
+
+        # sum
+        obj_maji3 = Maji(cin, obj_maji1.out, obj_maji2.out, [False, False, True], prefix=self.prefix+"_maji"+str(self.get_instance_num(cls=Maji)), outid=2, parent_component=self)
+        self.add_component(obj_maji3)
 
         self.out.connect(0, propagate_or.out)
         self.out.connect(1, generate_and.out)
-        self.out.connect(2, fa.get_sum_wire())
+        self.out.connect(2, obj_maji3.out)
 
     def get_propagate_wire(self):
         """Get output wire carrying propagate signal value.