final
This commit is contained in:
parent
b92289e7d5
commit
b6669d3189
@ -49,11 +49,14 @@ architecture behavioral of block_memory is
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signal memory_data : std_logic_vector(ITEM_WIDTH-1 downto 0);
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signal memory_data_valid : std_logic;
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attribute ramstyle : string;
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attribute ramstyle of memory : signal is "M20K";
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--attribute ram_style : string;
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--attribute ram_style of memory: signal is "DISTRIBUTED"; -- 208 MHZ in implementation when no pipelining on memory but need lot of LUTRAM
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--attribute ram_style of memory: signal is "BLOCK";
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--attribute ram_style of memory: signal is "M20K";
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begin
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-- Unsupported configurations checks -----------------------------------------
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assert ITEMS > 1 report "FAILURE: Block Memory must have at least two items!" severity failure;
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assert ITEM_WIDTH > 0 report "FAILURE: Block Memory item must be at least 1 bit wide!" severity failure;
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@ -68,82 +68,52 @@ begin
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s(0).key <= INPUT_KEY;
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s(0).valid <= INPUT_VALID;
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-- Stage 1: c ^= b; c -= rot(b,14);
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stage1_p : process ( clk ) is
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pipeline_p : process ( clk ) is
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begin
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if rising_edge ( clk ) then
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-- Stage 1: c ^= b; c -= rot(b,14);
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s(1).a <= s(0).a;
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s(1).b <= s(0).b;
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s(1).c <= (s(0).c xor s(0).b) - rot(s(0).b, 14);
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s(1).key <= s(0).key;
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s(1).valid <= s(0).valid;
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end if;
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end process;
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-- Stage 2: a ^= c; a -= rot(c,11);
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stage2_p : process ( clk ) is
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begin
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if rising_edge ( clk ) then
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-- Stage 2: a ^= c; a -= rot(c,11);
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s(2).a <= (s(1).a xor s(1).c) - rot(s(1).c, 11);
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s(2).b <= s(1).b;
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s(2).c <= s(1).c;
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s(2).key <= s(1).key;
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s(2).valid <= s(1).valid;
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end if;
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end process;
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-- Stage 3: b ^= a; b -= rot(a,25);
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stage3_p : process ( clk ) is
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begin
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if rising_edge ( clk ) then
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-- Stage 3: b ^= a; b -= rot(a,25);
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s(3).a <= s(2).a;
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s(3).b <= (s(2).b xor s(2).a) - rot(s(2).a, 25);
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s(3).c <= s(2).c;
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s(3).key <= s(2).key;
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s(3).valid <= s(2).valid;
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end if;
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end process;
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-- Stage 4: c ^= b; c -= rot(b,16);
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stage4_p : process ( clk ) is
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begin
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if rising_edge ( clk ) then
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-- Stage 4: c ^= b; c -= rot(b,16);
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s(4).a <= s(3).a;
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s(4).b <= s(3).b;
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s(4).c <= (s(3).c xor s(3).b) - rot(s(3).b, 16);
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s(4).key <= s(3).key;
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s(4).valid <= s(3).valid;
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end if;
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end process;
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-- Stage 5: a ^= c; a -= rot(c,4);
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stage5_p : process ( clk ) is
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begin
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if rising_edge ( clk ) then
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-- Stage 5: a ^= c; a -= rot(c,4);
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s(5).a <= (s(4).a xor s(4).c) - rot(s(4).c, 4);
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s(5).b <= s(4).b;
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s(5).c <= s(4).c;
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s(5).key <= s(4).key;
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s(5).valid <= s(4).valid;
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end if;
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end process;
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-- Stage 6: b ^= a; b -= rot(a,14);
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stage6_p : process ( clk ) is
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begin
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if rising_edge ( clk ) then
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-- Stage 6: b ^= a; b -= rot(a,14);
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s(6).a <= s(5).a;
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s(6).b <= (s(5).b xor s(5).a) - rot(s(5).a, 14);
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s(6).c <= s(5).c;
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s(6).key <= s(5).key;
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s(6).valid <= s(5).valid;
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end if;
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end process;
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-- Stage 7: c ^= b; c -= rot(b,24);
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stage7_p : process ( clk ) is
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begin
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if rising_edge ( clk ) then
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-- Stage 7: c ^= b; c -= rot(b,24);
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s(7).a <= s(6).a;
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s(7).b <= s(6).b;
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s(7).c <= (s(6).c xor s(6).b) - rot(s(6).b, 24);
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@ -68,71 +68,46 @@ begin
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s(0).key <= INPUT_KEY;
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s(0).valid <= INPUT_VALID;
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-- Stage 1: a -= c; a ^= rot(c, 4); c += b;
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stage1_p : process ( clk ) is
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pipeline_p : process ( clk ) is
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begin
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if rising_edge ( clk ) then
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-- Stage 1: a -= c; a ^= rot(c, 4); c += b;
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s(1).a <= (s(0).a - s(0).c) xor rot(s(0).c, 4);
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s(1).b <= s(0).b;
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s(1).c <= s(0).c + s(0).b;
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s(1).key <= s(0).key;
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s(1).valid <= s(0).valid;
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end if;
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end process;
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-- Stage 2: b -= a; b ^= rot(a, 6); a += c;
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stage2_p : process ( clk ) is
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begin
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if rising_edge ( clk ) then
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-- Stage 2: b -= a; b ^= rot(a, 6); a += c;
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s(2).a <= s(1).a + s(1).c;
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s(2).b <= (s(1).b - s(1).a) xor rot(s(1).a, 6);
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s(2).c <= s(1).c;
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s(2).key <= s(1).key;
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s(2).valid <= s(1).valid;
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end if;
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end process;
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-- Stage 3: c -= b; c ^= rot(b, 8); b += a;
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stage3_p : process ( clk ) is
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begin
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if rising_edge ( clk ) then
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-- Stage 3: c -= b; c ^= rot(b, 8); b += a;
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s(3).a <= s(2).a;
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s(3).b <= s(2).b + s(2).a;
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s(3).c <= (s(2).c - s(2).b) xor rot(s(2).b, 8);
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s(3).key <= s(2).key;
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s(3).valid <= s(2).valid;
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end if;
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end process;
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-- Stage 4: a -= c; a ^= rot(c,16); c += b;
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stage4_p : process ( clk ) is
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begin
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if rising_edge ( clk ) then
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-- Stage 4: a -= c; a ^= rot(c,16); c += b;
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s(4).a <= (s(3).a - s(3).c) xor rot(s(3).c, 16);
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s(4).b <= s(3).b;
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s(4).c <= s(3).c + s(3).b;
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s(4).key <= s(3).key;
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s(4).valid <= s(3).valid;
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end if;
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end process;
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-- Stage 5: b -= a; b ^= rot(a,19); a += c;
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stage5_p : process ( clk ) is
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begin
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if rising_edge ( clk ) then
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-- Stage 5: b -= a; b ^= rot(a,19); a += c;
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s(5).a <= s(4).a + s(4).c;
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s(5).b <= (s(4).b - s(4).a) xor rot(s(4).a, 19);
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s(5).c <= s(4).c;
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s(5).key <= s(4).key;
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s(5).valid <= s(4).valid;
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end if;
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end process;
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-- Stage 6: c -= b; c ^= rot(b, 4); b += a;
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stage6_p : process ( clk ) is
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begin
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if rising_edge ( clk ) then
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-- Stage 6: c -= b; c ^= rot(b, 4); b += a;
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s(6).a <= s(5).a;
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s(6).b <= s(5).b + s(5).a;
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s(6).c <= (s(5).c - s(5).b) xor rot(s(5).b, 4);
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@ -140,7 +115,7 @@ begin
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s(6).valid <= s(5).valid;
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end if;
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end process;
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-- Output connections
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OUTPUT_A <= s(STAGES).a;
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OUTPUT_B <= s(STAGES).b;
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@ -159,7 +159,7 @@ begin
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generic map (
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ITEM_WIDTH => RULE_WIDTH,
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ITEMS => TABLE_SIZE,
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OUTPUT_REGISTER => false
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OUTPUT_REGISTER => true
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) port map (
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CLK => CLK,
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RESET => RESET,
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@ -177,9 +177,9 @@ begin
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key_memory_register: process(CLK) -- key pipeline to match memory latency
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begin
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if rising_edge(CLK) then
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memory_key <= hash_key; -- memory is configured to have one cycle read latecy
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-- memory_key_reg <= hash_key;
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-- memory_key <= memory_key_reg;
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--memory_key <= hash_key; -- memory is configured to have one cycle read latecy
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memory_key_reg <= hash_key;
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memory_key <= memory_key_reg;
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end if;
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end process;
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10
synth/filter_vivado.cache/sim/ssm.db
Normal file
10
synth/filter_vivado.cache/sim/ssm.db
Normal file
@ -0,0 +1,10 @@
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################################################################################
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# DONOT REMOVE THIS FILE
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# Unified simulation database file for selected simulation model for IP
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#
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# File: ssm.db (Mon Dec 4 22:28:29 2023)
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#
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# This file is generated by the unified simulation automation and contains the
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# selected simulation model information for the IP/BD instances.
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# DONOT REMOVE THIS FILE
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################################################################################
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@ -1,4 +1,4 @@
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version:1
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6d6f64655f636f756e7465727c42617463684d6f6465:1
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6d6f64655f636f756e7465727c4755494d6f6465:2
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6d6f64655f636f756e7465727c4755494d6f6465:5
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eof:
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@ -45,7 +45,7 @@ version:1
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73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
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73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d64656275675f6c6f67:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
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73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d657374:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00
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73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a303873:00:00
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73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323236392e3735344d42:00:00
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73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3937342e3137324d42:00:00
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eof:920102437
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73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30313a313273:00:00
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73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:323234392e3534374d42:00:00
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73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3936382e3137324d42:00:00
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eof:1824714065
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@ -3,10 +3,10 @@
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<!--The data in this file is primarily intended for consumption by Xilinx tools.
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The structure and the elements are likely to change over the next few releases.
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This means code written to parse this file will need to be revisited each subsequent release.-->
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<application name="pa" timeStamp="Sun Dec 3 21:14:11 2023">
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<application name="pa" timeStamp="Tue Dec 12 15:26:16 2023">
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<section name="Project Information" visible="false">
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<property name="ProjectID" value="c9dd3875e3334360b2616c96fbb25f60" type="ProjectID"/>
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<property name="ProjectIteration" value="7" type="ProjectIteration"/>
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<property name="ProjectIteration" value="18" type="ProjectIteration"/>
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</section>
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<section name="PlanAhead Usage" visible="true">
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<item name="Project Data">
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4
synth/filter_vivado.cache/wt/xsim.wdf
Normal file
4
synth/filter_vivado.cache/wt/xsim.wdf
Normal file
@ -0,0 +1,4 @@
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version:1
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7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:64656661756c743a3a6265686176696f72616c:00:00
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7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00
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eof:241934075
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1
synth/filter_vivado.ip_user_files/README.txt
Normal file
1
synth/filter_vivado.ip_user_files/README.txt
Normal file
@ -0,0 +1 @@
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The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
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15
synth/filter_vivado.runs/.jobs/vrs_config_11.xml
Normal file
15
synth/filter_vivado.runs/.jobs/vrs_config_11.xml
Normal file
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<?xml version="1.0"?>
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<Runs Version="1" Minor="0">
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<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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<Run Id="impl_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
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<Parent Id="synth_1"/>
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</Run>
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<Parameters>
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<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
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<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
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<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
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<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
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</Parameters>
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<ProductInfo Name="vivado"/>
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</Runs>
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12
synth/filter_vivado.runs/.jobs/vrs_config_12.xml
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12
synth/filter_vivado.runs/.jobs/vrs_config_12.xml
Normal file
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<?xml version="1.0"?>
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<Runs Version="1" Minor="0">
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<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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<Parameters>
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<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
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<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
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<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
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<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
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</Parameters>
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<ProductInfo Name="vivado"/>
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</Runs>
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12
synth/filter_vivado.runs/.jobs/vrs_config_13.xml
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12
synth/filter_vivado.runs/.jobs/vrs_config_13.xml
Normal file
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<?xml version="1.0"?>
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<Runs Version="1" Minor="0">
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<Run Id="impl_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
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<Parameters>
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<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
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<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
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<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
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<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
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</Parameters>
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<ProductInfo Name="vivado"/>
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</Runs>
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12
synth/filter_vivado.runs/.jobs/vrs_config_14.xml
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12
synth/filter_vivado.runs/.jobs/vrs_config_14.xml
Normal file
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<?xml version="1.0"?>
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<Runs Version="1" Minor="0">
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<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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<Parameters>
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<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
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<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
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<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
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<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
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</Parameters>
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<ProductInfo Name="vivado"/>
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</Runs>
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12
synth/filter_vivado.runs/.jobs/vrs_config_15.xml
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12
synth/filter_vivado.runs/.jobs/vrs_config_15.xml
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<?xml version="1.0"?>
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<Runs Version="1" Minor="0">
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<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
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<Parameters>
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<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
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<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
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<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
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<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
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</Parameters>
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<ProductInfo Name="vivado"/>
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</Runs>
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12
synth/filter_vivado.runs/.jobs/vrs_config_16.xml
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12
synth/filter_vivado.runs/.jobs/vrs_config_16.xml
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<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
<ProductInfo Name="vivado"/>
|
||||
</Runs>
|
||||
|
||||
12
synth/filter_vivado.runs/.jobs/vrs_config_17.xml
Normal file
12
synth/filter_vivado.runs/.jobs/vrs_config_17.xml
Normal file
@ -0,0 +1,12 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="impl_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
<ProductInfo Name="vivado"/>
|
||||
</Runs>
|
||||
|
||||
12
synth/filter_vivado.runs/.jobs/vrs_config_18.xml
Normal file
12
synth/filter_vivado.runs/.jobs/vrs_config_18.xml
Normal file
@ -0,0 +1,12 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
<ProductInfo Name="vivado"/>
|
||||
</Runs>
|
||||
|
||||
12
synth/filter_vivado.runs/.jobs/vrs_config_19.xml
Normal file
12
synth/filter_vivado.runs/.jobs/vrs_config_19.xml
Normal file
@ -0,0 +1,12 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
<ProductInfo Name="vivado"/>
|
||||
</Runs>
|
||||
|
||||
12
synth/filter_vivado.runs/.jobs/vrs_config_20.xml
Normal file
12
synth/filter_vivado.runs/.jobs/vrs_config_20.xml
Normal file
@ -0,0 +1,12 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="impl_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
<ProductInfo Name="vivado"/>
|
||||
</Runs>
|
||||
|
||||
12
synth/filter_vivado.runs/.jobs/vrs_config_21.xml
Normal file
12
synth/filter_vivado.runs/.jobs/vrs_config_21.xml
Normal file
@ -0,0 +1,12 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
<ProductInfo Name="vivado"/>
|
||||
</Runs>
|
||||
|
||||
12
synth/filter_vivado.runs/.jobs/vrs_config_22.xml
Normal file
12
synth/filter_vivado.runs/.jobs/vrs_config_22.xml
Normal file
@ -0,0 +1,12 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="impl_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
<ProductInfo Name="vivado"/>
|
||||
</Runs>
|
||||
|
||||
15
synth/filter_vivado.runs/.jobs/vrs_config_23.xml
Normal file
15
synth/filter_vivado.runs/.jobs/vrs_config_23.xml
Normal file
@ -0,0 +1,15 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Run Id="impl_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
|
||||
<Parent Id="synth_1"/>
|
||||
</Run>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
<ProductInfo Name="vivado"/>
|
||||
</Runs>
|
||||
|
||||
15
synth/filter_vivado.runs/.jobs/vrs_config_24.xml
Normal file
15
synth/filter_vivado.runs/.jobs/vrs_config_24.xml
Normal file
@ -0,0 +1,15 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Run Id="impl_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
|
||||
<Parent Id="synth_1"/>
|
||||
</Run>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
<ProductInfo Name="vivado"/>
|
||||
</Runs>
|
||||
|
||||
15
synth/filter_vivado.runs/.jobs/vrs_config_25.xml
Normal file
15
synth/filter_vivado.runs/.jobs/vrs_config_25.xml
Normal file
@ -0,0 +1,15 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Run Id="impl_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
|
||||
<Parent Id="synth_1"/>
|
||||
</Run>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
<ProductInfo Name="vivado"/>
|
||||
</Runs>
|
||||
|
||||
15
synth/filter_vivado.runs/.jobs/vrs_config_26.xml
Normal file
15
synth/filter_vivado.runs/.jobs/vrs_config_26.xml
Normal file
@ -0,0 +1,15 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Run Id="impl_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
|
||||
<Parent Id="synth_1"/>
|
||||
</Run>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
<ProductInfo Name="vivado"/>
|
||||
</Runs>
|
||||
|
||||
15
synth/filter_vivado.runs/.jobs/vrs_config_27.xml
Normal file
15
synth/filter_vivado.runs/.jobs/vrs_config_27.xml
Normal file
@ -0,0 +1,15 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Run Id="impl_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
|
||||
<Parent Id="synth_1"/>
|
||||
</Run>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
<ProductInfo Name="vivado"/>
|
||||
</Runs>
|
||||
|
||||
12
synth/filter_vivado.runs/.jobs/vrs_config_28.xml
Normal file
12
synth/filter_vivado.runs/.jobs/vrs_config_28.xml
Normal file
@ -0,0 +1,12 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
<ProductInfo Name="vivado"/>
|
||||
</Runs>
|
||||
|
||||
12
synth/filter_vivado.runs/.jobs/vrs_config_29.xml
Normal file
12
synth/filter_vivado.runs/.jobs/vrs_config_29.xml
Normal file
@ -0,0 +1,12 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
<ProductInfo Name="vivado"/>
|
||||
</Runs>
|
||||
|
||||
12
synth/filter_vivado.runs/.jobs/vrs_config_30.xml
Normal file
12
synth/filter_vivado.runs/.jobs/vrs_config_30.xml
Normal file
@ -0,0 +1,12 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
<ProductInfo Name="vivado"/>
|
||||
</Runs>
|
||||
|
||||
12
synth/filter_vivado.runs/.jobs/vrs_config_31.xml
Normal file
12
synth/filter_vivado.runs/.jobs/vrs_config_31.xml
Normal file
@ -0,0 +1,12 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
<ProductInfo Name="vivado"/>
|
||||
</Runs>
|
||||
|
||||
12
synth/filter_vivado.runs/.jobs/vrs_config_32.xml
Normal file
12
synth/filter_vivado.runs/.jobs/vrs_config_32.xml
Normal file
@ -0,0 +1,12 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="impl_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
<ProductInfo Name="vivado"/>
|
||||
</Runs>
|
||||
|
||||
12
synth/filter_vivado.runs/.jobs/vrs_config_33.xml
Normal file
12
synth/filter_vivado.runs/.jobs/vrs_config_33.xml
Normal file
@ -0,0 +1,12 @@
|
||||
<?xml version="1.0"?>
|
||||
<Runs Version="1" Minor="0">
|
||||
<Run Id="synth_1" LaunchDir="/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
|
||||
<Parameters>
|
||||
<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
|
||||
<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.ignorePathLengthChecks" Val="true" Type="bool"/>
|
||||
<Parameter Name="general.shortenLongPath" Val="true" Type="bool"/>
|
||||
</Parameters>
|
||||
<ProductInfo Name="vivado"/>
|
||||
</Runs>
|
||||
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command=".planAhead." Owner="veronikaplevacova" Host="" Pid="50397">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command=".planAhead." Owner="veronikaplevacova" Host="" Pid="50397">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command=".planAhead." Owner="veronikaplevacova" Host="" Pid="50397">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command=".planAhead." Owner="veronikaplevacova" Host="" Pid="50397">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command=".planAhead." Owner="veronikaplevacova" Host="" Pid="50397">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
@ -1,25 +1,50 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="29770" HostCore="4" HostMemory="3812172">
|
||||
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="58729" HostCore="4" HostMemory="3812172">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="35112" HostCore="4" HostMemory="3812172">
|
||||
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="62326" HostCore="4" HostMemory="3812172">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="39451" HostCore="4" HostMemory="3812172">
|
||||
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="68175" HostCore="4" HostMemory="3812172">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="44480" HostCore="4" HostMemory="3812172">
|
||||
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="87731" HostCore="4" HostMemory="3812172">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="50339" HostCore="4" HostMemory="3812172">
|
||||
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="95119" HostCore="4" HostMemory="3812172">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="103405" HostCore="4" HostMemory="3812172">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="106328" HostCore="4" HostMemory="3812172">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="109573" HostCore="4" HostMemory="3812172">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="147902" HostCore="4" HostMemory="3812172">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="19237" HostCore="4" HostMemory="3812160">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
@ -1,270 +0,0 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
// GLOBAL VARIABLES
|
||||
var ISEShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var ISERunDir = "";
|
||||
var ISELogFile = "runme.log";
|
||||
var ISELogFileStr = null;
|
||||
var ISELogEcho = true;
|
||||
var ISEOldVersionWSH = false;
|
||||
|
||||
|
||||
|
||||
// BOOTSTRAP
|
||||
ISEInit();
|
||||
|
||||
|
||||
|
||||
//
|
||||
// ISE FUNCTIONS
|
||||
//
|
||||
function ISEInit() {
|
||||
|
||||
// 1. RUN DIR setup
|
||||
var ISEScrFP = WScript.ScriptFullName;
|
||||
var ISEScrN = WScript.ScriptName;
|
||||
ISERunDir =
|
||||
ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
|
||||
|
||||
// 2. LOG file setup
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
// 3. LOG echo?
|
||||
var ISEScriptArgs = WScript.Arguments;
|
||||
for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
|
||||
if ( ISEScriptArgs(loopi) == "-quiet" ) {
|
||||
ISELogEcho = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// 4. WSH version check
|
||||
var ISEOptimalVersionWSH = 5.6;
|
||||
var ISECurrentVersionWSH = WScript.Version;
|
||||
if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
|
||||
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
|
||||
ISEOptimalVersionWSH + " or higher. Downloads" );
|
||||
ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
|
||||
ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
|
||||
ISEStdErr( "" );
|
||||
|
||||
ISEOldVersionWSH = true;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEStep( ISEProg, ISEArgs ) {
|
||||
|
||||
// CHECK for a STOP FILE
|
||||
if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
|
||||
ISEStdErr( "" );
|
||||
ISEStdErr( "*** Halting run - EA reset detected ***" );
|
||||
ISEStdErr( "" );
|
||||
WScript.Quit( 1 );
|
||||
}
|
||||
|
||||
// WRITE STEP HEADER to LOG
|
||||
ISEStdOut( "" );
|
||||
ISEStdOut( "*** Running " + ISEProg );
|
||||
ISEStdOut( " with args " + ISEArgs );
|
||||
ISEStdOut( "" );
|
||||
|
||||
// LAUNCH!
|
||||
var ISEExitCode = ISEExec( ISEProg, ISEArgs );
|
||||
if ( ISEExitCode != 0 ) {
|
||||
WScript.Quit( ISEExitCode );
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
function ISEExec( ISEProg, ISEArgs ) {
|
||||
|
||||
var ISEStep = ISEProg;
|
||||
if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
|
||||
ISEProg += ".bat";
|
||||
}
|
||||
|
||||
var ISECmdLine = ISEProg + " " + ISEArgs;
|
||||
var ISEExitCode = 1;
|
||||
|
||||
if ( ISEOldVersionWSH ) { // WSH 5.1
|
||||
|
||||
// BEGIN file creation
|
||||
ISETouchFile( ISEStep, "begin" );
|
||||
|
||||
// LAUNCH!
|
||||
ISELogFileStr.Close();
|
||||
ISECmdLine =
|
||||
"%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
|
||||
ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
|
||||
ISELogFileStr = ISEOpenFile( ISELogFile );
|
||||
|
||||
} else { // WSH 5.6
|
||||
|
||||
// LAUNCH!
|
||||
ISEShell.CurrentDirectory = ISERunDir;
|
||||
|
||||
// Redirect STDERR to STDOUT
|
||||
ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
|
||||
var ISEProcess = ISEShell.Exec( ISECmdLine );
|
||||
|
||||
// BEGIN file creation
|
||||
var wbemFlagReturnImmediately = 0x10;
|
||||
var wbemFlagForwardOnly = 0x20;
|
||||
var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
|
||||
var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
|
||||
var NOC = 0;
|
||||
var NOLP = 0;
|
||||
var TPM = 0;
|
||||
var cpuInfos = new Enumerator(processor);
|
||||
for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
|
||||
var cpuInfo = cpuInfos.item();
|
||||
NOC += cpuInfo.NumberOfCores;
|
||||
NOLP += cpuInfo.NumberOfLogicalProcessors;
|
||||
}
|
||||
var csInfos = new Enumerator(computerSystem);
|
||||
for(;!csInfos.atEnd(); csInfos.moveNext()) {
|
||||
var csInfo = csInfos.item();
|
||||
TPM += csInfo.TotalPhysicalMemory;
|
||||
}
|
||||
|
||||
var ISEHOSTCORE = NOLP
|
||||
var ISEMEMTOTAL = TPM
|
||||
|
||||
var ISENetwork = WScript.CreateObject( "WScript.Network" );
|
||||
var ISEHost = ISENetwork.ComputerName;
|
||||
var ISEUser = ISENetwork.UserName;
|
||||
var ISEPid = ISEProcess.ProcessID;
|
||||
var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
|
||||
ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
|
||||
ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
|
||||
ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
|
||||
"\" Owner=\"" + ISEUser +
|
||||
"\" Host=\"" + ISEHost +
|
||||
"\" Pid=\"" + ISEPid +
|
||||
"\" HostCore=\"" + ISEHOSTCORE +
|
||||
"\" HostMemory=\"" + ISEMEMTOTAL +
|
||||
"\">" );
|
||||
ISEBeginFile.WriteLine( " </Process>" );
|
||||
ISEBeginFile.WriteLine( "</ProcessHandle>" );
|
||||
ISEBeginFile.Close();
|
||||
|
||||
var ISEOutStr = ISEProcess.StdOut;
|
||||
var ISEErrStr = ISEProcess.StdErr;
|
||||
|
||||
// WAIT for ISEStep to finish
|
||||
while ( ISEProcess.Status == 0 ) {
|
||||
|
||||
// dump stdout then stderr - feels a little arbitrary
|
||||
while ( !ISEOutStr.AtEndOfStream ) {
|
||||
ISEStdOut( ISEOutStr.ReadLine() );
|
||||
}
|
||||
|
||||
WScript.Sleep( 100 );
|
||||
}
|
||||
|
||||
ISEExitCode = ISEProcess.ExitCode;
|
||||
}
|
||||
|
||||
ISELogFileStr.Close();
|
||||
|
||||
// END/ERROR file creation
|
||||
if ( ISEExitCode != 0 ) {
|
||||
ISETouchFile( ISEStep, "error" );
|
||||
|
||||
} else {
|
||||
ISETouchFile( ISEStep, "end" );
|
||||
}
|
||||
|
||||
return ISEExitCode;
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// UTILITIES
|
||||
//
|
||||
function ISEStdOut( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdOut.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISEStdErr( ISELine ) {
|
||||
|
||||
ISELogFileStr.WriteLine( ISELine );
|
||||
|
||||
if ( ISELogEcho ) {
|
||||
WScript.StdErr.WriteLine( ISELine );
|
||||
}
|
||||
}
|
||||
|
||||
function ISETouchFile( ISERoot, ISEStatus ) {
|
||||
|
||||
var ISETFile =
|
||||
ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
|
||||
ISETFile.Close();
|
||||
}
|
||||
|
||||
function ISEOpenFile( ISEFilename ) {
|
||||
|
||||
// This function has been updated to deal with a problem seen in CR #870871.
|
||||
// In that case the user runs a script that runs impl_1, and then turns around
|
||||
// and runs impl_1 -to_step write_bitstream. That second run takes place in
|
||||
// the same directory, which means we may hit some of the same files, and in
|
||||
// particular, we will open the runme.log file. Even though this script closes
|
||||
// the file (now), we see cases where a subsequent attempt to open the file
|
||||
// fails. Perhaps the OS is slow to release the lock, or the disk comes into
|
||||
// play? In any case, we try to work around this by first waiting if the file
|
||||
// is already there for an arbitrary 5 seconds. Then we use a try-catch block
|
||||
// and try to open the file 10 times with a one second delay after each attempt.
|
||||
// Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
|
||||
// If there is an unrecognized exception when trying to open the file, we output
|
||||
// an error message and write details to an exception.log file.
|
||||
var ISEFullPath = ISERunDir + "/" + ISEFilename;
|
||||
if (ISEFileSys.FileExists(ISEFullPath)) {
|
||||
// File is already there. This could be a problem. Wait in case it is still in use.
|
||||
WScript.Sleep(5000);
|
||||
}
|
||||
var i;
|
||||
for (i = 0; i < 10; ++i) {
|
||||
try {
|
||||
return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
|
||||
} catch (exception) {
|
||||
var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
|
||||
if (error_code == 52) { // 52 is bad file name or number.
|
||||
// Wait a second and try again.
|
||||
WScript.Sleep(1000);
|
||||
continue;
|
||||
} else {
|
||||
WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
var exceptionFilePath = ISERunDir + "/exception.log";
|
||||
if (!ISEFileSys.FileExists(exceptionFilePath)) {
|
||||
WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
|
||||
var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
|
||||
exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
|
||||
exceptionFile.WriteLine("\tException name: " + exception.name);
|
||||
exceptionFile.WriteLine("\tException error code: " + error_code);
|
||||
exceptionFile.WriteLine("\tException message: " + exception.message);
|
||||
exceptionFile.Close();
|
||||
}
|
||||
throw exception;
|
||||
}
|
||||
}
|
||||
}
|
||||
// If we reached this point, we failed to open the file after 10 attempts.
|
||||
// We need to error out.
|
||||
WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
|
||||
WScript.Quit(1);
|
||||
}
|
||||
@ -1,85 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# ISEWrap.sh: Vivado Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
cmd_exists()
|
||||
{
|
||||
command -v "$1" >/dev/null 2>&1
|
||||
}
|
||||
|
||||
HD_LOG=$1
|
||||
shift
|
||||
|
||||
# CHECK for a STOP FILE
|
||||
if [ -f .stop.rst ]
|
||||
then
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Halting run - EA reset detected ***" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
exit 1
|
||||
fi
|
||||
|
||||
ISE_STEP=$1
|
||||
shift
|
||||
|
||||
# WRITE STEP HEADER to LOG
|
||||
echo "" >> $HD_LOG
|
||||
echo "*** Running $ISE_STEP" >> $HD_LOG
|
||||
echo " with args $@" >> $HD_LOG
|
||||
echo "" >> $HD_LOG
|
||||
|
||||
# LAUNCH!
|
||||
$ISE_STEP "$@" >> $HD_LOG 2>&1 &
|
||||
|
||||
# BEGIN file creation
|
||||
ISE_PID=$!
|
||||
|
||||
HostNameFile=/proc/sys/kernel/hostname
|
||||
if cmd_exists hostname
|
||||
then
|
||||
ISE_HOST=$(hostname)
|
||||
elif cmd_exists uname
|
||||
then
|
||||
ISE_HOST=$(uname -n)
|
||||
elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
|
||||
then
|
||||
ISE_HOST=$(cat $HostNameFile)
|
||||
elif [ X != X$HOSTNAME ]
|
||||
then
|
||||
ISE_HOST=$HOSTNAME #bash
|
||||
else
|
||||
ISE_HOST=$HOST #csh
|
||||
fi
|
||||
|
||||
ISE_USER=$USER
|
||||
|
||||
ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
|
||||
ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
|
||||
|
||||
ISE_BEGINFILE=.$ISE_STEP.begin.rst
|
||||
/bin/touch $ISE_BEGINFILE
|
||||
echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
|
||||
echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
|
||||
echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
|
||||
echo " </Process>" >> $ISE_BEGINFILE
|
||||
echo "</ProcessHandle>" >> $ISE_BEGINFILE
|
||||
|
||||
# WAIT for ISEStep to finish
|
||||
wait $ISE_PID
|
||||
|
||||
# END/ERROR file creation
|
||||
RETVAL=$?
|
||||
if [ $RETVAL -eq 0 ]
|
||||
then
|
||||
/bin/touch .$ISE_STEP.end.rst
|
||||
else
|
||||
/bin/touch .$ISE_STEP.error.rst
|
||||
fi
|
||||
|
||||
exit $RETVAL
|
||||
|
||||
@ -1,10 +0,0 @@
|
||||
-------------------------------------
|
||||
| Tool Version : Vivado v.2023.2
|
||||
| Date : Sun Dec 3 21:17:35 2023
|
||||
| Host : veronika-swiftsf11433
|
||||
| Design : design_1
|
||||
| Device : xc7k160t-ffv676-1--
|
||||
-------------------------------------
|
||||
|
||||
For more information on clockInfo.txt clock routing debug file see https://support.xilinx.com/s/article/000035660?language=en_US
|
||||
|
||||
@ -1,301 +0,0 @@
|
||||
#
|
||||
# Report generation script generated by Vivado
|
||||
#
|
||||
|
||||
proc create_report { reportName command } {
|
||||
set status "."
|
||||
append status $reportName ".fail"
|
||||
if { [file exists $status] } {
|
||||
eval file delete [glob $status]
|
||||
}
|
||||
send_msg_id runtcl-4 info "Executing : $command"
|
||||
set retval [eval catch { $command } msg]
|
||||
if { $retval != 0 } {
|
||||
set fp [open $status w]
|
||||
close $fp
|
||||
send_msg_id runtcl-5 warning "$msg"
|
||||
}
|
||||
}
|
||||
namespace eval ::optrace {
|
||||
variable script "/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter.tcl"
|
||||
variable category "vivado_impl"
|
||||
}
|
||||
|
||||
# Try to connect to running dispatch if we haven't done so already.
|
||||
# This code assumes that the Tcl interpreter is not using threads,
|
||||
# since the ::dispatch::connected variable isn't mutex protected.
|
||||
if {![info exists ::dispatch::connected]} {
|
||||
namespace eval ::dispatch {
|
||||
variable connected false
|
||||
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
|
||||
set result "true"
|
||||
if {[catch {
|
||||
if {[lsearch -exact [package names] DispatchTcl] < 0} {
|
||||
set result [load librdi_cd_clienttcl[info sharedlibextension]]
|
||||
}
|
||||
if {$result eq "false"} {
|
||||
puts "WARNING: Could not load dispatch client library"
|
||||
}
|
||||
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
|
||||
if { $connect_id eq "" } {
|
||||
puts "WARNING: Could not initialize dispatch client"
|
||||
} else {
|
||||
puts "INFO: Dispatch client connection id - $connect_id"
|
||||
set connected true
|
||||
}
|
||||
} catch_res]} {
|
||||
puts "WARNING: failed to connect to dispatch server - $catch_res"
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if {$::dispatch::connected} {
|
||||
# Remove the dummy proc if it exists.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
|
||||
rename ::OPTRACE ""
|
||||
}
|
||||
proc ::OPTRACE { task action {tags {} } } {
|
||||
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
|
||||
}
|
||||
# dispatch is generic. We specifically want to attach logging.
|
||||
::vitis_log::connect_client
|
||||
} else {
|
||||
# Add dummy proc if it doesn't exist.
|
||||
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
|
||||
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
|
||||
# Do nothing
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
proc start_step { step } {
|
||||
set stopFile ".stop.rst"
|
||||
if {[file isfile .stop.rst]} {
|
||||
puts ""
|
||||
puts "*** Halting run - EA reset detected ***"
|
||||
puts ""
|
||||
puts ""
|
||||
return -code error
|
||||
}
|
||||
set beginFile ".$step.begin.rst"
|
||||
set platform "$::tcl_platform(platform)"
|
||||
set user "$::tcl_platform(user)"
|
||||
set pid [pid]
|
||||
set host ""
|
||||
if { [string equal $platform unix] } {
|
||||
if { [info exist ::env(HOSTNAME)] } {
|
||||
set host $::env(HOSTNAME)
|
||||
} elseif { [info exist ::env(HOST)] } {
|
||||
set host $::env(HOST)
|
||||
}
|
||||
} else {
|
||||
if { [info exist ::env(COMPUTERNAME)] } {
|
||||
set host $::env(COMPUTERNAME)
|
||||
}
|
||||
}
|
||||
set ch [open $beginFile w]
|
||||
puts $ch "<?xml version=\"1.0\"?>"
|
||||
puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
|
||||
puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
|
||||
puts $ch " </Process>"
|
||||
puts $ch "</ProcessHandle>"
|
||||
close $ch
|
||||
}
|
||||
|
||||
proc end_step { step } {
|
||||
set endFile ".$step.end.rst"
|
||||
set ch [open $endFile w]
|
||||
close $ch
|
||||
}
|
||||
|
||||
proc step_failed { step } {
|
||||
set endFile ".$step.error.rst"
|
||||
set ch [open $endFile w]
|
||||
close $ch
|
||||
OPTRACE "impl_1" END { }
|
||||
}
|
||||
|
||||
|
||||
OPTRACE "impl_1" START { ROLLUP_1 }
|
||||
OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
|
||||
start_step init_design
|
||||
set ACTIVE_STEP init_design
|
||||
set rc [catch {
|
||||
create_msg_db init_design.pb
|
||||
set_param chipscope.maxJobs 1
|
||||
set_param runs.launchOptions { -jobs 2 }
|
||||
OPTRACE "create in-memory project" START { }
|
||||
create_project -in_memory -part xc7k160tffv676-1
|
||||
set_property design_mode GateLvl [current_fileset]
|
||||
set_param project.singleFileAddWarning.threshold 0
|
||||
OPTRACE "create in-memory project" END { }
|
||||
OPTRACE "set parameters" START { }
|
||||
set_property webtalk.parent_dir /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.cache/wt [current_project]
|
||||
set_property parent.project_path /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.xpr [current_project]
|
||||
set_property ip_output_repo /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.cache/ip [current_project]
|
||||
set_property ip_cache_permissions {read write} [current_project]
|
||||
OPTRACE "set parameters" END { }
|
||||
OPTRACE "add files" START { }
|
||||
add_files -quiet /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/synth_1/filter.dcp
|
||||
OPTRACE "read constraints: implementation" START { }
|
||||
read_xdc /home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc
|
||||
OPTRACE "read constraints: implementation" END { }
|
||||
OPTRACE "read constraints: implementation_pre" START { }
|
||||
OPTRACE "read constraints: implementation_pre" END { }
|
||||
OPTRACE "add files" END { }
|
||||
OPTRACE "link_design" START { }
|
||||
link_design -top filter -part xc7k160tffv676-1
|
||||
OPTRACE "link_design" END { }
|
||||
OPTRACE "gray box cells" START { }
|
||||
OPTRACE "gray box cells" END { }
|
||||
OPTRACE "init_design_reports" START { REPORT }
|
||||
OPTRACE "init_design_reports" END { }
|
||||
OPTRACE "init_design_write_hwdef" START { }
|
||||
OPTRACE "init_design_write_hwdef" END { }
|
||||
close_msg_db -file init_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed init_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step init_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "Phase: Init Design" END { }
|
||||
OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO }
|
||||
start_step opt_design
|
||||
set ACTIVE_STEP opt_design
|
||||
set rc [catch {
|
||||
create_msg_db opt_design.pb
|
||||
OPTRACE "read constraints: opt_design" START { }
|
||||
OPTRACE "read constraints: opt_design" END { }
|
||||
OPTRACE "opt_design" START { }
|
||||
opt_design
|
||||
OPTRACE "opt_design" END { }
|
||||
OPTRACE "read constraints: opt_design_post" START { }
|
||||
OPTRACE "read constraints: opt_design_post" END { }
|
||||
OPTRACE "opt_design reports" START { REPORT }
|
||||
create_report "impl_1_opt_report_drc_0" "report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx"
|
||||
create_report "impl_1_opt_report_timing_summary_0" "report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_opted.rpt -pb filter_timing_summary_opted.pb -rpx filter_timing_summary_opted.rpx"
|
||||
OPTRACE "opt_design reports" END { }
|
||||
OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT }
|
||||
write_checkpoint -force filter_opt.dcp
|
||||
OPTRACE "Opt Design: write_checkpoint" END { }
|
||||
close_msg_db -file opt_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed opt_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step opt_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "Phase: Opt Design" END { }
|
||||
OPTRACE "Phase: Place Design" START { ROLLUP_AUTO }
|
||||
start_step place_design
|
||||
set ACTIVE_STEP place_design
|
||||
set rc [catch {
|
||||
create_msg_db place_design.pb
|
||||
OPTRACE "read constraints: place_design" START { }
|
||||
OPTRACE "read constraints: place_design" END { }
|
||||
if { [llength [get_debug_cores -quiet] ] > 0 } {
|
||||
OPTRACE "implement_debug_core" START { }
|
||||
implement_debug_core
|
||||
OPTRACE "implement_debug_core" END { }
|
||||
}
|
||||
OPTRACE "place_design" START { }
|
||||
place_design
|
||||
OPTRACE "place_design" END { }
|
||||
OPTRACE "read constraints: place_design_post" START { }
|
||||
OPTRACE "read constraints: place_design_post" END { }
|
||||
OPTRACE "place_design reports" START { REPORT }
|
||||
create_report "impl_1_place_report_io_0" "report_io -file filter_io_placed.rpt"
|
||||
create_report "impl_1_place_report_utilization_0" "report_utilization -file filter_utilization_placed.rpt -pb filter_utilization_placed.pb"
|
||||
create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file filter_control_sets_placed.rpt"
|
||||
OPTRACE "place_design reports" END { }
|
||||
OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT }
|
||||
write_checkpoint -force filter_placed.dcp
|
||||
OPTRACE "Place Design: write_checkpoint" END { }
|
||||
close_msg_db -file place_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed place_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step place_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "Phase: Place Design" END { }
|
||||
OPTRACE "Phase: Physical Opt Design" START { ROLLUP_AUTO }
|
||||
start_step phys_opt_design
|
||||
set ACTIVE_STEP phys_opt_design
|
||||
set rc [catch {
|
||||
create_msg_db phys_opt_design.pb
|
||||
OPTRACE "read constraints: phys_opt_design" START { }
|
||||
OPTRACE "read constraints: phys_opt_design" END { }
|
||||
OPTRACE "phys_opt_design" START { }
|
||||
phys_opt_design
|
||||
OPTRACE "phys_opt_design" END { }
|
||||
OPTRACE "read constraints: phys_opt_design_post" START { }
|
||||
OPTRACE "read constraints: phys_opt_design_post" END { }
|
||||
OPTRACE "phys_opt_design report" START { REPORT }
|
||||
OPTRACE "phys_opt_design report" END { }
|
||||
OPTRACE "Post-Place Phys Opt Design: write_checkpoint" START { CHECKPOINT }
|
||||
write_checkpoint -force filter_physopt.dcp
|
||||
OPTRACE "Post-Place Phys Opt Design: write_checkpoint" END { }
|
||||
close_msg_db -file phys_opt_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
step_failed phys_opt_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step phys_opt_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "Phase: Physical Opt Design" END { }
|
||||
OPTRACE "Phase: Route Design" START { ROLLUP_AUTO }
|
||||
start_step route_design
|
||||
set ACTIVE_STEP route_design
|
||||
set rc [catch {
|
||||
create_msg_db route_design.pb
|
||||
OPTRACE "read constraints: route_design" START { }
|
||||
OPTRACE "read constraints: route_design" END { }
|
||||
OPTRACE "route_design" START { }
|
||||
route_design
|
||||
OPTRACE "route_design" END { }
|
||||
OPTRACE "read constraints: route_design_post" START { }
|
||||
OPTRACE "read constraints: route_design_post" END { }
|
||||
OPTRACE "route_design reports" START { REPORT }
|
||||
create_report "impl_1_route_report_drc_0" "report_drc -file filter_drc_routed.rpt -pb filter_drc_routed.pb -rpx filter_drc_routed.rpx"
|
||||
create_report "impl_1_route_report_methodology_0" "report_methodology -file filter_methodology_drc_routed.rpt -pb filter_methodology_drc_routed.pb -rpx filter_methodology_drc_routed.rpx"
|
||||
create_report "impl_1_route_report_power_0" "report_power -file filter_power_routed.rpt -pb filter_power_summary_routed.pb -rpx filter_power_routed.rpx"
|
||||
create_report "impl_1_route_report_route_status_0" "report_route_status -file filter_route_status.rpt -pb filter_route_status.pb"
|
||||
create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_routed.rpt -pb filter_timing_summary_routed.pb -rpx filter_timing_summary_routed.rpx -warn_on_violation "
|
||||
create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file filter_incremental_reuse_routed.rpt"
|
||||
create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file filter_clock_utilization_routed.rpt"
|
||||
create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file filter_bus_skew_routed.rpt -pb filter_bus_skew_routed.pb -rpx filter_bus_skew_routed.rpx"
|
||||
OPTRACE "route_design reports" END { }
|
||||
OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT }
|
||||
write_checkpoint -force filter_routed.dcp
|
||||
OPTRACE "Route Design: write_checkpoint" END { }
|
||||
OPTRACE "route_design misc" START { }
|
||||
close_msg_db -file route_design.pb
|
||||
} RESULT]
|
||||
if {$rc} {
|
||||
OPTRACE "route_design write_checkpoint" START { CHECKPOINT }
|
||||
OPTRACE "route_design write_checkpoint" END { }
|
||||
write_checkpoint -force filter_routed_error.dcp
|
||||
step_failed route_design
|
||||
return -code error $RESULT
|
||||
} else {
|
||||
end_step route_design
|
||||
unset ACTIVE_STEP
|
||||
}
|
||||
|
||||
OPTRACE "route_design misc" END { }
|
||||
OPTRACE "Phase: Route Design" END { }
|
||||
OPTRACE "impl_1" END { }
|
||||
File diff suppressed because it is too large
Load Diff
446
synth/filter_vivado.runs/impl_1/filter_147960.backup.vdi
Normal file
446
synth/filter_vivado.runs/impl_1/filter_147960.backup.vdi
Normal file
@ -0,0 +1,446 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Mon Dec 4 22:37:41 2023
|
||||
# Process ID: 147960
|
||||
# Current directory: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1
|
||||
# Command line: vivado -log filter.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source filter.tcl -notrace
|
||||
# Log file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter.vdi
|
||||
# Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/vivado.jou
|
||||
# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2785.745 MHz, CPU Physical cores: 4, Host memory: 3903 MB
|
||||
#-----------------------------------------------------------
|
||||
source filter.tcl -notrace
|
||||
create_project: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1309.508 ; gain = 0.023 ; free physical = 428 ; free virtual = 5957
|
||||
Command: link_design -top filter -part xc7k160tffv676-1
|
||||
Design is defaulting to srcset: sources_1
|
||||
Design is defaulting to constrset: constrs_1
|
||||
INFO: [Device 21-403] Loading part xc7k160tffv676-1
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1630.383 ; gain = 0.000 ; free physical = 119 ; free virtual = 5562
|
||||
INFO: [Netlist 29-17] Analyzing 781 Unisim elements for replacement
|
||||
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
|
||||
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||
Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc]
|
||||
WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13]
|
||||
Finished Parsing XDC File [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc]
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1748.727 ; gain = 0.000 ; free physical = 123 ; free virtual = 5292
|
||||
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||
No Unisim elements were transformed.
|
||||
|
||||
7 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
link_design completed successfully
|
||||
link_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 1751.730 ; gain = 442.223 ; free physical = 167 ; free virtual = 5285
|
||||
Command: opt_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t'
|
||||
Running DRC as a precondition to command opt_design
|
||||
|
||||
Starting DRC Task
|
||||
INFO: [DRC 23-27] Running DRC with 4 threads
|
||||
INFO: [Project 1-461] DRC finished with 0 Errors
|
||||
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1802.523 ; gain = 50.793 ; free physical = 135 ; free virtual = 5244
|
||||
|
||||
Starting Cache Timing Information Task
|
||||
WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13]
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Ending Cache Timing Information Task | Checksum: c501db34
|
||||
|
||||
Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 2321.430 ; gain = 518.906 ; free physical = 188 ; free virtual = 4846
|
||||
|
||||
Starting Logic Optimization Task
|
||||
|
||||
Phase 1 Initialization
|
||||
|
||||
Phase 1.1 Core Generation And Design Setup
|
||||
Phase 1.1 Core Generation And Design Setup | Checksum: c501db34
|
||||
|
||||
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2626.180 ; gain = 0.000 ; free physical = 124 ; free virtual = 4604
|
||||
|
||||
Phase 1.2 Setup Constraints And Sort Netlist
|
||||
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: c501db34
|
||||
|
||||
Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2626.180 ; gain = 0.000 ; free physical = 152 ; free virtual = 4603
|
||||
Phase 1 Initialization | Checksum: c501db34
|
||||
|
||||
Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2626.180 ; gain = 0.000 ; free physical = 164 ; free virtual = 4604
|
||||
|
||||
Phase 2 Timer Update And Timing Data Collection
|
||||
|
||||
Phase 2.1 Timer Update
|
||||
Phase 2.1 Timer Update | Checksum: c501db34
|
||||
|
||||
Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2626.180 ; gain = 0.000 ; free physical = 199 ; free virtual = 4603
|
||||
|
||||
Phase 2.2 Timing Data Collection
|
||||
Phase 2.2 Timing Data Collection | Checksum: c501db34
|
||||
|
||||
Time (s): cpu = 00:00:00.78 ; elapsed = 00:00:00.4 . Memory (MB): peak = 2626.180 ; gain = 0.000 ; free physical = 185 ; free virtual = 4599
|
||||
Phase 2 Timer Update And Timing Data Collection | Checksum: c501db34
|
||||
|
||||
Time (s): cpu = 00:00:00.79 ; elapsed = 00:00:00.4 . Memory (MB): peak = 2626.180 ; gain = 0.000 ; free physical = 185 ; free virtual = 4599
|
||||
|
||||
Phase 3 Retarget
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
INFO: [Opt 31-49] Retargeted 0 cell(s).
|
||||
Phase 3 Retarget | Checksum: a3d35512
|
||||
|
||||
Time (s): cpu = 00:00:00.96 ; elapsed = 00:00:00.68 . Memory (MB): peak = 2626.180 ; gain = 0.000 ; free physical = 133 ; free virtual = 4583
|
||||
Retarget | Checksum: a3d35512
|
||||
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells
|
||||
|
||||
Phase 4 Constant propagation
|
||||
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||
Phase 4 Constant propagation | Checksum: e34d5785
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.82 . Memory (MB): peak = 2626.180 ; gain = 0.000 ; free physical = 151 ; free virtual = 4576
|
||||
Constant propagation | Checksum: e34d5785
|
||||
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
|
||||
|
||||
Phase 5 Sweep
|
||||
Phase 5 Sweep | Checksum: e123e2a4
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2626.180 ; gain = 0.000 ; free physical = 137 ; free virtual = 4575
|
||||
Sweep | Checksum: e123e2a4
|
||||
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
|
||||
|
||||
Phase 6 BUFG optimization
|
||||
Phase 6 BUFG optimization | Checksum: e123e2a4
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2658.195 ; gain = 32.016 ; free physical = 127 ; free virtual = 4574
|
||||
BUFG optimization | Checksum: e123e2a4
|
||||
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
|
||||
|
||||
Phase 7 Shift Register Optimization
|
||||
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
|
||||
Phase 7 Shift Register Optimization | Checksum: e123e2a4
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2658.195 ; gain = 32.016 ; free physical = 127 ; free virtual = 4574
|
||||
Shift Register Optimization | Checksum: e123e2a4
|
||||
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
|
||||
|
||||
Phase 8 Post Processing Netlist
|
||||
Phase 8 Post Processing Netlist | Checksum: e123e2a4
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2658.195 ; gain = 32.016 ; free physical = 126 ; free virtual = 4578
|
||||
Post Processing Netlist | Checksum: e123e2a4
|
||||
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
|
||||
|
||||
Phase 9 Finalization
|
||||
|
||||
Phase 9.1 Finalizing Design Cores and Updating Shapes
|
||||
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 198845eae
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2658.195 ; gain = 32.016 ; free physical = 232 ; free virtual = 4593
|
||||
|
||||
Phase 9.2 Verifying Netlist Connectivity
|
||||
|
||||
Starting Connectivity Check Task
|
||||
|
||||
Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2658.195 ; gain = 0.000 ; free physical = 230 ; free virtual = 4592
|
||||
Phase 9.2 Verifying Netlist Connectivity | Checksum: 198845eae
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2658.195 ; gain = 32.016 ; free physical = 230 ; free virtual = 4592
|
||||
Phase 9 Finalization | Checksum: 198845eae
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2658.195 ; gain = 32.016 ; free physical = 230 ; free virtual = 4592
|
||||
Opt_design Change Summary
|
||||
=========================
|
||||
|
||||
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
| Retarget | 0 | 0 | 0 |
|
||||
| Constant propagation | 0 | 0 | 0 |
|
||||
| Sweep | 0 | 0 | 0 |
|
||||
| BUFG optimization | 0 | 0 | 0 |
|
||||
| Shift Register Optimization | 0 | 0 | 0 |
|
||||
| Post Processing Netlist | 0 | 0 | 0 |
|
||||
-------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Ending Logic Optimization Task | Checksum: 198845eae
|
||||
|
||||
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 2658.195 ; gain = 32.016 ; free physical = 230 ; free virtual = 4592
|
||||
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
|
||||
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2658.195 ; gain = 0.000 ; free physical = 230 ; free virtual = 4592
|
||||
|
||||
Starting Power Optimization Task
|
||||
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
|
||||
WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13]
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
Running Vector-less Activity Propagation...
|
||||
|
||||
Finished Running Vector-less Activity Propagation
|
||||
INFO: [Pwropt 34-9] Applying IDT optimizations ...
|
||||
INFO: [Pwropt 34-10] Applying ODC optimizations ...
|
||||
|
||||
|
||||
Starting PowerOpt Patch Enables Task
|
||||
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 36 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
|
||||
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
|
||||
Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 72
|
||||
Ending PowerOpt Patch Enables Task | Checksum: 198845eae
|
||||
|
||||
Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.24 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 174 ; free virtual = 4483
|
||||
Ending Power Optimization Task | Checksum: 198845eae
|
||||
|
||||
Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 2799.070 ; gain = 140.875 ; free physical = 165 ; free virtual = 4482
|
||||
|
||||
Starting Final Cleanup Task
|
||||
Ending Final Cleanup Task | Checksum: 198845eae
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 165 ; free virtual = 4482
|
||||
|
||||
Starting Netlist Obfuscation Task
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 154 ; free virtual = 4480
|
||||
Ending Netlist Obfuscation Task | Checksum: 198845eae
|
||||
|
||||
Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 154 ; free virtual = 4480
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
30 Infos, 3 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||
opt_design completed successfully
|
||||
opt_design: Time (s): cpu = 00:00:48 ; elapsed = 00:00:46 . Memory (MB): peak = 2799.070 ; gain = 1047.340 ; free physical = 144 ; free virtual = 4480
|
||||
INFO: [runtcl-4] Executing : report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx
|
||||
Command: report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx
|
||||
INFO: [IP_Flow 19-234] Refreshing IP repositories
|
||||
INFO: [IP_Flow 19-1704] No user IP repositories specified
|
||||
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/tools/Xilinx/Vivado/2023.2/data/ip'.
|
||||
INFO: [DRC 23-27] Running DRC with 4 threads
|
||||
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_drc_opted.rpt.
|
||||
report_drc completed successfully
|
||||
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file filter_timing_summary_opted.rpt -pb filter_timing_summary_opted.pb -rpx filter_timing_summary_opted.rpx
|
||||
WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13]
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
|
||||
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 4 CPUs
|
||||
WARNING: [Timing 38-242] The property HD.CLK_SRC of clock port "CLK" is not set. In out-of-context mode, this prevents timing estimation for clock delay/skew
|
||||
Resolution: Set the HD.CLK_SRC property of the out-of-context port to the location of the clock buffer instance in the top-level design
|
||||
INFO: [Timing 38-480] Writing timing data to binary archive.
|
||||
Write ShapeDB Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 161 ; free virtual = 4498
|
||||
INFO: [Common 17-1381] The checkpoint '/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter_opt.dcp' has been generated.
|
||||
Command: place_design
|
||||
Attempting to get a license for feature 'Implementation' and/or device 'xc7k160t'
|
||||
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k160t'
|
||||
INFO: [Common 17-83] Releasing license: Implementation
|
||||
INFO: [DRC 23-27] Running DRC with 4 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
Running DRC as a precondition to command place_design
|
||||
INFO: [DRC 23-27] Running DRC with 4 threads
|
||||
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
|
||||
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
|
||||
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 4 CPUs
|
||||
|
||||
Starting Placer Task
|
||||
|
||||
Phase 1 Placer Initialization
|
||||
|
||||
Phase 1.1 Placer Initialization Netlist Sorting
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 135 ; free virtual = 4509
|
||||
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: d8cd780a
|
||||
|
||||
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 136 ; free virtual = 4509
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 135 ; free virtual = 4509
|
||||
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
|
||||
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 8ad34538
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.86 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 186 ; free virtual = 4538
|
||||
|
||||
Phase 1.3 Build Placer Netlist Model
|
||||
Phase 1.3 Build Placer Netlist Model | Checksum: 148eef814
|
||||
|
||||
Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 188 ; free virtual = 4547
|
||||
|
||||
Phase 1.4 Constrain Clocks/Macros
|
||||
Phase 1.4 Constrain Clocks/Macros | Checksum: 148eef814
|
||||
|
||||
Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 188 ; free virtual = 4547
|
||||
Phase 1 Placer Initialization | Checksum: 148eef814
|
||||
|
||||
Time (s): cpu = 00:00:06 ; elapsed = 00:00:03 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 188 ; free virtual = 4546
|
||||
|
||||
Phase 2 Global Placement
|
||||
|
||||
Phase 2.1 Floorplanning
|
||||
Phase 2.1 Floorplanning | Checksum: 1133dee1f
|
||||
|
||||
Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 182 ; free virtual = 4545
|
||||
|
||||
Phase 2.2 Update Timing before SLR Path Opt
|
||||
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1708a7738
|
||||
|
||||
Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 182 ; free virtual = 4545
|
||||
|
||||
Phase 2.3 Post-Processing in Floorplanning
|
||||
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1708a7738
|
||||
|
||||
Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 182 ; free virtual = 4545
|
||||
|
||||
Phase 2.4 Global Placement Core
|
||||
|
||||
Phase 2.4.1 UpdateTiming Before Physical Synthesis
|
||||
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 127fd4737
|
||||
|
||||
Time (s): cpu = 00:00:27 ; elapsed = 00:00:12 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 156 ; free virtual = 4535
|
||||
|
||||
Phase 2.4.2 Physical Synthesis In Placer
|
||||
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 4 LUT instances to create LUTNM shape
|
||||
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
|
||||
INFO: [Physopt 32-1138] End 1 Pass. Optimized 2 nets or LUTs. Breaked 0 LUT, combined 2 existing LUTs and moved 0 existing LUT
|
||||
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
|
||||
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-456] No candidate cells for DSP register optimization found in the design.
|
||||
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-1123] No candidate cells found for Shift Register to Pipeline optimization
|
||||
INFO: [Physopt 32-775] End 2 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-1402] Pass 1: Identified 59 candidate cells for Shift Register optimization.
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 37 nets or cells. Created 73 new cells, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 140 ; free virtual = 4534
|
||||
INFO: [Physopt 32-526] No candidate cells for BRAM register optimization found in the design
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-846] No candidate cells for URAM register optimization found in the design
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
|
||||
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
|
||||
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 140 ; free virtual = 4534
|
||||
|
||||
Summary of Physical Synthesis Optimizations
|
||||
============================================
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| LUT Combining | 0 | 2 | 2 | 0 | 1 | 00:00:00 |
|
||||
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| DSP Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Shift Register | 73 | 0 | 37 | 0 | 1 | 00:00:00 |
|
||||
| BRAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| URAM Register | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
|
||||
| Total | 73 | 2 | 39 | 0 | 9 | 00:00:00 |
|
||||
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 182366011
|
||||
|
||||
Time (s): cpu = 00:00:29 ; elapsed = 00:00:13 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 140 ; free virtual = 4534
|
||||
Phase 2.4 Global Placement Core | Checksum: 1bced18a5
|
||||
|
||||
Time (s): cpu = 00:00:31 ; elapsed = 00:00:13 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 140 ; free virtual = 4534
|
||||
Phase 2 Global Placement | Checksum: 1bced18a5
|
||||
|
||||
Time (s): cpu = 00:00:31 ; elapsed = 00:00:13 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 140 ; free virtual = 4534
|
||||
|
||||
Phase 3 Detail Placement
|
||||
|
||||
Phase 3.1 Commit Multi Column Macros
|
||||
Phase 3.1 Commit Multi Column Macros | Checksum: 1a3664554
|
||||
|
||||
Time (s): cpu = 00:00:33 ; elapsed = 00:00:14 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 139 ; free virtual = 4533
|
||||
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs
|
||||
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1a922434a
|
||||
|
||||
Time (s): cpu = 00:00:36 ; elapsed = 00:00:16 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 138 ; free virtual = 4533
|
||||
|
||||
Phase 3.3 Area Swap Optimization
|
||||
Phase 3.3 Area Swap Optimization | Checksum: 17277ad37
|
||||
|
||||
Time (s): cpu = 00:00:36 ; elapsed = 00:00:16 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 138 ; free virtual = 4533
|
||||
|
||||
Phase 3.4 Pipeline Register Optimization
|
||||
Phase 3.4 Pipeline Register Optimization | Checksum: 210ee07c3
|
||||
|
||||
Time (s): cpu = 00:00:36 ; elapsed = 00:00:16 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 138 ; free virtual = 4533
|
||||
|
||||
Phase 3.5 Fast Optimization
|
||||
Phase 3.5 Fast Optimization | Checksum: 174a33b00
|
||||
|
||||
Time (s): cpu = 00:00:41 ; elapsed = 00:00:18 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 136 ; free virtual = 4531
|
||||
|
||||
Phase 3.6 Small Shape Detail Placement
|
||||
Phase 3.6 Small Shape Detail Placement | Checksum: 1963521b5
|
||||
|
||||
Time (s): cpu = 00:00:44 ; elapsed = 00:00:20 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 123 ; free virtual = 4526
|
||||
|
||||
Phase 3.7 Re-assign LUT pins
|
||||
Phase 3.7 Re-assign LUT pins | Checksum: 11690d3e7
|
||||
|
||||
Time (s): cpu = 00:00:44 ; elapsed = 00:00:20 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 123 ; free virtual = 4525
|
||||
|
||||
Phase 3.8 Pipeline Register Optimization
|
||||
Phase 3.8 Pipeline Register Optimization | Checksum: 193172d63
|
||||
|
||||
Time (s): cpu = 00:00:44 ; elapsed = 00:00:20 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 123 ; free virtual = 4526
|
||||
|
||||
Phase 3.9 Fast Optimization
|
||||
Phase 3.9 Fast Optimization | Checksum: 143f97dd6
|
||||
|
||||
Time (s): cpu = 00:00:50 ; elapsed = 00:00:23 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 122 ; free virtual = 4525
|
||||
Phase 3 Detail Placement | Checksum: 143f97dd6
|
||||
|
||||
Time (s): cpu = 00:00:50 ; elapsed = 00:00:23 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 122 ; free virtual = 4525
|
||||
|
||||
Phase 4 Post Placement Optimization and Clean-Up
|
||||
|
||||
Phase 4.1 Post Commit Optimization
|
||||
WARNING: [Constraints 18-6211] Setting input delay on a clock pin 'CLK' relative to clock 'CLK' defined on the same pin is not supported, ignoring it [/home/veronikaplevacova/Plocha/PCS2/synth/filter.xdc:13]
|
||||
INFO: [Timing 38-35] Done setting XDC timing constraints.
|
||||
|
||||
Phase 4.1.1 Post Placement Optimization
|
||||
Post Placement Optimization Initialization | Checksum: 1cb7827e6
|
||||
|
||||
Phase 4.1.1.1 BUFG Insertion
|
||||
|
||||
Starting Physical Synthesis Task
|
||||
|
||||
Phase 1 Physical Synthesis Initialization
|
||||
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs
|
||||
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=-1.576 | TNS=-25.567 |
|
||||
Phase 1 Physical Synthesis Initialization | Checksum: 11da6909f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.54 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 120 ; free virtual = 4525
|
||||
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
|
||||
Ending Physical Synthesis Task | Checksum: 11da6909f
|
||||
|
||||
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.7 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 120 ; free virtual = 4525
|
||||
Phase 4.1.1.1 BUFG Insertion | Checksum: 1cb7827e6
|
||||
|
||||
Time (s): cpu = 00:00:58 ; elapsed = 00:00:26 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 120 ; free virtual = 4525
|
||||
|
||||
Phase 4.1.1.2 Post Placement Timing Optimization
|
||||
INFO: [Common 17-41] Interrupt caught. Command should exit soon.
|
||||
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1fb5672e7
|
||||
|
||||
Time (s): cpu = 00:01:50 ; elapsed = 00:01:22 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 104 ; free virtual = 4784
|
||||
|
||||
Time (s): cpu = 00:01:50 ; elapsed = 00:01:22 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 102 ; free virtual = 4784
|
||||
Phase 4.1 Post Commit Optimization | Checksum: 1fb5672e7
|
||||
|
||||
Time (s): cpu = 00:01:50 ; elapsed = 00:01:22 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 109 ; free virtual = 4782
|
||||
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1fb5672e7
|
||||
|
||||
Time (s): cpu = 00:01:50 ; elapsed = 00:01:22 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 116 ; free virtual = 4781
|
||||
INFO: [Place 30-491] Placement has been cancelled by the user.
|
||||
Ending Placer Task | Checksum: 10e3da2ff
|
||||
|
||||
Time (s): cpu = 00:01:50 ; elapsed = 00:01:23 . Memory (MB): peak = 2799.070 ; gain = 0.000 ; free physical = 110 ; free virtual = 4780
|
||||
INFO: [Common 17-41] Interrupt caught. Command should exit soon.
|
||||
78 Infos, 6 Warnings, 0 Critical Warnings and 1 Errors encountered.
|
||||
place_design failed
|
||||
INFO: [Common 17-344] 'place_design' was cancelled
|
||||
INFO: [Common 17-344] 'source' was cancelled
|
||||
INFO: [Common 17-206] Exiting Vivado at Mon Dec 4 22:40:30 2023...
|
||||
Binary file not shown.
@ -1,16 +0,0 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
| Date : Sun Dec 3 21:20:44 2023
|
||||
| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux
|
||||
| Command : report_bus_skew -warn_on_violation -file filter_bus_skew_routed.rpt -pb filter_bus_skew_routed.pb -rpx filter_bus_skew_routed.rpx
|
||||
| Design : filter
|
||||
| Device : 7k160t-ffv676
|
||||
| Speed File : -1 PRODUCTION 1.12 2017-02-17
|
||||
| Design State : Routed
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Bus Skew Report
|
||||
|
||||
No bus skew constraints
|
||||
|
||||
Binary file not shown.
@ -1,99 +0,0 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
| Date : Sun Dec 3 21:20:44 2023
|
||||
| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux
|
||||
| Command : report_clock_utilization -file filter_clock_utilization_routed.rpt
|
||||
| Design : filter
|
||||
| Device : 7k160t-ffv676
|
||||
| Speed File : -1 PRODUCTION 1.12 2017-02-17
|
||||
| Design State : Routed
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Clock Utilization Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Clock Primitive Utilization
|
||||
2. Global Clock Resources
|
||||
3. Global Clock Source Details
|
||||
4. Clock Regions: Key Resource Utilization
|
||||
5. Clock Regions : Global Clock Summary
|
||||
|
||||
1. Clock Primitive Utilization
|
||||
------------------------------
|
||||
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
| Type | Used | Available | LOC | Clock Region | Pblock |
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
| BUFGCTRL | 0 | 32 | 0 | 0 | 0 |
|
||||
| BUFH | 0 | 120 | 0 | 0 | 0 |
|
||||
| BUFIO | 0 | 32 | 0 | 0 | 0 |
|
||||
| BUFMR | 0 | 16 | 0 | 0 | 0 |
|
||||
| BUFR | 0 | 32 | 0 | 0 | 0 |
|
||||
| MMCM | 0 | 8 | 0 | 0 | 0 |
|
||||
| PLL | 0 | 8 | 0 | 0 | 0 |
|
||||
+----------+------+-----------+-----+--------------+--------+
|
||||
|
||||
|
||||
2. Global Clock Resources
|
||||
-------------------------
|
||||
|
||||
+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+
|
||||
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
|
||||
+-----------+-----------+-----------------+------------+------+--------------+-------------------+-------------+-----------------+--------------+-------+------------+-----+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
|
||||
|
||||
3. Global Clock Source Details
|
||||
------------------------------
|
||||
|
||||
+-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+
|
||||
| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
|
||||
+-----------+-----------+-----------------+------------+------+--------------+-------------+-----------------+---------------------+--------------+------------+-----+
|
||||
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
|
||||
** Non-Clock Loads column represents cell count of non-clock pin loads
|
||||
|
||||
|
||||
4. Clock Regions: Key Resource Utilization
|
||||
------------------------------------------
|
||||
|
||||
+-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
|
||||
| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
|
||||
| X1Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
|
||||
| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
|
||||
| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
|
||||
| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
|
||||
| X1Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2700 | 0 | 950 | 0 | 80 | 0 | 40 | 0 | 60 |
|
||||
| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2200 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
|
||||
| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 2150 | 0 | 800 | 0 | 50 | 0 | 25 | 0 | 60 |
|
||||
| X0Y4 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2800 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
|
||||
| X1Y4 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2300 | 0 | 850 | 0 | 60 | 0 | 30 | 0 | 60 |
|
||||
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
|
||||
* Global Clock column represents track count; while other columns represents cell counts
|
||||
|
||||
|
||||
5. Clock Regions : Global Clock Summary
|
||||
---------------------------------------
|
||||
|
||||
All Modules
|
||||
+----+----+----+
|
||||
| | X0 | X1 |
|
||||
+----+----+----+
|
||||
| Y4 | 0 | 0 |
|
||||
| Y3 | 0 | 0 |
|
||||
| Y2 | 0 | 0 |
|
||||
| Y1 | 0 | 0 |
|
||||
| Y0 | 0 | 0 |
|
||||
+----+----+----+
|
||||
|
||||
|
||||
|
||||
# Location of IO Primitives which is load of clock spine
|
||||
|
||||
# Location of clock ports
|
||||
@ -1,80 +0,0 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
| Date : Sun Dec 3 21:18:40 2023
|
||||
| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux
|
||||
| Command : report_control_sets -verbose -file filter_control_sets_placed.rpt
|
||||
| Design : filter
|
||||
| Device : xc7k160t
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Control Set Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
2. Histogram
|
||||
3. Flip-Flop Distribution
|
||||
4. Detailed Control Set Information
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+----------------------------------------------------------+-------+
|
||||
| Status | Count |
|
||||
+----------------------------------------------------------+-------+
|
||||
| Total control sets | 2 |
|
||||
| Minimum number of control sets | 2 |
|
||||
| Addition due to synthesis replication | 0 |
|
||||
| Addition due to physical synthesis replication | 0 |
|
||||
| Unused register locations in slices containing registers | 9 |
|
||||
+----------------------------------------------------------+-------+
|
||||
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
|
||||
** Run report_qor_suggestions for automated merging and remapping suggestions
|
||||
|
||||
|
||||
2. Histogram
|
||||
------------
|
||||
|
||||
+--------------------+-------+
|
||||
| Fanout | Count |
|
||||
+--------------------+-------+
|
||||
| Total control sets | 2 |
|
||||
| >= 0 to < 4 | 0 |
|
||||
| >= 4 to < 6 | 1 |
|
||||
| >= 6 to < 8 | 0 |
|
||||
| >= 8 to < 10 | 0 |
|
||||
| >= 10 to < 12 | 0 |
|
||||
| >= 12 to < 14 | 0 |
|
||||
| >= 14 to < 16 | 0 |
|
||||
| >= 16 | 1 |
|
||||
+--------------------+-------+
|
||||
* Control sets can be remapped at either synth_design or opt_design
|
||||
|
||||
|
||||
3. Flip-Flop Distribution
|
||||
-------------------------
|
||||
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
| No | No | No | 4835 | 1097 |
|
||||
| No | No | Yes | 0 | 0 |
|
||||
| No | Yes | No | 4 | 3 |
|
||||
| Yes | No | No | 0 | 0 |
|
||||
| Yes | No | Yes | 0 | 0 |
|
||||
| Yes | Yes | No | 0 | 0 |
|
||||
+--------------+-----------------------+------------------------+-----------------+--------------+
|
||||
|
||||
|
||||
4. Detailed Control Set Information
|
||||
-----------------------------------
|
||||
|
||||
+--------------+---------------+------------------+------------------+----------------+--------------+
|
||||
| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
|
||||
+--------------+---------------+------------------+------------------+----------------+--------------+
|
||||
| CLK | | RESET | 3 | 4 | 1.33 |
|
||||
| CLK | | | 1098 | 4996 | 4.55 |
|
||||
+--------------+---------------+------------------+------------------+----------------+--------------+
|
||||
|
||||
|
||||
Binary file not shown.
@ -1,49 +0,0 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
| Date : Sun Dec 3 21:17:27 2023
|
||||
| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux
|
||||
| Command : report_drc -file filter_drc_opted.rpt -pb filter_drc_opted.pb -rpx filter_drc_opted.rpx
|
||||
| Design : filter
|
||||
| Device : xc7k160tffv676-1
|
||||
| Speed File : -1
|
||||
| Design State : Synthesized
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report DRC
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: design_1
|
||||
Design limits: <entire design considered>
|
||||
Ruledeck: default
|
||||
Max violations: <unlimited>
|
||||
Violations found: 1
|
||||
+----------+----------+-----------------------------------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+----------+----------+-----------------------------------------------------+------------+
|
||||
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
|
||||
+----------+----------+-----------------------------------------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
CFGBVS-1#1 Warning
|
||||
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
|
||||
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
|
||||
|
||||
set_property CFGBVS value1 [current_design]
|
||||
#where value1 is either VCCO or GND
|
||||
|
||||
set_property CONFIG_VOLTAGE value2 [current_design]
|
||||
#where value2 is the voltage provided to configuration bank 0
|
||||
|
||||
Refer to the device configuration user guide for more information.
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
@ -1,49 +0,0 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
| Date : Sun Dec 3 21:20:35 2023
|
||||
| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux
|
||||
| Command : report_drc -file filter_drc_routed.rpt -pb filter_drc_routed.pb -rpx filter_drc_routed.rpx
|
||||
| Design : filter
|
||||
| Device : xc7k160tffv676-1
|
||||
| Speed File : -1
|
||||
| Design State : Fully Routed
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Report DRC
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. REPORT SUMMARY
|
||||
2. REPORT DETAILS
|
||||
|
||||
1. REPORT SUMMARY
|
||||
-----------------
|
||||
Netlist: netlist
|
||||
Floorplan: design_1
|
||||
Design limits: <entire design considered>
|
||||
Ruledeck: default
|
||||
Max violations: <unlimited>
|
||||
Violations found: 1
|
||||
+----------+----------+-----------------------------------------------------+------------+
|
||||
| Rule | Severity | Description | Violations |
|
||||
+----------+----------+-----------------------------------------------------+------------+
|
||||
| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
|
||||
+----------+----------+-----------------------------------------------------+------------+
|
||||
|
||||
2. REPORT DETAILS
|
||||
-----------------
|
||||
CFGBVS-1#1 Warning
|
||||
Missing CFGBVS and CONFIG_VOLTAGE Design Properties
|
||||
Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
|
||||
|
||||
set_property CFGBVS value1 [current_design]
|
||||
#where value1 is either VCCO or GND
|
||||
|
||||
set_property CONFIG_VOLTAGE value2 [current_design]
|
||||
#where value2 is the voltage provided to configuration bank 0
|
||||
|
||||
Refer to the device configuration user guide for more information.
|
||||
Related violations: <none>
|
||||
|
||||
|
||||
Binary file not shown.
@ -1,718 +0,0 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
| Date : Sun Dec 3 21:18:40 2023
|
||||
| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux
|
||||
| Command : report_io -file filter_io_placed.rpt
|
||||
| Design : filter
|
||||
| Device : xc7k160t
|
||||
| Speed File : -1
|
||||
| Package : ffv676
|
||||
| Package Version : FINAL 2012-06-26
|
||||
| Package Pin Delay Version : VERS. 2.0 2012-06-26
|
||||
----------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
IO Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
2. IO Assignments by Package Pin
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+---------------+
|
||||
| Total User IO |
|
||||
+---------------+
|
||||
| 436 |
|
||||
+---------------+
|
||||
|
||||
|
||||
2. IO Assignments by Package Pin
|
||||
--------------------------------
|
||||
|
||||
+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
|
||||
+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
| A1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A3 | | | MGTXTXN3_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| A4 | | | MGTXTXP3_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| A5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A8 | | High Range | IO_L9N_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A9 | | High Range | IO_L9P_T1_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A10 | | High Range | IO_L22N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A11 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
|
||||
| A12 | | High Range | IO_L24N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A13 | | High Range | IO_L24P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A14 | | High Range | IO_L21N_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A15 | | High Range | IO_L23N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| A16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| A17 | | High Range | IO_L3N_T0_DQS_AD1N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| A18 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| A19 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| A20 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| A21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
|
||||
| A22 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| A23 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| A24 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| A25 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| A26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA1 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| AA2 | | High Performance | IO_L12N_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AA3 | | High Performance | IO_L12P_T1_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AA4 | | High Performance | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AA5 | | High Performance | IO_L15P_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AA6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA7 | | High Performance | IO_L8N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA8 | | High Performance | IO_L8P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA9 | | High Performance | IO_L11P_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA10 | | High Performance | IO_L14P_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA11 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| AA12 | | High Performance | IO_L16N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA13 | | High Performance | IO_L16P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AA14 | | High Performance | IO_L7P_T1_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AA15 | | High Performance | IO_L7N_T1_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AA16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AA17 | | High Performance | IO_L11P_T1_SRCC_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AA18 | | High Performance | IO_L11N_T1_SRCC_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AA19 | | High Performance | IO_L16P_T2_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AA20 | | High Performance | IO_L16N_T2_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AA21 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | |
|
||||
| AA22 | | High Range | IO_L13N_T2_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AA23 | | High Range | IO_L11P_T1_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AA24 | | High Range | IO_L12N_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AA25 | | High Range | IO_L7P_T1_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AA26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB1 | | High Performance | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AB2 | | High Performance | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AB3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB4 | | High Performance | IO_L13N_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AB5 | | High Performance | IO_L15N_T2_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AB6 | | High Performance | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AB7 | | High Performance | IO_L10P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AB8 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| AB9 | | High Performance | IO_L11N_T1_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AB10 | | High Performance | IO_L14N_T2_SRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AB11 | | High Performance | IO_L13P_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AB12 | | High Performance | IO_L15P_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AB13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB14 | | High Performance | IO_L10P_T1_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AB15 | | High Performance | IO_L10N_T1_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AB16 | | High Performance | IO_L12P_T1_MRCC_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AB17 | | High Performance | IO_L14P_T2_SRCC_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AB18 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| AB19 | | High Performance | IO_L18P_T2_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AB20 | | High Performance | IO_L18N_T2_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AB21 | | High Range | IO_L18P_T2_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AB22 | | High Range | IO_L17P_T2_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AB23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AB24 | | High Range | IO_L11N_T1_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AB25 | | High Range | IO_L7N_T1_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AB26 | | High Range | IO_L9P_T1_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AC1 | | High Performance | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AC2 | | High Performance | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AC3 | | High Performance | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AC4 | | High Performance | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AC5 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| AC6 | | High Performance | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AC7 | | High Performance | IO_L10N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AC8 | | High Performance | IO_L9P_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AC9 | | High Performance | IO_L12P_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AC10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AC11 | | High Performance | IO_L13N_T2_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AC12 | | High Performance | IO_L15N_T2_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AC13 | | High Performance | IO_L17P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AC14 | | High Performance | IO_L8P_T1_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AC15 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| AC16 | | High Performance | IO_L12N_T1_MRCC_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AC17 | | High Performance | IO_L14N_T2_SRCC_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AC18 | | High Performance | IO_L13P_T2_MRCC_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AC19 | | High Performance | IO_L17P_T2_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AC20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AC21 | | High Range | IO_L18N_T2_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AC22 | | High Range | IO_L17N_T2_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AC23 | | High Range | IO_L14P_T2_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AC24 | | High Range | IO_L14N_T2_SRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AC25 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | |
|
||||
| AC26 | | High Range | IO_L9N_T1_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AD1 | | High Performance | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AD2 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| AD3 | | High Performance | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AD4 | | High Performance | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AD5 | | High Performance | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AD6 | | High Performance | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AD7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AD8 | | High Performance | IO_L9N_T1_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AD9 | | High Performance | IO_L12N_T1_MRCC_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AD10 | | High Performance | IO_L20P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AD11 | | High Performance | IO_L19P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AD12 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| AD13 | | High Performance | IO_L17N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AD14 | | High Performance | IO_L8N_T1_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AD15 | | High Performance | IO_L4P_T0_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AD16 | | High Performance | IO_L6P_T0_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AD17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AD18 | | High Performance | IO_L13N_T2_MRCC_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AD19 | | High Performance | IO_L17N_T2_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AD20 | | High Performance | IO_L15P_T2_DQS_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AD21 | | High Range | IO_L19P_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AD22 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | |
|
||||
| AD23 | | High Range | IO_L16P_T2_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AD24 | | High Range | IO_L16N_T2_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AD25 | | High Range | IO_L23P_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AD26 | | High Range | IO_L21P_T3_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AE1 | | High Performance | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AE2 | | High Performance | IO_L22N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AE3 | | High Performance | IO_L22P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AE4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AE5 | | High Performance | IO_L23N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AE6 | | High Performance | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AE7 | | High Performance | IO_L7P_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AE8 | | High Performance | IO_L22P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AE9 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| AE10 | | High Performance | IO_L20N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AE11 | | High Performance | IO_L19N_T3_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AE12 | | High Performance | IO_L21P_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AE13 | | High Performance | IO_L23P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AE14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AE15 | | High Performance | IO_L4N_T0_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AE16 | | High Performance | IO_L6N_T0_VREF_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AE17 | | High Performance | IO_L1P_T0_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AE18 | | High Performance | IO_L3P_T0_DQS_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AE19 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| AE20 | | High Performance | IO_L15N_T2_DQS_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AE21 | | High Range | IO_L19N_T3_VREF_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AE22 | | High Range | IO_L24P_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AE23 | | High Range | IO_L22P_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AE24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AE25 | | High Range | IO_L23N_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AE26 | | High Range | IO_L21N_T3_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AF1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF2 | | High Performance | IO_L24N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AF3 | | High Performance | IO_L24P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AF4 | | High Performance | IO_L21N_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AF5 | | High Performance | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| AF6 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| AF7 | | High Performance | IO_L7N_T1_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AF8 | | High Performance | IO_L22N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AF9 | | High Performance | IO_L24N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AF10 | | High Performance | IO_L24P_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AF11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF12 | | High Performance | IO_L21N_T3_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AF13 | | High Performance | IO_L23N_T3_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| AF14 | | High Performance | IO_L2P_T0_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AF15 | | High Performance | IO_L2N_T0_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AF16 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| AF17 | | High Performance | IO_L1N_T0_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AF18 | | High Performance | IO_L3N_T0_DQS_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AF19 | | High Performance | IO_L5P_T0_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AF20 | | High Performance | IO_L5N_T0_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| AF21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| AF22 | | High Range | IO_L24N_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AF23 | | High Range | IO_L22N_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AF24 | | High Range | IO_L20P_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AF25 | | High Range | IO_L20N_T3_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| AF26 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | |
|
||||
| B1 | | | MGTXTXN2_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| B2 | | | MGTXTXP2_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| B3 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| B4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B5 | | | MGTXRXN3_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| B6 | | | MGTXRXP3_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| B7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B8 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
|
||||
| B9 | | High Range | IO_L10N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| B10 | | High Range | IO_L22P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| B11 | | High Range | IO_L20N_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| B12 | | High Range | IO_L20P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| B13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B14 | | High Range | IO_L21P_T3_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| B15 | | High Range | IO_L23P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| B16 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| B17 | | High Range | IO_L3P_T0_DQS_AD1P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| B18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
|
||||
| B19 | | High Range | IO_L4N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| B20 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| B21 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| B22 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| B23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| B24 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| B25 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| B26 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| C1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| C3 | | | MGTXRXN2_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| C4 | | | MGTXRXP2_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| C5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| C7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C8 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| C9 | | High Range | IO_L10P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C11 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C12 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C13 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C14 | | High Range | IO_L19P_T3_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| C15 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
|
||||
| C16 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| C17 | | High Range | IO_L5P_T0_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| C18 | | High Range | IO_L5N_T0_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| C19 | | High Range | IO_L4P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| C20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| C21 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| C22 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| C23 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| C24 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| C25 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
|
||||
| C26 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| D1 | | | MGTXTXN1_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| D2 | | | MGTXTXP1_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| D3 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| D4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D5 | | | MGTREFCLK0N_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| D6 | | | MGTREFCLK0P_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| D7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D8 | | High Range | IO_L8N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D9 | | High Range | IO_L8P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D10 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D11 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D12 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
|
||||
| D13 | | High Range | IO_L17N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D14 | | High Range | IO_L17P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| D15 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| D16 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| D17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| D18 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| D19 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| D20 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| D21 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| D22 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
|
||||
| D23 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| D24 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| D25 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| D26 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| E1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E3 | | | MGTXRXN1_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| E4 | | | MGTXRXP1_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| E5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| E7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| E9 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
|
||||
| E10 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| E11 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| E12 | | High Range | IO_L18N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| E13 | | High Range | IO_L18P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E15 | | High Range | IO_L10P_T1_AD4P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| E16 | | High Range | IO_L10N_T1_AD4N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| E17 | | High Range | IO_L12N_T1_MRCC_AD5N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| E18 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| E19 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
|
||||
| E20 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| E21 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| E22 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| E23 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| E24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| E25 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| E26 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| F1 | | | MGTXTXN0_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| F2 | | | MGTXTXP0_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| F3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F5 | | | MGTREFCLK1N_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| F6 | | | MGTREFCLK1P_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F8 | | High Range | IO_L7N_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F9 | | High Range | IO_L7P_T1_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F10 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F12 | | High Range | IO_L16N_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F13 | | High Range | IO_L15N_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F14 | | High Range | IO_L15P_T2_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| F15 | | High Range | IO_L8N_T1_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| F16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
|
||||
| F17 | | High Range | IO_L12P_T1_MRCC_AD5P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| F18 | | High Range | IO_L11N_T1_SRCC_AD12N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| F19 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| F20 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| F21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| F22 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| F23 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| F24 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| F25 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| F26 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
|
||||
| G1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| G3 | | | MGTXRXN0_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| G4 | | | MGTXRXP0_116 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| G5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| G7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G9 | | High Range | IO_L2N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| G10 | | High Range | IO_L2P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| G11 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| G12 | | High Range | IO_L16P_T2_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| G13 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
|
||||
| G14 | | High Range | IO_L5N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| G15 | | High Range | IO_L8P_T1_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G16 | | High Range | IO_L7N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G17 | | High Range | IO_L11P_T1_SRCC_AD12P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| G19 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G20 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| G21 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| G22 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| G23 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
|
||||
| G24 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| G25 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| G26 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| H1 | | | MGTXTXN3_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| H2 | | | MGTXTXP3_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| H3 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| H4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H5 | | | MGTREFCLK0N_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| H6 | | | MGTREFCLK0P_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H8 | | High Range | IO_L1N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| H9 | | High Range | IO_L1P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| H10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
|
||||
| H11 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| H12 | | High Range | IO_L6P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| H13 | | High Range | IO_L3N_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| H14 | | High Range | IO_L5P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| H15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H16 | | High Range | IO_L7P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H17 | | High Range | IO_L14P_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H18 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H19 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| H20 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
|
||||
| H21 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| H22 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| H23 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| H24 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| H25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| H26 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| J1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J3 | | | MGTXRXN3_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| J4 | | | MGTXRXP3_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| J5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| J7 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| J8 | | High Range | IO_0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| J9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| J10 | | High Range | IO_L4N_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| J11 | | High Range | IO_L4P_T0_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J13 | | High Range | IO_L3P_T0_DQS_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| J14 | | High Range | IO_25_16 | User IO | | 16 | | | | | | | | | | | | | |
|
||||
| J15 | | High Range | IO_L9P_T1_DQS_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J16 | | High Range | IO_L9N_T1_DQS_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
|
||||
| J18 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J19 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J20 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| J21 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| J22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| J23 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| J24 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| J25 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| J26 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| K1 | | | MGTXTXN2_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| K2 | | | MGTXTXP2_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| K3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K5 | | | MGTREFCLK1N_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| K6 | | | MGTREFCLK1P_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| K9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K12 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| K13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| K15 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K16 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K17 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K18 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| K20 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| K21 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| K22 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| K23 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| K24 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
|
||||
| K25 | | High Range | IO_L1P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| K26 | | High Range | IO_L1N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| L1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L2 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| L3 | | | MGTXRXN2_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| L4 | | | MGTXRXP2_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| L5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L6 | | | MGTAVCC | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| L7 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
|
||||
| L8 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| L9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| L10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| L14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| L16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| L17 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L19 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L20 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| L21 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
|
||||
| L22 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| L23 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
|
||||
| L24 | | High Range | IO_L8N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| L25 | | High Range | IO_L3N_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| L26 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M1 | | | MGTXTXN1_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| M2 | | | MGTXTXP1_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| M3 | | | MGTAVTT | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| M4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M5 | | | MGTAVTTRCAL_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| M6 | | | MGTRREF_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| M11 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| M12 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| M13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| M17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
|
||||
| M18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | any** | | | | | | | | |
|
||||
| M19 | | High Range | IO_L22N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| M20 | | High Range | IO_L7N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| M21 | | High Range | IO_L10P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| M22 | | High Range | IO_L10N_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| M23 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| M24 | | High Range | IO_L8P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| M25 | | High Range | IO_L3P_T0_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| M26 | | High Range | IO_L5N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| N1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N3 | | | MGTXRXN1_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| N4 | | | MGTXRXP1_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| N5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N6 | | | MGTVCCAUX | Gigabit Power | | | | | | | | | | | | | | | |
|
||||
| N7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N8 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N11 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| N12 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| N13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| N14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| N16 | | High Range | IO_0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| N17 | | High Range | IO_L20N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| N18 | | High Range | IO_L22P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| N19 | | High Range | IO_L7P_T1_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| N20 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| N21 | | High Range | IO_L12P_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| N22 | | High Range | IO_L12N_T1_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| N23 | | High Range | IO_L11N_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| N24 | | High Range | IO_L4N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| N25 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
|
||||
| N26 | | High Range | IO_L5P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| P1 | | | MGTXTXN0_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| P2 | | | MGTXTXP0_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| P3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P5 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| P6 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| P7 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| P8 | | | VCCAUX_IO_G0 | VCCAUX | | | | | | | | | | | | | | | |
|
||||
| P9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| P11 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| P12 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
|
||||
| P13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| P15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P16 | | High Range | IO_L20P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| P17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| P18 | | High Range | IO_L24N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| P19 | | High Range | IO_L9P_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| P20 | | High Range | IO_L9N_T1_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| P21 | | High Range | IO_L13N_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| P22 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
|
||||
| P23 | | High Range | IO_L11P_T1_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| P24 | | High Range | IO_L4P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| P25 | | High Range | IO_L6N_T0_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| P26 | | High Range | IO_L2N_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| R1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R3 | | | MGTXRXN0_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| R4 | | | MGTXRXP0_115 | Gigabit | | | | | | | | | | | | | | | |
|
||||
| R5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R6 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| R7 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| R8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R9 | | | VCCAUX_IO_G0 | VCCAUX | | | | | | | | | | | | | | | |
|
||||
| R10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R11 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
|
||||
| R12 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
|
||||
| R13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| R16 | | High Range | IO_L21P_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| R17 | | High Range | IO_L21N_T3_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| R18 | | High Range | IO_L24P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| R19 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
|
||||
| R20 | | High Range | IO_L16N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| R21 | | High Range | IO_L13P_T2_MRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| R22 | | High Range | IO_L14P_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| R23 | | High Range | IO_L14N_T2_SRCC_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| R24 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| R25 | | High Range | IO_L6P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| R26 | | High Range | IO_L2P_T0_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| T1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T2 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| T3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T5 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
|
||||
| T6 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
|
||||
| T7 | | High Performance | IO_25_VRP_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| T8 | | | VCCAUX_IO_G0 | VCCAUX | | | | | | | | | | | | | | | |
|
||||
| T9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T10 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| T11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T12 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| T13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T14 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| T15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T16 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
|
||||
| T17 | | High Range | IO_L23N_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| T18 | | High Range | IO_L19P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| T19 | | High Range | IO_L19N_T3_VREF_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| T20 | | High Range | IO_L16P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| T21 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| T22 | | High Range | IO_L17P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| T23 | | High Range | IO_L17N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| T24 | | High Range | IO_L15P_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| T25 | | High Range | IO_L15N_T2_DQS_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| T26 | | High Range | VCCO_13 | VCCO | | 13 | | | | | any** | | | | | | | | |
|
||||
| U1 | | High Performance | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U2 | | High Performance | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U3 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| U4 | | High Performance | IO_0_VRN_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U5 | | High Performance | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U6 | | High Performance | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U7 | | High Performance | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| U8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U9 | | High Performance | IO_0_VRN_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U11 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
|
||||
| U12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U13 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
|
||||
| U14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U15 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
|
||||
| U16 | | High Range | IO_25_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| U17 | | High Range | IO_L23P_T3_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| U18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| U19 | | High Range | IO_L18P_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| U20 | | High Range | IO_L18N_T2_13 | User IO | | 13 | | | | | | | | | | | | | |
|
||||
| U21 | | High Range | IO_0_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| U22 | | High Range | IO_L1P_T0_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| U23 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | |
|
||||
| U24 | | High Range | IO_L2P_T0_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| U25 | | High Range | IO_L2N_T0_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| U26 | | High Range | IO_L4P_T0_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| V1 | | High Performance | IO_L8N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V2 | | High Performance | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V3 | | High Performance | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V4 | | High Performance | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V6 | | High Performance | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| V7 | | High Performance | IO_L2N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V8 | | High Performance | IO_L2P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V9 | | High Performance | IO_L6P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V10 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| V11 | | High Performance | IO_L1P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V12 | | High Performance | IO_25_VRP_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| V13 | | High Performance | IO_0_VRN_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| V14 | | High Performance | IO_L24P_T3_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| V15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V16 | | High Performance | IO_L20P_T3_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| V17 | | High Performance | IO_L20N_T3_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| V18 | | High Performance | IO_L23P_T3_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| V19 | | High Performance | IO_L23N_T3_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| V20 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | |
|
||||
| V21 | | High Range | IO_L6P_T0_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| V22 | | High Range | IO_L1N_T0_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| V23 | | High Range | IO_L3P_T0_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| V24 | | High Range | IO_L3N_T0_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| V25 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| V26 | | High Range | IO_L4N_T0_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| W1 | | High Performance | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| W2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| W3 | | High Performance | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| W4 | | High Performance | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| W5 | | High Performance | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| W6 | | High Performance | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| W7 | | High Performance | VCCO_33 | VCCO | | 33 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| W8 | | High Performance | IO_L6N_T0_VREF_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| W9 | | High Performance | IO_L3N_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| W10 | | High Performance | IO_L3P_T0_DQS_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| W11 | | High Performance | IO_L1N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| W12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| W13 | | High Performance | IO_25_VRP_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| W14 | | High Performance | IO_L24N_T3_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| W15 | | High Performance | IO_L22P_T3_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| W16 | | High Performance | IO_L22N_T3_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| W17 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| W18 | | High Performance | IO_L21P_T3_DQS_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| W19 | | High Performance | IO_L21N_T3_DQS_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| W20 | | High Range | IO_L15P_T2_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| W21 | | High Range | IO_L6N_T0_VREF_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| W22 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| W23 | | High Range | IO_L8P_T1_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| W24 | | High Range | IO_L8N_T1_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| W25 | | High Range | IO_L5P_T0_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| W26 | | High Range | IO_L5N_T0_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| Y1 | | High Performance | IO_L10N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y2 | | High Performance | IO_L7N_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y3 | | High Performance | IO_L7P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y4 | | High Performance | VCCO_34 | VCCO | | 34 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| Y5 | | High Performance | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y6 | | High Performance | IO_L17P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
|
||||
| Y7 | | High Performance | IO_L4N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y8 | | High Performance | IO_L4P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y10 | | High Performance | IO_L5N_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y11 | | High Performance | IO_L5P_T0_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y12 | | High Performance | IO_L18N_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y13 | | High Performance | IO_L18P_T2_33 | User IO | | 33 | | | | | | | | | | | | | |
|
||||
| Y14 | | High Performance | VCCO_32 | VCCO | | 32 | | | | | 0.00-1.80 | | | | | | | | |
|
||||
| Y15 | | High Performance | IO_L9P_T1_DQS_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| Y16 | | High Performance | IO_L9N_T1_DQS_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| Y17 | | High Performance | IO_L19P_T3_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| Y18 | | High Performance | IO_L19N_T3_VREF_32 | User IO | | 32 | | | | | | | | | | | | | |
|
||||
| Y19 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
|
||||
| Y20 | | High Range | IO_25_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| Y21 | | High Range | IO_L15N_T2_DQS_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| Y22 | | High Range | IO_L13P_T2_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| Y23 | | High Range | IO_L12P_T1_MRCC_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| Y24 | | High Range | VCCO_12 | VCCO | | 12 | | | | | any** | | | | | | | | |
|
||||
| Y25 | | High Range | IO_L10P_T1_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
| Y26 | | High Range | IO_L10N_T1_12 | User IO | | 12 | | | | | | | | | | | | | |
|
||||
+------------+-------------+------------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+-----------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
|
||||
* Default value
|
||||
** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
|
||||
|
||||
|
||||
Binary file not shown.
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@ -1,164 +0,0 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
-------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
| Date : Sun Dec 3 21:20:43 2023
|
||||
| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux
|
||||
| Command : report_power -file filter_power_routed.rpt -pb filter_power_summary_routed.pb -rpx filter_power_routed.rpx
|
||||
| Design : filter
|
||||
| Device : xc7k160tffv676-1
|
||||
| Design State : routed
|
||||
| Grade : commercial
|
||||
| Process : typical
|
||||
| Characterization : Production
|
||||
-------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Power Report
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Summary
|
||||
1.1 On-Chip Components
|
||||
1.2 Power Supply Summary
|
||||
1.3 Confidence Level
|
||||
2. Settings
|
||||
2.1 Environment
|
||||
2.2 Clock Constraints
|
||||
3. Detailed Reports
|
||||
3.1 By Hierarchy
|
||||
|
||||
1. Summary
|
||||
----------
|
||||
|
||||
+--------------------------+--------------+
|
||||
| Total On-Chip Power (W) | 0.689 |
|
||||
| Design Power Budget (W) | Unspecified* |
|
||||
| Power Budget Margin (W) | NA |
|
||||
| Dynamic (W) | 0.575 |
|
||||
| Device Static (W) | 0.114 |
|
||||
| Effective TJA (C/W) | 1.9 |
|
||||
| Max Ambient (C) | 83.7 |
|
||||
| Junction Temperature (C) | 26.3 |
|
||||
| Confidence Level | Medium |
|
||||
| Setting File | --- |
|
||||
| Simulation Activity File | --- |
|
||||
| Design Nets Matched | NA |
|
||||
+--------------------------+--------------+
|
||||
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
|
||||
|
||||
|
||||
1.1 On-Chip Components
|
||||
----------------------
|
||||
|
||||
+-------------------------+-----------+----------+-----------+-----------------+
|
||||
| On-Chip | Power (W) | Used | Available | Utilization (%) |
|
||||
+-------------------------+-----------+----------+-----------+-----------------+
|
||||
| Clocks | 0.096 | 3 | --- | --- |
|
||||
| Slice Logic | 0.127 | 10142 | --- | --- |
|
||||
| LUT as Logic | 0.101 | 3625 | 101400 | 3.57 |
|
||||
| CARRY4 | 0.013 | 745 | 25350 | 2.94 |
|
||||
| Register | 0.012 | 4839 | 202800 | 2.39 |
|
||||
| LUT as Shift Register | <0.001 | 82 | 35000 | 0.23 |
|
||||
| Others | 0.000 | 34 | --- | --- |
|
||||
| Signals | 0.147 | 7074 | --- | --- |
|
||||
| Block RAM | 0.206 | 34 | 325 | 10.46 |
|
||||
| Static Power | 0.114 | | | |
|
||||
| Total | 0.689 | | | |
|
||||
+-------------------------+-----------+----------+-----------+-----------------+
|
||||
|
||||
|
||||
1.2 Power Supply Summary
|
||||
------------------------
|
||||
|
||||
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
|
||||
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
|
||||
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
|
||||
| Vccint | 1.000 | 0.602 | 0.559 | 0.043 | NA | Unspecified | NA |
|
||||
| Vccaux | 1.800 | 0.018 | 0.000 | 0.018 | NA | Unspecified | NA |
|
||||
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vccbram | 1.000 | 0.018 | 0.016 | 0.002 | NA | Unspecified | NA |
|
||||
| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| MGTVccaux | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
|
||||
| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
|
||||
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
|
||||
|
||||
|
||||
1.3 Confidence Level
|
||||
--------------------
|
||||
|
||||
+-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| User Input Data | Confidence | Details | Action |
|
||||
+-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
| Design implementation state | High | Design is routed | |
|
||||
| Clock nodes activity | High | User specified more than 95% of clocks | |
|
||||
| I/O nodes activity | High | User specified more than 95% of inputs | |
|
||||
| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
|
||||
| Device models | High | Device models are Production | |
|
||||
| | | | |
|
||||
| Overall confidence level | Medium | | |
|
||||
+-----------------------------+------------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
|
||||
2. Settings
|
||||
-----------
|
||||
|
||||
2.1 Environment
|
||||
---------------
|
||||
|
||||
+-----------------------+--------------------------+
|
||||
| Ambient Temp (C) | 25.0 |
|
||||
| ThetaJA (C/W) | 1.9 |
|
||||
| Airflow (LFM) | 250 |
|
||||
| Heat Sink | medium (Medium Profile) |
|
||||
| ThetaSA (C/W) | 3.4 |
|
||||
| Board Selection | medium (10"x10") |
|
||||
| # of Board Layers | 12to15 (12 to 15 Layers) |
|
||||
| Board Temperature (C) | 25.0 |
|
||||
+-----------------------+--------------------------+
|
||||
|
||||
|
||||
2.2 Clock Constraints
|
||||
---------------------
|
||||
|
||||
+-------+--------+-----------------+
|
||||
| Clock | Domain | Constraint (ns) |
|
||||
+-------+--------+-----------------+
|
||||
| CLK | CLK | 4.0 |
|
||||
+-------+--------+-----------------+
|
||||
|
||||
|
||||
3. Detailed Reports
|
||||
-------------------
|
||||
|
||||
3.1 By Hierarchy
|
||||
----------------
|
||||
|
||||
+-------------------------------+-----------+
|
||||
| Name | Power (W) |
|
||||
+-------------------------------+-----------+
|
||||
| filter | 0.575 |
|
||||
| hash_generate[0].hash | 0.083 |
|
||||
| final | 0.033 |
|
||||
| mix_pipeline[0].mix | 0.050 |
|
||||
| hash_generate[1].hash | 0.083 |
|
||||
| final | 0.034 |
|
||||
| mix_pipeline[0].mix | 0.048 |
|
||||
| hash_generate[2].hash | 0.078 |
|
||||
| final | 0.031 |
|
||||
| mix_pipeline[0].mix | 0.047 |
|
||||
| hash_generate[3].hash | 0.079 |
|
||||
| final | 0.031 |
|
||||
| mix_pipeline[0].mix | 0.046 |
|
||||
| storage_generate[0].storage | 0.057 |
|
||||
| storage_generate[1].storage | 0.058 |
|
||||
| storage_generate[2].storage | 0.057 |
|
||||
| storage_generate[3].storage | 0.056 |
|
||||
+-------------------------------+-----------+
|
||||
|
||||
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1,12 +0,0 @@
|
||||
Design Route Status
|
||||
: # nets :
|
||||
------------------------------------------- : ----------- :
|
||||
# of logical nets.......................... : 13669 :
|
||||
# of nets not needing routing.......... : 6593 :
|
||||
# of internally routed nets........ : 6157 :
|
||||
# of implicitly routed ports....... : 436 :
|
||||
# of routable nets..................... : 7076 :
|
||||
# of fully routed nets............. : 7076 :
|
||||
# of nets with routing errors.......... : 0 :
|
||||
------------------------------------------- : ----------- :
|
||||
|
||||
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
@ -1,217 +0,0 @@
|
||||
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
|
||||
| Date : Sun Dec 3 21:18:40 2023
|
||||
| Host : veronika-swiftsf11433 running 64-bit EndeavourOS Linux
|
||||
| Command : report_utilization -file filter_utilization_placed.rpt -pb filter_utilization_placed.pb
|
||||
| Design : filter
|
||||
| Device : xc7k160tffv676-1
|
||||
| Speed File : -1
|
||||
| Design State : Fully Placed
|
||||
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||
|
||||
Utilization Design Information
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
1. Slice Logic
|
||||
1.1 Summary of Registers by Type
|
||||
2. Slice Logic Distribution
|
||||
3. Memory
|
||||
4. DSP
|
||||
5. IO and GT Specific
|
||||
6. Clocking
|
||||
7. Specific Feature
|
||||
8. Primitives
|
||||
9. Black Boxes
|
||||
10. Instantiated Netlists
|
||||
|
||||
1. Slice Logic
|
||||
--------------
|
||||
|
||||
+----------------------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+----------------------------+------+-------+------------+-----------+-------+
|
||||
| Slice LUTs | 3706 | 0 | 0 | 101400 | 3.65 |
|
||||
| LUT as Logic | 3624 | 0 | 0 | 101400 | 3.57 |
|
||||
| LUT as Memory | 82 | 0 | 0 | 35000 | 0.23 |
|
||||
| LUT as Distributed RAM | 0 | 0 | | | |
|
||||
| LUT as Shift Register | 82 | 0 | | | |
|
||||
| Slice Registers | 4839 | 0 | 0 | 202800 | 2.39 |
|
||||
| Register as Flip Flop | 4839 | 0 | 0 | 202800 | 2.39 |
|
||||
| Register as Latch | 0 | 0 | 0 | 202800 | 0.00 |
|
||||
| F7 Muxes | 0 | 0 | 0 | 50700 | 0.00 |
|
||||
| F8 Muxes | 0 | 0 | 0 | 25350 | 0.00 |
|
||||
+----------------------------+------+-------+------------+-----------+-------+
|
||||
* Warning! LUT value is adjusted to account for LUT combining.
|
||||
|
||||
|
||||
1.1 Summary of Registers by Type
|
||||
--------------------------------
|
||||
|
||||
+-------+--------------+-------------+--------------+
|
||||
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||
+-------+--------------+-------------+--------------+
|
||||
| 0 | _ | - | - |
|
||||
| 0 | _ | - | Set |
|
||||
| 0 | _ | - | Reset |
|
||||
| 0 | _ | Set | - |
|
||||
| 0 | _ | Reset | - |
|
||||
| 0 | Yes | - | - |
|
||||
| 0 | Yes | - | Set |
|
||||
| 0 | Yes | - | Reset |
|
||||
| 0 | Yes | Set | - |
|
||||
| 4839 | Yes | Reset | - |
|
||||
+-------+--------------+-------------+--------------+
|
||||
|
||||
|
||||
2. Slice Logic Distribution
|
||||
---------------------------
|
||||
|
||||
+--------------------------------------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+--------------------------------------------+------+-------+------------+-----------+-------+
|
||||
| Slice | 1259 | 0 | 0 | 25350 | 4.97 |
|
||||
| SLICEL | 823 | 0 | | | |
|
||||
| SLICEM | 436 | 0 | | | |
|
||||
| LUT as Logic | 3624 | 0 | 0 | 101400 | 3.57 |
|
||||
| using O5 output only | 0 | | | | |
|
||||
| using O6 output only | 2886 | | | | |
|
||||
| using O5 and O6 | 738 | | | | |
|
||||
| LUT as Memory | 82 | 0 | 0 | 35000 | 0.23 |
|
||||
| LUT as Distributed RAM | 0 | 0 | | | |
|
||||
| LUT as Shift Register | 82 | 0 | | | |
|
||||
| using O5 output only | 1 | | | | |
|
||||
| using O6 output only | 2 | | | | |
|
||||
| using O5 and O6 | 79 | | | | |
|
||||
| Slice Registers | 4839 | 0 | 0 | 202800 | 2.39 |
|
||||
| Register driven from within the Slice | 2898 | | | | |
|
||||
| Register driven from outside the Slice | 1941 | | | | |
|
||||
| LUT in front of the register is unused | 862 | | | | |
|
||||
| LUT in front of the register is used | 1079 | | | | |
|
||||
| Unique Control Sets | 2 | | 0 | 25350 | <0.01 |
|
||||
+--------------------------------------------+------+-------+------------+-----------+-------+
|
||||
* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
|
||||
|
||||
|
||||
3. Memory
|
||||
---------
|
||||
|
||||
+-------------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-------------------+------+-------+------------+-----------+-------+
|
||||
| Block RAM Tile | 34 | 0 | 0 | 325 | 10.46 |
|
||||
| RAMB36/FIFO* | 32 | 0 | 0 | 325 | 9.85 |
|
||||
| RAMB36E1 only | 32 | | | | |
|
||||
| RAMB18 | 4 | 0 | 0 | 650 | 0.62 |
|
||||
| RAMB18E1 only | 4 | | | | |
|
||||
+-------------------+------+-------+------------+-----------+-------+
|
||||
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||
|
||||
|
||||
4. DSP
|
||||
------
|
||||
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
| DSPs | 0 | 0 | 0 | 600 | 0.00 |
|
||||
+-----------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
5. IO and GT Specific
|
||||
---------------------
|
||||
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
| Bonded IOB | 0 | 0 | 0 | 400 | 0.00 |
|
||||
| Bonded IPADs | 0 | 0 | 0 | 26 | 0.00 |
|
||||
| Bonded OPADs | 0 | 0 | 0 | 16 | 0.00 |
|
||||
| PHY_CONTROL | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_REF | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| OUT_FIFO | 0 | 0 | 0 | 32 | 0.00 |
|
||||
| IN_FIFO | 0 | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYCTRL | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| IBUFDS | 0 | 0 | 0 | 384 | 0.00 |
|
||||
| GTXE2_COMMON | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| GTXE2_CHANNEL | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 32 | 0.00 |
|
||||
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 32 | 0.00 |
|
||||
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 400 | 0.00 |
|
||||
| ODELAYE2/ODELAYE2_FINEDELAY | 0 | 0 | 0 | 150 | 0.00 |
|
||||
| IBUFDS_GTE2 | 0 | 0 | 0 | 4 | 0.00 |
|
||||
| ILOGIC | 0 | 0 | 0 | 400 | 0.00 |
|
||||
| OLOGIC | 0 | 0 | 0 | 400 | 0.00 |
|
||||
+-----------------------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
6. Clocking
|
||||
-----------
|
||||
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
|
||||
| BUFIO | 0 | 0 | 0 | 32 | 0.00 |
|
||||
| MMCME2_ADV | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| PLLE2_ADV | 0 | 0 | 0 | 8 | 0.00 |
|
||||
| BUFMRCE | 0 | 0 | 0 | 16 | 0.00 |
|
||||
| BUFHCE | 0 | 0 | 0 | 120 | 0.00 |
|
||||
| BUFR | 0 | 0 | 0 | 32 | 0.00 |
|
||||
+------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
7. Specific Feature
|
||||
-------------------
|
||||
|
||||
+-------------+------+-------+------------+-----------+-------+
|
||||
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||
+-------------+------+-------+------------+-----------+-------+
|
||||
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
|
||||
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
|
||||
| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||
| XADC | 0 | 0 | 0 | 1 | 0.00 |
|
||||
+-------------+------+-------+------------+-----------+-------+
|
||||
|
||||
|
||||
8. Primitives
|
||||
-------------
|
||||
|
||||
+----------+------+---------------------+
|
||||
| Ref Name | Used | Functional Category |
|
||||
+----------+------+---------------------+
|
||||
| FDRE | 4839 | Flop & Latch |
|
||||
| LUT2 | 3166 | LUT |
|
||||
| LUT3 | 764 | LUT |
|
||||
| CARRY4 | 745 | CarryLogic |
|
||||
| LUT1 | 227 | LUT |
|
||||
| LUT6 | 201 | LUT |
|
||||
| SRL16E | 161 | Distributed Memory |
|
||||
| RAMB36E1 | 32 | Block Memory |
|
||||
| RAMB18E1 | 4 | Block Memory |
|
||||
| LUT4 | 4 | LUT |
|
||||
+----------+------+---------------------+
|
||||
|
||||
|
||||
9. Black Boxes
|
||||
--------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
10. Instantiated Netlists
|
||||
-------------------------
|
||||
|
||||
+----------+------+
|
||||
| Ref Name | Used |
|
||||
+----------+------+
|
||||
|
||||
|
||||
@ -1,166 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<GenRun Id="impl_1" LaunchPart="xc7k160tffv676-1" LaunchTime="1701634451">
|
||||
<File Type="ROUTE-RQS-RPT" Name="route_report_qor_suggestions_0.rpt"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-RQS" Name="filter_postroute_physopted.rqs"/>
|
||||
<File Type="ROUTE-RQS" Name="filter_routed.rqs"/>
|
||||
<File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
|
||||
<File Type="BG-BGN" Name="filter.bgn"/>
|
||||
<File Type="BITSTR-SYSDEF" Name="filter.sysdef"/>
|
||||
<File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
|
||||
<File Type="BITSTR-LTX" Name="filter.ltx"/>
|
||||
<File Type="RBD_FILE" Name="filter.rbd"/>
|
||||
<File Type="NPI_FILE" Name="filter.npi"/>
|
||||
<File Type="RNPI_FILE" Name="filter.rnpi"/>
|
||||
<File Type="CFI_FILE" Name="filter.cfi"/>
|
||||
<File Type="RCFI_FILE" Name="filter.rcfi"/>
|
||||
<File Type="PL-PDI-FILE" Name="filter_pld.pdi"/>
|
||||
<File Type="BOOT-PDI-FILE" Name="filter_boot.pdi"/>
|
||||
<File Type="RDI-RDI" Name="filter.vdi"/>
|
||||
<File Type="PDI-FILE" Name="filter.pdi"/>
|
||||
<File Type="BITSTR-MMI" Name="filter.mmi"/>
|
||||
<File Type="BITSTR-BMM" Name="filter_bd.bmm"/>
|
||||
<File Type="BITSTR-NKY" Name="filter.nky"/>
|
||||
<File Type="BITSTR-RBT" Name="filter.rbt"/>
|
||||
<File Type="BITSTR-MSK" Name="filter.msk"/>
|
||||
<File Type="BG-BIN" Name="filter.bin"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-RQS-RPT" Name="postroute_physopt_report_qor_suggestions_0.rpt"/>
|
||||
<File Type="BG-BIT" Name="filter.bit"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="filter_bus_skew_postroute_physopted_1.rpx"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="filter_bus_skew_postroute_physopted_1.pb"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="filter_bus_skew_postroute_physopted_1.rpt"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="filter_timing_summary_postroute_physopted_1.rpx"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="filter_timing_summary_postroute_physopted_1.pb"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-TIMING" Name="filter_timing_summary_postroute_physopted_1.rpt"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="filter_postroute_physopt_bb.dcp"/>
|
||||
<File Type="POSTROUTE-PHYSOPT-DCP" Name="filter_postroute_physopt.dcp"/>
|
||||
<File Type="BG-DRC" Name="filter.drc"/>
|
||||
<File Type="ROUTE-RQS-PB" Name="filter_rqs_routed.pb"/>
|
||||
<File Type="ROUTE-BUS-SKEW-RPX" Name="filter_bus_skew_routed.rpx"/>
|
||||
<File Type="ROUTE-BUS-SKEW-PB" Name="filter_bus_skew_routed.pb"/>
|
||||
<File Type="ROUTE-BUS-SKEW" Name="filter_bus_skew_routed.rpt"/>
|
||||
<File Type="ROUTE-CLK" Name="filter_clock_utilization_routed.rpt"/>
|
||||
<File Type="ROUTE-SIMILARITY" Name="filter_incremental_reuse_routed.rpt"/>
|
||||
<File Type="ROUTE-TIMING-RPX" Name="filter_timing_summary_routed.rpx"/>
|
||||
<File Type="ROUTE-TIMING-PB" Name="filter_timing_summary_routed.pb"/>
|
||||
<File Type="ROUTE-TIMINGSUMMARY" Name="filter_timing_summary_routed.rpt"/>
|
||||
<File Type="ROUTE-STATUS-PB" Name="filter_route_status.pb"/>
|
||||
<File Type="ROUTE-STATUS" Name="filter_route_status.rpt"/>
|
||||
<File Type="ROUTE-PWR-RPX" Name="filter_power_routed.rpx"/>
|
||||
<File Type="ROUTE-PWR-SUM" Name="filter_power_summary_routed.pb"/>
|
||||
<File Type="ROUTE-PWR" Name="filter_power_routed.rpt"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC-PB" Name="filter_methodology_drc_routed.pb"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="filter_methodology_drc_routed.rpx"/>
|
||||
<File Type="ROUTE-METHODOLOGY-DRC" Name="filter_methodology_drc_routed.rpt"/>
|
||||
<File Type="ROUTE-DRC-RPX" Name="filter_drc_routed.rpx"/>
|
||||
<File Type="ROUTE-DRC-PB" Name="filter_drc_routed.pb"/>
|
||||
<File Type="ROUTE-DRC" Name="filter_drc_routed.rpt"/>
|
||||
<File Type="ROUTE-BLACKBOX-DCP" Name="filter_routed_bb.dcp"/>
|
||||
<File Type="ROUTE-DCP" Name="filter_routed.dcp"/>
|
||||
<File Type="ROUTE-ERROR-DCP" Name="filter_routed_error.dcp"/>
|
||||
<File Type="PHYSOPT-TIMING" Name="filter_timing_summary_physopted.rpt"/>
|
||||
<File Type="PHYSOPT-DRC" Name="filter_drc_physopted.rpt"/>
|
||||
<File Type="PHYSOPT-DCP" Name="filter_physopt.dcp"/>
|
||||
<File Type="POSTPLACE-PWROPT-TIMING" Name="filter_timing_summary_postplace_pwropted.rpt"/>
|
||||
<File Type="POSTPLACE-PWROPT-DCP" Name="filter_postplace_pwropt.dcp"/>
|
||||
<File Type="PLACE-RQA-PB" Name="filter_rqa_placed.pb"/>
|
||||
<File Type="PLACE-TIMING" Name="filter_timing_summary_placed.rpt"/>
|
||||
<File Type="PLACE-PRE-SIMILARITY" Name="filter_incremental_reuse_pre_placed.rpt"/>
|
||||
<File Type="PLACE-SIMILARITY" Name="filter_incremental_reuse_placed.rpt"/>
|
||||
<File Type="PLACE-CTRL" Name="filter_control_sets_placed.rpt"/>
|
||||
<File Type="PLACE-UTIL-PB" Name="filter_utilization_placed.pb"/>
|
||||
<File Type="PLACE-UTIL" Name="filter_utilization_placed.rpt"/>
|
||||
<File Type="PLACE-CLK" Name="filter_clock_utilization_placed.rpt"/>
|
||||
<File Type="PLACE-IO" Name="filter_io_placed.rpt"/>
|
||||
<File Type="PLACE-DCP" Name="filter_placed.dcp"/>
|
||||
<File Type="PWROPT-TIMING" Name="filter_timing_summary_pwropted.rpt"/>
|
||||
<File Type="PWROPT-DRC" Name="filter_drc_pwropted.rpt"/>
|
||||
<File Type="PWROPT-DCP" Name="filter_pwropt.dcp"/>
|
||||
<File Type="OPT-RQA-PB" Name="filter_rqa_opted.pb"/>
|
||||
<File Type="OPT-HWDEF" Name="filter.hwdef"/>
|
||||
<File Type="OPT-METHODOLOGY-DRC" Name="filter_methodology_drc_opted.rpt"/>
|
||||
<File Type="OPT-DRC" Name="filter_drc_opted.rpt"/>
|
||||
<File Type="OPT-DCP" Name="filter_opt.dcp"/>
|
||||
<File Type="OPT-TIMING" Name="filter_timing_summary_opted.rpt"/>
|
||||
<File Type="REPORTS-TCL" Name="filter_reports.tcl"/>
|
||||
<File Type="INIT-TIMING" Name="filter_timing_summary_init.rpt"/>
|
||||
<File Type="PA-TCL" Name="filter.tcl"/>
|
||||
<FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../comp/functions.vhd">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../comp/block_memory.vhd">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../filter_ent.vhd">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../comp/jenkins_mix.vhd">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../comp/jenkins_final.vhd">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../comp/jenkins_hash.vhd">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PPRDIR/../filter.vhd">
|
||||
<FileInfo SFType="VHDL2008">
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="filter"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<File Path="$PPRDIR/filter.xdc">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
</GenRun>
|
||||
@ -1,10 +0,0 @@
|
||||
#
|
||||
# Vivado(TM)
|
||||
# htr.txt: a Vivado-generated description of how-to-repeat the
|
||||
# the basic steps of a run. Note that runme.bat/sh needs
|
||||
# to be invoked for Vivado to track run status.
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
vivado -log filter.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source filter.tcl -notrace
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -1,31 +0,0 @@
|
||||
version:1
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:37:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:5648444c:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f7873696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f6d6f64656c73696d:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f717565737461:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f696573:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f766373:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f72697669657261:30:00:00
|
||||
70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
|
||||
5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:3566643632386632633138353432663961623136653661643866623536373363:506172656e742050412070726f6a656374204944:00
|
||||
eof:3523505476
|
||||
Binary file not shown.
@ -1,45 +0,0 @@
|
||||
//
|
||||
// Vivado(TM)
|
||||
// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
|
||||
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
//
|
||||
|
||||
echo "This script was generated under a different operating system."
|
||||
echo "Please update the PATH variable below, before executing this script"
|
||||
exit
|
||||
|
||||
var WshShell = new ActiveXObject( "WScript.Shell" );
|
||||
var ProcEnv = WshShell.Environment( "Process" );
|
||||
var PathVal = ProcEnv("PATH");
|
||||
if ( PathVal.length == 0 ) {
|
||||
PathVal = "/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2023.2/bin;";
|
||||
} else {
|
||||
PathVal = "/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64;/tools/Xilinx/Vivado/2023.2/bin;" + PathVal;
|
||||
}
|
||||
|
||||
ProcEnv("PATH") = PathVal;
|
||||
|
||||
var RDScrFP = WScript.ScriptFullName;
|
||||
var RDScrN = WScript.ScriptName;
|
||||
var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
|
||||
var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
|
||||
eval( EAInclude(ISEJScriptLib) );
|
||||
|
||||
|
||||
// pre-commands:
|
||||
ISETouchFile( "init_design", "begin" );
|
||||
ISEStep( "vivado",
|
||||
"-log filter.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source filter.tcl -notrace" );
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
function EAInclude( EAInclFilename ) {
|
||||
var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
|
||||
var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
|
||||
var EAIFContents = EAInclFile.ReadAll();
|
||||
EAInclFile.Close();
|
||||
return EAIFContents;
|
||||
}
|
||||
@ -1,12 +0,0 @@
|
||||
@echo off
|
||||
|
||||
rem Vivado (TM)
|
||||
rem runme.bat: a Vivado-generated Script
|
||||
rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
rem Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
|
||||
|
||||
set HD_SDIR=%~dp0
|
||||
cd /d "%HD_SDIR%"
|
||||
set PATH=%SYSTEMROOT%\system32;%PATH%
|
||||
cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,44 +0,0 @@
|
||||
#!/bin/sh
|
||||
|
||||
#
|
||||
# Vivado(TM)
|
||||
# runme.sh: a Vivado-generated Runs Script for UNIX
|
||||
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||
#
|
||||
|
||||
if [ -z "$PATH" ]; then
|
||||
PATH=/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2023.2/bin
|
||||
else
|
||||
PATH=/tools/Xilinx/Vivado/2023.2/ids_lite/ISE/bin/lin64:/tools/Xilinx/Vivado/2023.2/bin:$PATH
|
||||
fi
|
||||
export PATH
|
||||
|
||||
if [ -z "$LD_LIBRARY_PATH" ]; then
|
||||
LD_LIBRARY_PATH=
|
||||
else
|
||||
LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
|
||||
fi
|
||||
export LD_LIBRARY_PATH
|
||||
|
||||
HD_PWD='/home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1'
|
||||
cd "$HD_PWD"
|
||||
|
||||
HD_LOG=runme.log
|
||||
/bin/touch $HD_LOG
|
||||
|
||||
ISEStep="./ISEWrap.sh"
|
||||
EAStep()
|
||||
{
|
||||
$ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
|
||||
if [ $? -ne 0 ]
|
||||
then
|
||||
exit
|
||||
fi
|
||||
}
|
||||
|
||||
# pre-commands:
|
||||
/bin/touch .init_design.begin.rst
|
||||
EAStep vivado -log filter.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source filter.tcl -notrace
|
||||
|
||||
|
||||
Binary file not shown.
14
synth/filter_vivado.runs/impl_1/vivado_147960.backup.jou
Normal file
14
synth/filter_vivado.runs/impl_1/vivado_147960.backup.jou
Normal file
@ -0,0 +1,14 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Mon Dec 4 22:37:41 2023
|
||||
# Process ID: 147960
|
||||
# Current directory: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1
|
||||
# Command line: vivado -log filter.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source filter.tcl -notrace
|
||||
# Log file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter.vdi
|
||||
# Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/vivado.jou
|
||||
# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2785.745 MHz, CPU Physical cores: 4, Host memory: 3903 MB
|
||||
#-----------------------------------------------------------
|
||||
source filter.tcl -notrace
|
||||
@ -3,12 +3,12 @@
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Sun Dec 3 21:16:13 2023
|
||||
# Process ID: 50397
|
||||
# Start of session at: Mon Dec 4 09:11:05 2023
|
||||
# Process ID: 62384
|
||||
# Current directory: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1
|
||||
# Command line: vivado -log filter.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source filter.tcl -notrace
|
||||
# Log file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter.vdi
|
||||
# Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/vivado.jou
|
||||
# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2785.806 MHz, CPU Physical cores: 4, Host memory: 3903 MB
|
||||
# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2785.745 MHz, CPU Physical cores: 4, Host memory: 3903 MB
|
||||
#-----------------------------------------------------------
|
||||
source filter.tcl -notrace
|
||||
14
synth/filter_vivado.runs/impl_1/vivado_68233.backup.jou
Normal file
14
synth/filter_vivado.runs/impl_1/vivado_68233.backup.jou
Normal file
@ -0,0 +1,14 @@
|
||||
#-----------------------------------------------------------
|
||||
# Vivado v2023.2 (64-bit)
|
||||
# SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
|
||||
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||
# Start of session at: Mon Dec 4 09:42:30 2023
|
||||
# Process ID: 68233
|
||||
# Current directory: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1
|
||||
# Command line: vivado -log filter.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source filter.tcl -notrace
|
||||
# Log file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/filter.vdi
|
||||
# Journal file: /home/veronikaplevacova/Plocha/PCS2/synth/filter_vivado.runs/impl_1/vivado.jou
|
||||
# Running On: veronika-swiftsf11433, OS: Linux, CPU Frequency: 2785.745 MHz, CPU Physical cores: 4, Host memory: 3903 MB
|
||||
#-----------------------------------------------------------
|
||||
source filter.tcl -notrace
|
||||
@ -1,5 +1,5 @@
|
||||
<?xml version="1.0"?>
|
||||
<ProcessHandle Version="1" Minor="0">
|
||||
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="50035" HostCore="4" HostMemory="3812172">
|
||||
<Process Command="vivado" Owner="veronikaplevacova" Host="veronika-swiftsf11433" Pid="23886" HostCore="4" HostMemory="3812160">
|
||||
</Process>
|
||||
</ProcessHandle>
|
||||
|
||||
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Reference in New Issue
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