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22 lines
872 B
Python
22 lines
872 B
Python
"""
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Support of custom PDK
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This file defines functions for generating full and half adders
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directly on the CMOS modules level.
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You may add your own modules as defined in the example below
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(inside `set_pdk45_library()`)
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NOTE: Please call this function before calling `get_v_code_XXX()` to allow the
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Verilog generation process to take into account the library's specific definitions.
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"""
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from .one_bit_circuits import (
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one_bit_components
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)
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def set_pdk45_library():
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one_bit_components.FullAdder.use_verilog_instance = "FAX1 {unit} (.A({wirea}), .B({wireb}), .C({wirec}), .YS({wireys}), .YC({wireyc}))"
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one_bit_components.HalfAdder.use_verilog_instance = "HAX1 {unit} (.A({wirea}), .B({wireb}), .YS({wireys}), .YC({wireyc}))"
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one_bit_components.TwoOneMultiplexer.use_verilog_instance = "MUX2X1 {unit} (.A({wirea}), .B({wireb}), .S({wires}), .Y({wirey}))"
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