4 Commits

Author	SHA1	Message	Date
honzastor	b88c502343	Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).	2023-03-22 17:57:51 +01:00
honzastor	d52e67bb25	Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.	2023-02-24 11:13:46 +01:00
Honza	c0dcf42499	Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.	2022-04-17 13:04:17 +02:00
Vojta Mrazek	d641595c3e	Support of PDK in HA and FA	2022-01-13 12:37:09 +01:00