Vojta 813f111df7 Merge branch 'devel' of github.com:ehw-fit/ariths-gen into devel

2024-10-03 08:19:27 +02:00

..

core

CGP with more than 26 inputs naming

2024-10-03 08:18:49 +02:00

multi_bit_circuits

Added ripple borrow subtractor circuit and updated automated testing.

2024-10-01 18:42:11 +02:00

one_bit_circuits

Fixed hierarchical BLIF generation for popcount_compare.

2024-04-17 18:47:41 +02:00

wire_components

reconnected wire was not identified as a bus

2024-07-22 15:10:21 +02:00

__init__.py

Implemented new parallel prefix adders and added the possibility for better configuration of partial product accumulators (adders) used in multipliers.

2023-02-24 11:13:46 +01:00

pdk.py

Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).

2023-03-22 17:57:51 +01:00