dissertation_thesis/ariths-gen
1
0
Fork 0
mirror of https://github.com/ehw-fit/ariths-gen.git synced 2025-04-04 06:11:41 +01:00
Code Issues Actions Packages Projects Releases Wiki Activity

dual logic
Some checks failed
BUILD / build (push) Failing after 12s
Details
BUILD / test (push) Has been skipped
Details
BUILD / Python ${{ matrix.python-version }} test (3.10) (push) Has been skipped
Details
BUILD / Python ${{ matrix.python-version }} test (3.11) (push) Has been skipped
Details
BUILD / Python ${{ matrix.python-version }} test (3.12) (push) Has been skipped
Details
BUILD / Python ${{ matrix.python-version }} test (3.9) (push) Has been skipped
Details
BUILD / documentation (push) Has been skipped
Details

Browse Source
This commit is contained in:
zvasicek 2025-01-20 13:22:17 +01:00
parent 2e0d3de856
commit f143bf73c5
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
ariths_gen/one_bit_circuits/logic_gates/logic_gates.py
View File

@ -108,7 +108,7 @@ class NandGate(TwoInputInvertedLogicGate):
self.gate_type = "nand_gate"
self.cgp_function = 5
self.operator = "&"
self.dual_gate = NOrGate
self.dual_gate = NorGate
# Logic gate output wire generation based on input values
# If constant input is present, logic gate is not generated and corresponding