From f143bf73c580bbdce1ff4289fb888fc6ddc7adfb Mon Sep 17 00:00:00 2001
From: zvasicek <37452722+zvasicek@users.noreply.github.com>
Date: Mon, 20 Jan 2025 13:22:17 +0100
Subject: [PATCH] dual logic
---
ariths_gen/one_bit_circuits/logic_gates/logic_gates.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/ariths_gen/one_bit_circuits/logic_gates/logic_gates.py b/ariths_gen/one_bit_circuits/logic_gates/logic_gates.py
index 5c95bd4..2ad7351 100644
--- a/ariths_gen/one_bit_circuits/logic_gates/logic_gates.py
+++ b/ariths_gen/one_bit_circuits/logic_gates/logic_gates.py
@@ -108,7 +108,7 @@ class NandGate(TwoInputInvertedLogicGate):
self.gate_type = "nand_gate"
self.cgp_function = 5
self.operator = "&"
- self.dual_gate = NOrGate
+ self.dual_gate = NorGate
# Logic gate output wire generation based on input values
# If constant input is present, logic gate is not generated and corresponding