94 lines
3.7 KiB
Markdown
94 lines
3.7 KiB
Markdown
# ArithsGen – tool for arithmetic circuits generation
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## Description
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ArithsGen presents an open source tool that enables generation of various arithmetic circuits along with the possibility to export them to various representations which all serve their specific purpose. C language for easy simulation, Verilog for logic synthesis, BLIF for formal verification possibilities and CGP to enable further global optimization.
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### Usage
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```bash
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python3 generate_test.py
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cd test_circuits
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ls
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```
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### Example of generation
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```py
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#Example generation of Verilog representation of 8-bit unsigned dadda multiplier that uses cla to provide the final product
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a = Bus(N=8, prefix="a_bus")
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b = Bus(N=8, prefix="b_bus")
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u_dadda = UnsignedDaddaMultiplier(a=a, b=b, prefix="h_u_dadda_cla8", unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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u_dadda.get_v_code_hier(open("h_u_dadda_cla8.v", "w"))
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```
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### Simple arithmetic circuits
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See ()[rca.py]
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### Complex circuits
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```py
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from ariths_gen.core.arithmetic_circuits.arithmetic_circuit import ArithmeticCircuit
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from ariths_gen.core.arithmetic_circuits import GeneralCircuit
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from ariths_gen.wire_components import Bus, Wire
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from ariths_gen.multi_bit_circuits.adders import UnsignedRippleCarryAdder
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from ariths_gen.multi_bit_circuits.multipliers import UnsignedArrayMultiplier, UnsignedDaddaMultiplier
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import os
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class MAC(GeneralCircuit):
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def __init__(self, a: Bus, b: Bus, r: Bus, prefix: str = "", name: str = "mac", **kwargs):
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super().__init__(prefix=prefix, name=name, out_N=2*a.N+1, inputs=[a, b, r], **kwargs)
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assert a.N == b.N
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assert r.N == 2 * a.N
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self.mul = self.add_component(UnsignedArrayMultiplier(a=a, b=b, prefix=self.prefix, name=f"u_arrmul{a.N}", inner_component=True))
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self.add = self.add_component(UnsignedRippleCarryAdder(a=r, b=self.mul.out, prefix=self.prefix, name=f"u_rca{r.N}", inner_component=True))
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self.out.connect_bus(connecting_bus=self.add.out)
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# usage
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if __name__ == "__main__":
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os.makedirs("test_circuits/mac", exist_ok=True)
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mymac = MAC(Bus("a", 8), Bus("b", 8), Bus("acc", 16))
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mymac.get_v_code_hier(open("test_circuits/mac/mac_hier.v", "w"))
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mymac.get_c_code_hier(open("test_circuits/mac/mac_hier.c", "w"))
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mymac.get_c_code_flat(open("test_circuits/mac/mac_flat.c", "w"))
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```
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## Documentation
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https://ehw-fit.github.io/ariths-gen/
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## Supporting various PDK kits
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When one uses a specific process design kit (PDK), it is not effective to implement half- and full-adders using two-inputs logic gates. These circuits are directly implemented as CMOS modules and are more effective than heuristic optimization by synthesis tool. If you want to use for example FreePDK45 library, you can call a following function before verilog code generating.
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```py
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from ariths_gen import set_pdk45_library
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set_pdk45_library()
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```
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You can add a support of arbitrary PDK (see an [example](ariths_gen/pdk.py) ).
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## Formal verification
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The `yosys_equiv_check.sh` script enables to formally check the equivalence of generated Verilog and BLIF representations of the same circuit.
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It uses the Yosys Open SYnthesis Suite tool by Clifford Wolf. For further information, please visit: http://www.clifford.at/yosys/documentation.html.
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## Execute permission
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```bash
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chmod +x yosys_equiv_check.sh
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```
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### Usage
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```bash
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./yosys_equiv_check.sh -v "verilog_file" -b "blif_file" [-H]
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```
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For more detailed description of script's usage, use help.
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```bash
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./yosys_equiv_check.sh -h|--help
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```
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## CGP testing
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The `chr2c.py` script converts the input CGP chromosome generated by ArithsGen to the corresponding C code and prints it to standard output.
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### Usage
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```bash
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python3 chr2c.py input.chr > output.c
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```
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