60 lines
2.0 KiB
Markdown
60 lines
2.0 KiB
Markdown
# ArithsGen – tool for arithmetic circuits generation
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### FIT BUT bachelor's degree project
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## Description
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ArithsGen presents an open source tool that enables generation of various arithmetic circuits along with the possibility to export them to various representations which all serve their specific purpose. C language for easy simulation, Verilog for logic synthesis, BLIF for formal verification possibilities and CGP to enable further global optimization.
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### Usage
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```bash
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python3 ariths_gen.py
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```
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### Example of generation
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#Example generation of Verilog representation of 8-bit unsigned dadda multiplier that uses cla to provide the final product
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a = Bus(N=8, prefix="a_bus")
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b = Bus(N=8, prefix="b_bus")
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u_dadda = UnsignedDaddaMultiplier(a=a, b=b, prefix="h_u_dadda_cla8", unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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u_dadda.get_v_code_hier(open("h_u_dadda_cla8.v", "w"))
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## Documentation
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Code documentation is provided using **pdoc** documentation generator tool. Source: https://pdoc3.github.io/pdoc/.
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### Installation
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```bash
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pip3 install pdoc3
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```
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### Usage
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```bash
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pdoc --html ariths_gen
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```
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## Formal verification
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The `yosys_equiv_check.sh` script enables to formally check the equivalence of generated Verilog and BLIF representations of the same circuit.
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It uses the Yosys Open SYnthesis Suite tool by Clifford Wolf. For further information, please visit: http://www.clifford.at/yosys/documentation.html.
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## Execute permission
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```bash
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chmod +x yosys_equiv_check.sh
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```
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### Usage
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```bash
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./yosys_equiv_check.sh -v "verilog_file" -b "blif_file" [-H]
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```
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For more detailed description of script's usage, use help.
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```bash
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./yosys_equiv_check.sh -h|--help
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```
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## CGP testing
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The `chr2c.py` script converts the input CGP chromosome generated by ArithsGen to the corresponding C code and prints it to standard output.
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It is a modified version of a script originally authored by Vojtech Mrazek. Note that it required Python2 to run!
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### Usage
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```bash
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python2 chr2c.py input.chr > output.c
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```
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