honzastor b88c502343 Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).

2023-03-22 17:57:51 +01:00

..

logic_gates

Updated circuits documentation.

2021-04-21 13:42:07 +02:00

one_bit_components

Addition of MUX2x1 PDK support and optimization of hierarchical Verilog code generation when using PDK modules (the gates and wires associated with native ArithsGen implementation are not generated).

2023-03-22 17:57:51 +01:00

__init__.py

Updated project's structure. Renamed class names to properly fit Python naming convention. TBD: proper documentation.

2021-03-30 03:04:48 +02:00