60 lines
2.0 KiB
Verilog
60 lines
2.0 KiB
Verilog
module f_u_rca3(input [2:0] a, input [2:0] b, output [3:0] out);
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wire a_0;
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wire a_1;
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wire a_2;
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wire b_0;
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wire b_1;
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wire b_2;
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wire f_u_rca3_ha_a_0;
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wire f_u_rca3_ha_b_0;
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wire f_u_rca3_ha_y0;
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wire f_u_rca3_ha_y1;
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wire f_u_rca3_fa1_a_1;
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wire f_u_rca3_fa1_b_1;
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wire f_u_rca3_fa1_y0;
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wire f_u_rca3_fa1_y1;
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wire f_u_rca3_fa1_f_u_rca3_ha_y1;
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wire f_u_rca3_fa1_y2;
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wire f_u_rca3_fa1_y3;
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wire f_u_rca3_fa1_y4;
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wire f_u_rca3_fa2_a_2;
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wire f_u_rca3_fa2_b_2;
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wire f_u_rca3_fa2_y0;
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wire f_u_rca3_fa2_y1;
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wire f_u_rca3_fa2_f_u_rca3_fa1_y4;
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wire f_u_rca3_fa2_y2;
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wire f_u_rca3_fa2_y3;
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wire f_u_rca3_fa2_y4;
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assign a_0 = a[0];
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assign a_1 = a[1];
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assign a_2 = a[2];
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assign b_0 = b[0];
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assign b_1 = b[1];
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assign b_2 = b[2];
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assign f_u_rca3_ha_a_0 = a_0;
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assign f_u_rca3_ha_b_0 = b_0;
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assign f_u_rca3_ha_y0 = f_u_rca3_ha_a_0 ^ f_u_rca3_ha_b_0;
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assign f_u_rca3_ha_y1 = f_u_rca3_ha_a_0 & f_u_rca3_ha_b_0;
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assign f_u_rca3_fa1_a_1 = a_1;
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assign f_u_rca3_fa1_b_1 = b_1;
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assign f_u_rca3_fa1_f_u_rca3_ha_y1 = f_u_rca3_ha_y1;
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assign f_u_rca3_fa1_y0 = f_u_rca3_fa1_a_1 ^ f_u_rca3_fa1_b_1;
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assign f_u_rca3_fa1_y1 = f_u_rca3_fa1_a_1 & f_u_rca3_fa1_b_1;
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assign f_u_rca3_fa1_y2 = f_u_rca3_fa1_y0 ^ f_u_rca3_fa1_f_u_rca3_ha_y1;
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assign f_u_rca3_fa1_y3 = f_u_rca3_fa1_y0 & f_u_rca3_fa1_f_u_rca3_ha_y1;
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assign f_u_rca3_fa1_y4 = f_u_rca3_fa1_y1 | f_u_rca3_fa1_y3;
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assign f_u_rca3_fa2_a_2 = a_2;
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assign f_u_rca3_fa2_b_2 = b_2;
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assign f_u_rca3_fa2_f_u_rca3_fa1_y4 = f_u_rca3_fa1_y4;
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assign f_u_rca3_fa2_y0 = f_u_rca3_fa2_a_2 ^ f_u_rca3_fa2_b_2;
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assign f_u_rca3_fa2_y1 = f_u_rca3_fa2_a_2 & f_u_rca3_fa2_b_2;
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assign f_u_rca3_fa2_y2 = f_u_rca3_fa2_y0 ^ f_u_rca3_fa2_f_u_rca3_fa1_y4;
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assign f_u_rca3_fa2_y3 = f_u_rca3_fa2_y0 & f_u_rca3_fa2_f_u_rca3_fa1_y4;
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assign f_u_rca3_fa2_y4 = f_u_rca3_fa2_y1 | f_u_rca3_fa2_y3;
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assign out[0] = f_u_rca3_ha_y0;
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assign out[1] = f_u_rca3_fa1_y2;
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assign out[2] = f_u_rca3_fa2_y2;
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assign out[3] = f_u_rca3_fa2_y4;
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endmodule |