55 lines
1.1 KiB
Verilog
55 lines
1.1 KiB
Verilog
`timescale 1ns / 1ps
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 16:06:05 02/24/2021
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// Design Name: f_ha
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// Module Name: C:/Xilinx_projects/Verilog_generated_circuits/Flat_adders/f_ha_test.v
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// Project Name: Flat_adders
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: f_ha
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module f_ha_test;
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// Inputs
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reg a;
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reg b;
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// Outputs
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wire f_ha_y0;
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wire f_ha_y1;
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// Instantiate the Unit Under Test (UUT)
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f_ha uut (
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.a(a),
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.b(b),
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.f_ha_y0(f_ha_y0),
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.f_ha_y1(f_ha_y1)
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);
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initial begin
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// Initialize Inputs
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a = 1'b0;
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b = 1'b1;
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end
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always #2 a = ~a;
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always #4 b = ~b;
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initial $monitor("Time:",$time," ns ", "a=%b, b=%b, sum=%b, cout=%b", a, b, f_ha_y0, f_ha_y1);
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initial #50 $finish;
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endmodule
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