19 lines
466 B
Verilog
19 lines
466 B
Verilog
module f_fa(input a, input b, input cin, output f_fa_y2, output f_fa_y4);
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wire f_fa_a;
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wire f_fa_b;
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wire f_fa_y0;
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wire f_fa_y1;
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wire f_fa_cin;
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wire f_fa_y2;
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wire f_fa_y3;
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wire f_fa_y4;
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assign f_fa_a = a;
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assign f_fa_b = b;
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assign f_fa_cin = cin;
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assign f_fa_y0 = f_fa_a ^ f_fa_b;
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assign f_fa_y1 = f_fa_a & f_fa_b;
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assign f_fa_y2 = f_fa_y0 ^ f_fa_cin;
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assign f_fa_y3 = f_fa_y0 & f_fa_cin;
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assign f_fa_y4 = f_fa_y1 | f_fa_y3;
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endmodule |