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dissertation_thesis
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ariths-gen-mig
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ariths-gen-mig
/
ariths_gen
/
multi_bit_circuits
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honzastor
6003886eb7
Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later
2024-04-14 16:29:10 +02:00
..
adders
Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue.
2024-04-13 17:04:03 +02:00
approximate_adders
Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue.
2024-04-13 17:04:03 +02:00
approximate_multipliers
Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue.
2024-04-13 17:04:03 +02:00
dividers
Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue.
2024-04-13 17:04:03 +02:00
multipliers
Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue.
2024-04-13 17:04:03 +02:00
others
Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later
2024-04-14 16:29:10 +02:00
__init__.py
Updated project's structure. Renamed class names to properly fit Python naming convention. TBD: proper documentation.
2021-03-30 03:04:48 +02:00
