88 lines
4.0 KiB
Markdown
88 lines
4.0 KiB
Markdown
# ArithsGenMig – tool for arithmetic circuits generation on MIG backend
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[](https://www.python.org/)
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[](https://ehw-fit.github.io/ariths-gen)
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## Description
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ArithsGen presents an open source tool that enables generation of various arithmetic circuits along with the possibility to export them to various formats which all serve their specific purpose. C language for easy simulation, Verilog for logic synthesis, BLIF for formal verification possibilities and CGP to enable further global optimization.
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In contrast to standard HDL languages Python supports
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* Multiple output formats (BLIF, Verilog, C, Integer netlist)
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* Advanced language construction (better configuration, inheritance, etc.)
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* Support of various PDKs (for using library cells as half-adders and full-adders)
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## Reference
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When you use this tool in your work/research, please cite the following article: KLHUFEK Jan and MRAZEK Vojtech. ArithsGen: Arithmetics Circuit Generator for HW Accelerators. In: 2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '22). Prague, 2022, p. 4.
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```bibtex
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@INPROCEEDINGS{klhufek:DDECS22,
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author = "Jan Klhufek and Vojtech Mrazek",
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title = "ArithsGen: Arithmetics Circuit Generator for HW Accelerators",
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pages = 4,
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booktitle = "2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '22)",
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year = 2022,
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location = "Prague, CZ"
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}
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```
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### Usage
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```bash
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python3 generate_test.py
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cd test_circuits
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ls
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```
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### Example of generation
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```py
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#Example generation of Verilog representation of 8-bit unsigned dadda multiplier that uses cla to provide the final product
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a = Bus(N=8, prefix="a_bus")
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b = Bus(N=8, prefix="b_bus")
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u_dadda = UnsignedDaddaMultiplier(a=a, b=b, prefix="h_u_dadda_cla8", unsigned_adder_class_name=UnsignedCarryLookaheadAdder)
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u_dadda.get_v_code_hier(open("h_u_dadda_cla8.v", "w"))
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```
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### Simple arithmetic circuits
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See [Ripple Carry Adder](ariths_gen/multi_bit_circuits/adders/ripple_carry_adder.py) file for a basic example.
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### Complex circuits
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It is possible to combine some basic circuits to generate more complex circuits (such as MAC). The design can be parametrised (i.e., you can pass `UnsignedArraymultiplier` as an input parameter).
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```py
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from ariths_gen.core.arithmetic_circuits.arithmetic_circuit import ArithmeticCircuit
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from ariths_gen.core.arithmetic_circuits import GeneralCircuit
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from ariths_gen.wire_components import Bus, Wire
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from ariths_gen.multi_bit_circuits.adders import UnsignedRippleCarryAdder
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from ariths_gen.multi_bit_circuits.multipliers import UnsignedArrayMultiplier, UnsignedDaddaMultiplier
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import os
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class MAC(GeneralCircuit):
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def __init__(self, a: Bus, b: Bus, r: Bus, prefix: str = "", name: str = "mac", **kwargs):
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super().__init__(prefix=prefix, name=name, out_N=2*a.N+1, inputs=[a, b, r], **kwargs)
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assert a.N == b.N
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assert r.N == 2 * a.N
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self.mul = self.add_component(UnsignedArrayMultiplier(a=a, b=b, prefix=self.prefix, name=f"u_arrmul{a.N}", inner_component=True))
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self.add = self.add_component(UnsignedRippleCarryAdder(a=r, b=self.mul.out, prefix=self.prefix, name=f"u_rca{r.N}", inner_component=True))
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self.out.connect_bus(connecting_bus=self.add.out)
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# usage
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if __name__ == "__main__":
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os.makedirs("test_circuits/mac", exist_ok=True)
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mymac = MAC(Bus("a", 8), Bus("b", 8), Bus("acc", 16))
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mymac.get_v_code_flat(open("test_circuits/mac/mac_hier.v", "w"))
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mymac.get_c_code_flat(open("test_circuits/mac/mac_flat.c", "w"))
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```
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## Documentation
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The automatically generated documentation is available at
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https://ehw-fit.github.io/ariths-gen/ .
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## CGP testing
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The `chr2c.py` script converts the input CGP chromosome generated by ArithsGen to the corresponding C code and prints it to standard output.
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### Usage
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```bash
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python3 chr2c.py input.chr > output.c
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```
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