5bb50a325f
Remove iverilog from pipe
BUILD / test (push) Failing after 1m34s
2024-11-14 15:19:54 +01:00
975ab01a1c
Fixing pipeline
BUILD / test (push) Failing after 17s
2024-11-14 15:18:50 +01:00
c476479827
Fix mux with wrong gate ordering
BUILD / test (push) Blocked by required conditions
CodeQL / Analyze (python) (push) Failing after 39s
2024-11-14 15:15:17 +01:00
Vojta
616efb25db
workflow documentation
2024-10-03 08:20:24 +02:00
honzastor
e804265a7b
Updated git actions.
2024-10-02 14:56:52 +02:00
honzastor
03212a62f5
Actions fix
2024-10-01 18:47:24 +02:00
Vojta Mrazek
0180735dd5
workflow to node.js 20
2024-04-05 11:27:41 +02:00
Vojta Mrazek
77724ad115
workflow update
2024-04-05 11:21:42 +02:00
Vojta Mrazek
363e402e16
workflow: docs
2023-03-23 08:00:37 +01:00
Vojta Mrazek
bb4c6d35a7
page deploy
2023-02-24 13:41:36 +01:00
Vojta Mrazek
283f9c79f5
Merge branch 'main' into devel
2023-02-22 12:12:20 +01:00
Vojta Mrazek
d022195e48
Workflow ( #16 )
...
* workflow
* workflow
* workflow
2023-02-22 12:08:21 +01:00
Vojta Mrazek
da4347148c
workflow python 3.6 version
2023-02-22 10:00:32 +01:00
Vojta Mrazek
60c4d3d24e
workflow python 3.6 version
2023-02-22 09:55:19 +01:00
Vojta Mrazek
43b3d65463
workflow modification, bus indexing
2023-02-22 09:52:06 +01:00
Vojta Mrazek
a4a48dea57
Create codeql-analysis.yml ( #14 )
2022-05-26 10:08:35 +02:00
Jan Klhůfek
56c86c13ca
New multipliers ( #13 )
...
* #10 CGP Circuits as inputs (#11 )
* CGP Circuits as inputs
* #10 support of signed output in general circuit
* input as output works
* output connected to input (c)
* automated verilog testing
* output rename
* Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup.
* Typos fix and code cleanup.
* Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats.
* Updated automated testing scripts.
* Small bugfix in python code generation (I initially thought this line is useless).
* Updated generated circuits folder.
Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
2022-04-17 16:00:00 +02:00
Vojta Mrazek
1c2efef024
automated verilog testing
2022-02-02 13:19:54 +01:00
Vojta Mrazek
5646334b7f
workflow axmult typo
2022-01-13 16:11:48 +01:00
Vojta Mrazek
aeacd72d24
Readme, axmults in workflow
2022-01-13 16:10:51 +01:00
Vojta Mrazek
152a6b1583
Python eval ( #4 )
...
* #3 basic clean up arithmetic circuit and general circuit
* #3 implementation of python generator
* #3 pytest in actions
* #3 pytest in actions fix
2021-10-04 11:58:28 +02:00
Vojta Mrazek
fffb928875
auto test MAC
2021-09-07 08:32:52 +02:00
Vojta Mrazek
87a7f2b8bb
pip in actions
2021-06-23 13:46:25 +02:00
Vojta Mrazek
c6e542231c
CGP tests; reversed output order
2021-06-23 13:43:58 +02:00
Vojta Mrazek
5228923b69
doc on main branch only
2021-06-18 12:40:56 +02:00
Vojta Mrazek
cfe0ca6b4b
Automated testing, preparing the package for publishing ( #1 )
...
* automated pandoc deploy
* automated pandoc deploy (v2)
* automated pandoc deploy (v2)
* automated pdoc deploy (v3)
* automated pdoc deploy (v4)
* automated pdoc deploy (v5)
* automated pdoc deploy (v5)
* prepare for python project
* 8-bit testing
* 8-bit testing
* 8-bit testing (v2)
* 8-bit testing (v3)
* update of sign
2021-06-18 12:38:11 +02:00
honzastor
a328e91996
Removed automatic documentation generation from git action.
2021-03-31 04:43:35 +02:00
honzastor
a336a683e7
Added some code documentation and updated git action to generate it.
2021-03-31 04:40:54 +02:00
honzastor
5fe150a824
Adding possibility for automatic generation using git actions.
2021-03-30 16:13:42 +02:00
Vojta Mrazek
af8cd2c93b
no actions
2021-03-23 14:05:54 +01:00
Vojta Mrazek
a8a8779616
action2
2021-03-23 13:46:23 +01:00
Vojta Mrazek
915f494331
workflow
2021-03-23 13:41:56 +01:00
