40 lines
1.2 KiB
Tcl
40 lines
1.2 KiB
Tcl
# filter.tcl: Verification execution script for ModelSim
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# Copyright (C) 2019 FIT BUT
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# Author(s): Lukas Kekely <ikekely@fit.vutbr.cz>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# Create Vivado Project
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#create_project -part xc7vx330tffg1157-1 -force filter_vivado
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create_project -part xc7k160tffv676-1 -force filter_vivado
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set_param project.enableVHDL2008 1
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set_property target_language VHDL [current_project]
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set_property enable_vhdl_2008 1 [current_project]
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# Add source files
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add_files -norecurse \
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../comp/functions.vhd \
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../comp/block_memory.vhd \
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../comp/jenkins_mix.vhd \
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../comp/jenkins_final.vhd \
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../comp/jenkins_hash.vhd \
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../filter_ent.vhd \
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../filter.vhd
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set_property file_type {VHDL 2008} [get_files]
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set_property top filter [current_fileset]
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# Add contraints file
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add_files -fileset constrs_1 filter.xdc
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# Run synthesis
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set_property -name {STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS} -value "-mode out_of_context" -objects [get_runs synth_1]
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launch_runs synth_1
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wait_on_run synth_1
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open_run synth_1
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# Generate reports
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report_timing_summary -delay_type min_max -report_unconstrained -max_paths 64 -input_pins -name timing_1 -file filter_synthesis_timing.log
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report_utilization -file filter_synthesis_utilization.log
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