120 lines
3.5 KiB
VHDL
120 lines
3.5 KiB
VHDL
-- jenkins_mix.vhd: Part of Jenkins hashing function based on https://burtleburtle.net/bob/c/lookup3.c
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-- Copyright (C) 2019 FIT BUT
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-- Author(s): Lukas Kekely <ikekely@fit.vutbr.cz>
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--
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-- SPDX-License-Identifier: BSD-3-Clause
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_unsigned.all;
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entity jenkins_mix is
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generic(
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-- Width of hashed key in 32-bit words.
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LENGTH : natural := 1
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);
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port (
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-- Main clock signal and its synchronous reset.
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CLK : in std_logic;
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RESET : in std_logic;
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-- Input interface ---------------------------------------------------------
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INPUT_A : in std_logic_vector(32-1 downto 0);
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INPUT_B : in std_logic_vector(32-1 downto 0);
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INPUT_C : in std_logic_vector(32-1 downto 0);
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INPUT_KEY : in std_logic_vector(LENGTH*32-1 downto 0);
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INPUT_VALID : in std_logic;
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-- Output interface --------------------------------------------------------
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OUTPUT_A : out std_logic_vector(32-1 downto 0);
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OUTPUT_B : out std_logic_vector(32-1 downto 0);
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OUTPUT_C : out std_logic_vector(32-1 downto 0);
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OUTPUT_KEY : out std_logic_vector(LENGTH*32-1 downto 0);
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OUTPUT_VALID : out std_logic
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);
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end entity;
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architecture behavioral of jenkins_mix is
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constant STAGES : integer := 6;
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function rot(x : std_logic_vector(32-1 downto 0); k : natural) return std_logic_vector is
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begin
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return x(32-k-1 downto 0) & x(32-1 downto 32-k);
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end function;
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type computation_stage is record
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a : std_logic_vector(32-1 downto 0);
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b : std_logic_vector(32-1 downto 0);
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c : std_logic_vector(32-1 downto 0);
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key : std_logic_vector(LENGTH*32-1 downto 0);
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valid : std_logic;
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end record;
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type computation_stage_array is array(natural range <>) of computation_stage;
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signal s : computation_stage_array(0 to STAGES);
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begin
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-- Input connections
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s(0).a <= INPUT_A;
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s(0).b <= INPUT_B;
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s(0).c <= INPUT_C;
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s(0).key <= INPUT_KEY;
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s(0).valid <= INPUT_VALID;
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-- Stage 1: a -= c; a ^= rot(c, 4); c += b;
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s(1).a <= (s(0).a - s(0).c) xor rot(s(0).c, 4);
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s(1).b <= s(0).b;
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s(1).c <= s(0).c + s(0).b;
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s(1).key <= s(0).key;
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s(1).valid <= s(0).valid;
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-- Stage 2: b -= a; b ^= rot(a, 6); a += c;
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s(2).a <= s(1).a + s(1).c;
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s(2).b <= (s(1).b - s(1).a) xor rot(s(1).a, 6);
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s(2).c <= s(1).c;
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s(2).key <= s(1).key;
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s(2).valid <= s(1).valid;
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-- Stage 3: c -= b; c ^= rot(b, 8); b += a;
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s(3).a <= s(2).a;
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s(3).b <= s(2).b + s(2).a;
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s(3).c <= (s(2).c - s(2).b) xor rot(s(2).b, 8);
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s(3).key <= s(2).key;
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s(3).valid <= s(2).valid;
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-- Stage 4: a -= c; a ^= rot(c,16); c += b;
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s(4).a <= (s(3).a - s(3).c) xor rot(s(3).c, 16);
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s(4).b <= s(3).b;
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s(4).c <= s(3).c + s(3).b;
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s(4).key <= s(3).key;
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s(4).valid <= s(3).valid;
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-- Stage 5: b -= a; b ^= rot(a,19); a += c;
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s(5).a <= s(4).a + s(4).c;
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s(5).b <= (s(4).b - s(4).a) xor rot(s(4).a, 19);
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s(5).c <= s(4).c;
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s(5).key <= s(4).key;
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s(5).valid <= s(4).valid;
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-- Stage 6: c -= b; c ^= rot(b, 4); b += a;
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s(6).a <= s(5).a;
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s(6).b <= s(5).b + s(5).a;
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s(6).c <= (s(5).c - s(5).b) xor rot(s(5).b, 4);
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s(6).key <= s(5).key;
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s(6).valid <= s(5).valid;
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-- Output connections
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OUTPUT_A <= s(STAGES).a;
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OUTPUT_B <= s(STAGES).b;
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OUTPUT_C <= s(STAGES).c;
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OUTPUT_KEY <= s(STAGES).key;
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OUTPUT_VALID <= s(STAGES).valid;
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end architecture; |