57 lines
1.6 KiB
Systemverilog
57 lines
1.6 KiB
Systemverilog
// testbench.sv: Verification top-level connection of specific DUT
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// Copyright (C) 2019 FIT BUT
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// Author(s): Lukas Kekely <ikekely@fit.vutbr.cz>
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//
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// SPDX-License-Identifier: BSD-3-Clause
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import test_package::*;
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module testbench;
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logic clk = 0;
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logic reset;
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InputSignal #(KEY_WIDTH) rx (clk, reset);
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OutputSignal #(RULE_WIDTH) tx (clk, reset);
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InputSignal #(CONFIG_WIDTH) cfg (clk, reset);
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always #(CLK_PERIOD/2) clk = ~clk;
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filter #(
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.KEY_WIDTH (KEY_WIDTH),
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.DATA_WIDTH (DATA_WIDTH),
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.TABLES (TABLES),
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.TABLE_SIZE (TABLE_SIZE),
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.INPUT_REGISTER (1),
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.OUTPUT_REGISTER (1),
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.CONFIG_REGISTER (1)
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) VHDL_DUT (
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.CLK (clk),
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.RESET (reset),
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.INPUT_KEY (rx.VALUE),
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.INPUT_VALID (rx.VALID),
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.OUTPUT_KEY (tx.VALUE[KEY_WIDTH+DATA_WIDTH : DATA_WIDTH+1]),
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.OUTPUT_KEY_FOUND (tx.VALUE[0]),
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.OUTPUT_DATA (tx.VALUE[DATA_WIDTH : 1]),
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.OUTPUT_VALID (tx.VALID),
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.CONFIG_KEY (cfg.VALUE[KEY_WIDTH+DATA_WIDTH : DATA_WIDTH+1]),
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.CONFIG_DATA (cfg.VALUE[DATA_WIDTH : 1]),
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.CONFIG_EMPTY (cfg.VALUE[0]),
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.CONFIG_ADDRESS_TABLE (cfg.VALUE[CONFIG_WIDTH-1 : CONFIG_WIDTH-$clog2(TABLES)]),
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.CONFIG_ADDRESS_ITEM (cfg.VALUE[CONFIG_WIDTH-$clog2(TABLES)-1 : CONFIG_WIDTH-$clog2(TABLES)-$clog2(TABLE_SIZE)]),
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.CONFIG_WRITE (cfg.VALID)
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);
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TEST TEST_PROGRAM (
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.CLK (clk),
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.RESET (reset),
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.RX (rx),
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.TX (tx),
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.CFG (cfg)
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);
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endmodule
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