38 lines
1.0 KiB
Tcl
38 lines
1.0 KiB
Tcl
# filter.tcl: Verification execution script for ModelSim
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# Copyright (C) 2019 FIT BUT
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# Author(s): Lukas Kekely <ikekely@fit.vutbr.cz>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# Compile VHDL sources
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eval vlib work
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vcom -2008 -explicit -work work ../comp/functions.vhd
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vcom -2008 -explicit -work work ../comp/block_memory.vhd
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vcom -2008 -explicit -work work ../comp/jenkins_mix.vhd
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vcom -2008 -explicit -work work ../comp/jenkins_final.vhd
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vcom -2008 -explicit -work work ../comp/jenkins_hash.vhd
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vcom -2008 -explicit -work work ../filter_ent.vhd
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vcom -2008 -explicit -work work ../filter.vhd
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# Compile verification sources
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vlog -sv -work work +incdir+comp comp/signal_package.sv
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vlog -sv -work work comp/exact_match.sv
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vlog -sv -work work test_package.sv
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vlog -sv -work work test.sv
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vlog -sv -work work testbench.sv
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# Run verification
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quit -sim
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vsim -t 1ps -lib work testbench
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set StdArithNoWarnings 1
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view wave
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delete wave *
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add wave -noupdate -hex /testbench/VHDL_DUT/*
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config wave -signalnamewidth 1
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restart -f
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run -all |