15 lines
343 B
Systemverilog
15 lines
343 B
Systemverilog
// signal_package.sv: Package with signal related verification components
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// Copyright (C) 2019 FIT BUT
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// Author(s): Lukas Kekely <ikekely@fit.vutbr.cz>
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//
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// SPDX-License-Identifier: BSD-3-Clause
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`include "signal_interface.sv"
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package signal_package;
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`include "signal_driver.sv"
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`include "signal_monitor.sv"
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endpackage
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