55 lines
1.2 KiB
Systemverilog
55 lines
1.2 KiB
Systemverilog
// signal_monitor.sv: Monitor of signal interface
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// Copyright (C) 2019 FIT BUT
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// Author(s): Lukas Kekely <ikekely@fit.vutbr.cz>
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//
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// SPDX-License-Identifier: BSD-3-Clause
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class SignalMonitor #(WIDTH);
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protected bit enabled;
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protected virtual OutputSignal #(WIDTH).test vif;
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protected mailbox #(bit [WIDTH-1 : 0]) mbox;
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function new(virtual OutputSignal #(WIDTH).test v);
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enabled = 0;
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vif = v;
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mbox = new(0);
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endfunction
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function void start();
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enabled = 1;
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fork
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run();
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join_none;
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endfunction
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function void stop();
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enabled = 0;
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endfunction
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task run();
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@(vif.cb); // initial sync
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while(enabled) begin
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if(vif.cb.VALID === 1'bX && vif.cb.RESET == 0) begin
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$write("ERROR: Signal monitor detected an unitialized value on connected VALID flag! (time %0t ps)\n", $time);
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$write("ERROR: Simulation behaviour may be different compared to actual hardware! Stopping ...\n");
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$stop();
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end
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if(vif.cb.VALID)
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mbox.put(vif.cb.VALUE);
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@(vif.cb);
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end
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endtask
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task get(ref bit [WIDTH-1 : 0] value);
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mbox.get(value);
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endtask
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function num();
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return mbox.num();
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endfunction
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endclass
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