41 lines
860 B
Systemverilog
41 lines
860 B
Systemverilog
// signal_interface.sv: Specification of general data signal interface
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// Copyright (C) 2019 FIT BUT
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// Author(s): Lukas Kekely <ikekely@fit.vutbr.cz>
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//
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// SPDX-License-Identifier: BSD-3-Clause
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interface InputSignal #(WIDTH = 32) (input logic CLK, RESET);
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logic [WIDTH-1:0] VALUE;
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logic VALID;
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clocking cb @(posedge CLK);
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default input #1step output #500ps;
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input RESET;
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output VALUE, VALID;
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endclocking;
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modport dut (input VALUE, VALID);
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modport test (clocking cb);
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endinterface
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interface OutputSignal #(WIDTH = 32) (input logic CLK, RESET);
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logic [WIDTH-1:0] VALUE;
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logic VALID;
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clocking cb @(posedge CLK);
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default input #1step output #500ps;
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input VALUE, VALID, RESET;
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endclocking;
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modport dut (output VALUE, VALID);
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modport test (clocking cb);
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endinterface
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