73 lines
1.6 KiB
Systemverilog
73 lines
1.6 KiB
Systemverilog
// signal_driver.sv: Driver of signal interface
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// Copyright (C) 2019 FIT BUT
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// Author(s): Lukas Kekely <ikekely@fit.vutbr.cz>
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//
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// SPDX-License-Identifier: BSD-3-Clause
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class SignalDriver #(WIDTH);
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protected bit enabled;
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protected virtual InputSignal #(WIDTH).test vif;
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protected mailbox #(bit [WIDTH-1 : 0]) mbox;
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protected rand integer Delay;
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protected rand bit DelayEnable;
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int DelayLow = 1;
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int DelayHigh = 5;
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int DelayEnableRatio = 2;
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int DelayDisableRatio = 8;
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constraint Delays {
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DelayEnable dist { 1'b1 := DelayEnableRatio, 1'b0 := DelayDisableRatio };
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Delay inside { [DelayLow : DelayHigh] };
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}
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function new(virtual InputSignal #(WIDTH).test v);
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enabled = 0;
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vif = v;
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mbox = new(1);
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endfunction
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function void start();
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enabled = 1;
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fork
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run();
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join_none;
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endfunction
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function void stop();
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enabled = 0;
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endfunction
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task run();
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bit [WIDTH-1 : 0] data;
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vif.cb.VALUE <= 0;
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vif.cb.VALID <= 0;
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@(vif.cb); // initial sync
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while(enabled) begin
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if(mbox.try_get(data) == 0) begin
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vif.cb.VALUE <= 'X;
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vif.cb.VALID <= 0;
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end else begin
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DELAY_RANDOMIZE : assert(randomize());
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if(DelayEnable) begin
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vif.cb.VALUE <= 'X;
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vif.cb.VALID <= 0;
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repeat(Delay)
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@(vif.cb);
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end
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vif.cb.VALUE <= data;
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vif.cb.VALID <= 1;
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end
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@(vif.cb);
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end
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endtask
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task put(bit [WIDTH-1 : 0] value);
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mbox.put(value);
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endtask
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endclass
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