14 lines
407 B
Tcl
14 lines
407 B
Tcl
# filter.tcl: Verification execution script for ModelSim
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# Copyright (C) 2019 FIT BUT
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# Author(s): Lukas Kekely <ikekely@fit.vutbr.cz>
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#
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# SPDX-License-Identifier: BSD-3-Clause
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# Configure clock frequencies
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create_clock -period 4 [get_ports CLK]
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# Configure delays for synthesis
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set_input_delay -clock [get_clocks CLK] 1 [all_inputs]
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set_output_delay -clock [get_clocks CLK] 1 [all_outputs] |