204 lines
7.4 KiB
VHDL
204 lines
7.4 KiB
VHDL
-- filter.vhd: Exact match filter for IP addresses using multiple parallel hash tables (architecture)
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-- Copyright (C) 2019 FIT BUT
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-- Author(s): Lukas Kekely <ikekely@fit.vutbr.cz>
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--
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-- SPDX-License-Identifier: BSD-3-Clause
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use IEEE.std_logic_arith.all;
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use work.functions_package.all;
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architecture structural of filter is
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constant RULE_WIDTH : natural := KEY_WIDTH + DATA_WIDTH + 1; -- each rule record consists of key, data, and empty flag
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subtype RULE_KEY is natural range KEY_WIDTH+DATA_WIDTH downto DATA_WIDTH+1;
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subtype RULE_DATA is natural range DATA_WIDTH downto 1;
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constant RULE_EMPTY : natural := 0;
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constant KEY_WORDS : natural := cdiv(KEY_WIDTH, 32); -- hash component operates with 32-bit words
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type uint32_array is array (natural range<>) of std_logic_vector(32-1 downto 0);
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type rule_array is array (natural range <>) of std_logic_vector(RULE_WIDTH-1 downto 0);
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signal in_key : std_logic_vector(KEY_WORDS*32-1 downto 0) := (others => '0');
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signal in_valid : std_logic;
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signal out_key : std_logic_vector(KEY_WIDTH-1 downto 0);
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signal out_key_found : std_logic;
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signal out_data : std_logic_vector(DATA_WIDTH-1 downto 0);
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signal out_valid : std_logic;
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signal cfg_record : std_logic_vector(RULE_WIDTH-1 downto 0);
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signal cfg_table : std_logic_vector(clog2(TABLES)-1 downto 0);
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signal cfg_item : std_logic_vector(clog2(TABLE_SIZE)-1 downto 0);
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signal cfg_write : std_logic;
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signal hash_values : uint32_array(0 to TABLES-1);
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signal hash_key : std_logic_vector(KEY_WIDTH-1 downto 0);
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signal hash_valid : std_logic_vector(TABLES-1 downto 0);
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signal memory_rule : rule_array(0 to TABLES-1);
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signal memory_key, memory_key_reg : std_logic_vector(KEY_WIDTH-1 downto 0);
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signal memory_valid : std_logic_vector(TABLES-1 downto 0);
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signal match_flags : std_logic_vector(TABLES-1 downto 0);
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begin
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-- Unsupported configurations checks -----------------------------------------
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assert KEY_WIDTH > 0 report "FAILURE: Filter key must be at least one bit wide!" severity failure;
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assert DATA_WIDTH > 0 report "FAILURE: Filter data must be at least one bit wide!" severity failure;
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assert TABLES >= 2 report "FAILURE: Filter must have at least two tables to support effective hashing scheme!" severity failure;
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assert TABLE_SIZE > 1 report "FAILURE: Filter table must have multiple items!" severity failure;
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assert 2**clog2(TABLE_SIZE) = TABLE_SIZE report "FAILURE: Filter table must have size that is a power of 2!" severity failure;
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-- Registering of entity interfaces ------------------------------------------
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-- Input interface
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registered_input: if INPUT_REGISTER generate
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input_register: process(CLK)
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begin
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if rising_edge(CLK) then
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in_key(KEY_WIDTH-1 downto 0) <= INPUT_KEY;
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if RESET = '1' then
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in_valid <= '0';
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else
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in_valid <= INPUT_VALID;
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end if;
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end if;
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end process;
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end generate;
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dirrect_input: if not INPUT_REGISTER generate
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in_key(KEY_WIDTH-1 downto 0) <= INPUT_KEY;
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in_valid <= INPUT_VALID;
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end generate;
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-- Output interface
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registered_output: if OUTPUT_REGISTER generate
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output_register: process(CLK)
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begin
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if rising_edge(CLK) then
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OUTPUT_KEY <= out_key;
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OUTPUT_KEY_FOUND <= out_key_found;
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OUTPUT_DATA <= out_data;
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if RESET = '1' then
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OUTPUT_VALID <= '0';
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else
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OUTPUT_VALID <= out_valid;
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end if;
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end if;
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end process;
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end generate;
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dirrect_output: if not OUTPUT_REGISTER generate
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OUTPUT_KEY_FOUND <= out_key_found;
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OUTPUT_DATA <= out_data;
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OUTPUT_VALID <= out_valid;
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end generate;
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-- Configuration interface
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registered_config: if CONFIG_REGISTER generate
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config_register: process(CLK)
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begin
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if rising_edge(CLK) then
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cfg_record(RULE_KEY) <= CONFIG_KEY;
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cfg_record(RULE_DATA) <= CONFIG_DATA;
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cfg_record(RULE_EMPTY) <= CONFIG_EMPTY;
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cfg_table <= CONFIG_ADDRESS_TABLE;
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cfg_item <= CONFIG_ADDRESS_ITEM;
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if RESET = '1' then
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cfg_write <= '0';
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else
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cfg_write <= CONFIG_WRITE;
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end if;
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end if;
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end process;
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end generate;
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dirrect_config: if not CONFIG_REGISTER generate
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cfg_record(RULE_KEY) <= CONFIG_KEY;
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cfg_record(RULE_DATA) <= CONFIG_DATA;
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cfg_record(RULE_EMPTY) <= CONFIG_EMPTY;
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cfg_table <= CONFIG_ADDRESS_TABLE;
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cfg_item <= CONFIG_ADDRESS_ITEM;
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cfg_write <= CONFIG_WRITE;
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end generate;
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-- Hashing stage -------------------------------------------------------------
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hash_generate: for t in 0 to TABLES-1 generate
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signal local_key : std_logic_vector(KEY_WORDS*32-1 downto 0);
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signal local_valid : std_logic;
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begin
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hash: entity work.jenkins_hash
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generic map (
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LENGTH => KEY_WORDS,
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INITVAL => conv_std_logic_vector(t+1,32)
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) port map (
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CLK => CLK,
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RESET => RESET,
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INPUT_KEY => in_key,
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INPUT_VALID => in_valid,
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OUTPUT_HASH => hash_values(t),
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OUTPUT_KEY => local_key,
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OUTPUT_VALID => hash_valid(t)
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);
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key_valid_connection: if t = 0 generate -- key is pipelined inside the hash for table #0
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hash_key <= local_key(KEY_WIDTH-1 downto 0);
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end generate;
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end generate;
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-- Storage stage -------------------------------------------------------------
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storage_generate: for t in 0 to TABLES-1 generate
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signal table_select : std_logic;
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signal write_here : std_logic;
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begin
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storage: entity work.block_memory
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generic map (
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ITEM_WIDTH => RULE_WIDTH,
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ITEMS => TABLE_SIZE,
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OUTPUT_REGISTER => true
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) port map (
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CLK => CLK,
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RESET => RESET,
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READ_ADDRESS => hash_values(t)(clog2(TABLE_SIZE)-1 downto 0), -- lowest hash bits are used as address
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READ_VALID => hash_valid(t),
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READ_DATA => memory_rule(t),
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READ_DATA_VALID => memory_valid(t),
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WRITE_DATA => cfg_record,
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WRITE_ADDRESS => cfg_item,
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WRITE_VALID => write_here
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);
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table_select <= '1' when cfg_table = conv_std_logic_vector(t,clog2(TABLES)) else '0'; -- table write enable selection
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write_here <= cfg_write and table_select;
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end generate;
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key_memory_register: process(CLK) -- key pipeline to match memory latency
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begin
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if rising_edge(CLK) then
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--memory_key <= hash_key; -- memory is configured to have one cycle read latecy
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memory_key_reg <= hash_key;
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memory_key <= memory_key_reg;
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end if;
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end process;
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-- Match decoding stage ------------------------------------------------------
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compare_and_select: process(memory_key, memory_rule)
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begin
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out_key_found <= '0';
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out_data <= (others => 'X');
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for t in 0 to TABLES-1 loop
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if memory_key = memory_rule(t)(RULE_KEY) then -- main key compares
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if memory_rule(t)(RULE_EMPTY) = '0' then -- do not forget to ignore empty rules
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out_key_found <= '1';
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out_data <= memory_rule(t)(RULE_DATA);
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end if;
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end if;
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end loop;
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end process;
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out_valid <= memory_valid(0); -- select pipelined valid flag from table #0
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out_key <= memory_key;
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end architecture; |