honzastor 6003886eb7 Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later

2024-04-14 16:29:10 +02:00

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arithmetic_circuits

Fixed hierarchical Verilog generation of popcount compare. BLIF probably needs a similar treatment, TBD later

2024-04-14 16:29:10 +02:00

logic_gate_circuits

Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue.

2024-04-13 17:04:03 +02:00

one_bit_circuits

Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue.

2024-04-13 17:04:03 +02:00

__init__.py

Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.

2021-04-21 11:33:07 +02:00

cgp_circuit.py

Big code cleanup and some fixes. Hierarchical generation for popcount seems problematic. It seems bus connections are the issue.

2024-04-13 17:04:03 +02:00