honzastor e16de78c2b Updated logic behind generating export representations, mainly focused around circuit and its buses and subcomponents namings.

2021-09-07 17:39:39 +02:00

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arithmetic_circuits

Updated logic behind generating export representations, mainly focused around circuit and its buses and subcomponents namings.

2021-09-07 17:39:39 +02:00

logic_gate_circuits

CGP format minor

2021-06-23 14:09:46 +02:00

one_bit_circuits

Updated logic behind generating export representations, mainly focused around circuit and its buses and subcomponents namings.

2021-09-07 17:39:39 +02:00

__init__.py

Optimized circuits generation, refactored code, fixed cla, added new csa, array divider circuits and create yosys equivalence check script. TBD: Documentation and sample generated circuits.

2021-04-21 11:33:07 +02:00