Vojta Mrazek 1c2efef024 automated verilog testing

2022-02-02 13:19:54 +01:00

..

adder_signed.c

Added signedness support for the output C code representation. Also modified the testing scripts and the chr2c.py converter accordingly and did some documentation changes (even made a small change in readme.md). Signedness support for the output python representation is TBD.

2021-10-09 23:45:54 +02:00

adder_unsigned.c

Automated testing, preparing the package for publishing (#1)

2021-06-18 12:38:11 +02:00

mac.c

auto test MAC

2021-09-07 08:32:52 +02:00

multiplier_signed.c

Added signedness support for the output C code representation. Also modified the testing scripts and the chr2c.py converter accordingly and did some documentation changes (even made a small change in readme.md). Signedness support for the output python representation is TBD.

2021-10-09 23:45:54 +02:00

multiplier_unsigned.c

Automated testing, preparing the package for publishing (#1)

2021-06-18 12:38:11 +02:00

tb_adder_signed.v

automated verilog testing

2022-02-02 13:19:54 +01:00

tb_adder_unsigned.v

automated verilog testing

2022-02-02 13:19:54 +01:00

tb_multiplier_signed.v

automated verilog testing

2022-02-02 13:19:54 +01:00

tb_multiplier_unsigned.v

automated verilog testing

2022-02-02 13:19:54 +01:00

test_all.py

input as output works

2022-02-02 11:19:32 +01:00

test_cgp.py

output connected to input (c)

2022-02-02 12:53:18 +01:00

test_circuits_cgp.sh

CGP tests; reversed output order

2021-06-23 13:43:58 +02:00

test_circuits_verilog.sh

automated verilog testing

2022-02-02 13:19:54 +01:00

test_circuits.sh

Automated testing, preparing the package for publishing (#1)

2021-06-18 12:38:11 +02:00

test_mac.sh

test all

2021-09-07 09:44:23 +02:00