Vojta Mrazek ee8621ef4d output connected to input (c)

2022-02-02 12:53:18 +01:00

..

core

#10 CGP Circuits as inputs (#11)

2022-02-01 13:23:26 +01:00

multi_bit_circuits

input as output works

2022-02-02 11:19:32 +01:00

one_bit_circuits

Fixed a small bug – missing ending semicolon in generation of library desired HA/FA to Verilog. Added script for generation of AX multipliers.

2022-01-13 13:11:24 +01:00

wire_components

output connected to input (c)

2022-02-02 12:53:18 +01:00

__init__.py

Support of PDK in HA and FA

2022-01-13 12:37:09 +01:00

pdk.py

Support of PDK in HA and FA

2022-01-13 12:37:09 +01:00