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56c86c13ca
* #10 CGP Circuits as inputs (#11) * CGP Circuits as inputs * #10 support of signed output in general circuit * input as output works * output connected to input (c) * automated verilog testing * output rename * Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. * Typos fix and code cleanup. * Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. * Updated automated testing scripts. * Small bugfix in python code generation (I initially thought this line is useless). * Updated generated circuits folder. Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
89 lines
4.8 KiB
Verilog
89 lines
4.8 KiB
Verilog
module or_gate(input a, input b, output out);
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assign out = a | b;
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endmodule
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module and_gate(input a, input b, output out);
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assign out = a & b;
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endmodule
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module xor_gate(input a, input b, output out);
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assign out = a ^ b;
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endmodule
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module pg_logic(input [0:0] a, input [0:0] b, output [0:0] pg_logic_or0, output [0:0] pg_logic_and0, output [0:0] pg_logic_xor0);
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or_gate or_gate_pg_logic_or0(.a(a[0]), .b(b[0]), .out(pg_logic_or0));
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and_gate and_gate_pg_logic_and0(.a(a[0]), .b(b[0]), .out(pg_logic_and0));
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xor_gate xor_gate_pg_logic_xor0(.a(a[0]), .b(b[0]), .out(pg_logic_xor0));
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endmodule
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module s_cla4(input [3:0] a, input [3:0] b, output [4:0] s_cla4_out);
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wire [0:0] s_cla4_pg_logic0_or0;
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wire [0:0] s_cla4_pg_logic0_and0;
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wire [0:0] s_cla4_pg_logic0_xor0;
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wire [0:0] s_cla4_pg_logic1_or0;
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wire [0:0] s_cla4_pg_logic1_and0;
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wire [0:0] s_cla4_pg_logic1_xor0;
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wire [0:0] s_cla4_xor1;
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wire [0:0] s_cla4_and0;
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wire [0:0] s_cla4_or0;
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wire [0:0] s_cla4_pg_logic2_or0;
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wire [0:0] s_cla4_pg_logic2_and0;
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wire [0:0] s_cla4_pg_logic2_xor0;
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wire [0:0] s_cla4_xor2;
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wire [0:0] s_cla4_and1;
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wire [0:0] s_cla4_and2;
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wire [0:0] s_cla4_and3;
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wire [0:0] s_cla4_and4;
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wire [0:0] s_cla4_or1;
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wire [0:0] s_cla4_or2;
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wire [0:0] s_cla4_pg_logic3_or0;
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wire [0:0] s_cla4_pg_logic3_and0;
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wire [0:0] s_cla4_pg_logic3_xor0;
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wire [0:0] s_cla4_xor3;
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wire [0:0] s_cla4_and5;
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wire [0:0] s_cla4_and6;
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wire [0:0] s_cla4_and7;
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wire [0:0] s_cla4_and8;
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wire [0:0] s_cla4_and9;
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wire [0:0] s_cla4_and10;
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wire [0:0] s_cla4_and11;
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wire [0:0] s_cla4_or3;
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wire [0:0] s_cla4_or4;
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wire [0:0] s_cla4_or5;
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wire [0:0] s_cla4_xor4;
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wire [0:0] s_cla4_xor5;
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pg_logic pg_logic_s_cla4_pg_logic0_out(.a(a[0]), .b(b[0]), .pg_logic_or0(s_cla4_pg_logic0_or0), .pg_logic_and0(s_cla4_pg_logic0_and0), .pg_logic_xor0(s_cla4_pg_logic0_xor0));
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pg_logic pg_logic_s_cla4_pg_logic1_out(.a(a[1]), .b(b[1]), .pg_logic_or0(s_cla4_pg_logic1_or0), .pg_logic_and0(s_cla4_pg_logic1_and0), .pg_logic_xor0(s_cla4_pg_logic1_xor0));
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xor_gate xor_gate_s_cla4_xor1(.a(s_cla4_pg_logic1_xor0[0]), .b(s_cla4_pg_logic0_and0[0]), .out(s_cla4_xor1));
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and_gate and_gate_s_cla4_and0(.a(s_cla4_pg_logic0_and0[0]), .b(s_cla4_pg_logic1_or0[0]), .out(s_cla4_and0));
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or_gate or_gate_s_cla4_or0(.a(s_cla4_pg_logic1_and0[0]), .b(s_cla4_and0[0]), .out(s_cla4_or0));
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pg_logic pg_logic_s_cla4_pg_logic2_out(.a(a[2]), .b(b[2]), .pg_logic_or0(s_cla4_pg_logic2_or0), .pg_logic_and0(s_cla4_pg_logic2_and0), .pg_logic_xor0(s_cla4_pg_logic2_xor0));
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xor_gate xor_gate_s_cla4_xor2(.a(s_cla4_pg_logic2_xor0[0]), .b(s_cla4_or0[0]), .out(s_cla4_xor2));
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and_gate and_gate_s_cla4_and1(.a(s_cla4_pg_logic2_or0[0]), .b(s_cla4_pg_logic0_or0[0]), .out(s_cla4_and1));
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and_gate and_gate_s_cla4_and2(.a(s_cla4_pg_logic0_and0[0]), .b(s_cla4_pg_logic2_or0[0]), .out(s_cla4_and2));
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and_gate and_gate_s_cla4_and3(.a(s_cla4_and2[0]), .b(s_cla4_pg_logic1_or0[0]), .out(s_cla4_and3));
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and_gate and_gate_s_cla4_and4(.a(s_cla4_pg_logic1_and0[0]), .b(s_cla4_pg_logic2_or0[0]), .out(s_cla4_and4));
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or_gate or_gate_s_cla4_or1(.a(s_cla4_and3[0]), .b(s_cla4_and4[0]), .out(s_cla4_or1));
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or_gate or_gate_s_cla4_or2(.a(s_cla4_pg_logic2_and0[0]), .b(s_cla4_or1[0]), .out(s_cla4_or2));
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pg_logic pg_logic_s_cla4_pg_logic3_out(.a(a[3]), .b(b[3]), .pg_logic_or0(s_cla4_pg_logic3_or0), .pg_logic_and0(s_cla4_pg_logic3_and0), .pg_logic_xor0(s_cla4_pg_logic3_xor0));
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xor_gate xor_gate_s_cla4_xor3(.a(s_cla4_pg_logic3_xor0[0]), .b(s_cla4_or2[0]), .out(s_cla4_xor3));
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and_gate and_gate_s_cla4_and5(.a(s_cla4_pg_logic3_or0[0]), .b(s_cla4_pg_logic1_or0[0]), .out(s_cla4_and5));
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and_gate and_gate_s_cla4_and6(.a(s_cla4_pg_logic0_and0[0]), .b(s_cla4_pg_logic2_or0[0]), .out(s_cla4_and6));
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and_gate and_gate_s_cla4_and7(.a(s_cla4_pg_logic3_or0[0]), .b(s_cla4_pg_logic1_or0[0]), .out(s_cla4_and7));
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and_gate and_gate_s_cla4_and8(.a(s_cla4_and6[0]), .b(s_cla4_and7[0]), .out(s_cla4_and8));
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and_gate and_gate_s_cla4_and9(.a(s_cla4_pg_logic1_and0[0]), .b(s_cla4_pg_logic3_or0[0]), .out(s_cla4_and9));
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and_gate and_gate_s_cla4_and10(.a(s_cla4_and9[0]), .b(s_cla4_pg_logic2_or0[0]), .out(s_cla4_and10));
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and_gate and_gate_s_cla4_and11(.a(s_cla4_pg_logic2_and0[0]), .b(s_cla4_pg_logic3_or0[0]), .out(s_cla4_and11));
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or_gate or_gate_s_cla4_or3(.a(s_cla4_and8[0]), .b(s_cla4_and11[0]), .out(s_cla4_or3));
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or_gate or_gate_s_cla4_or4(.a(s_cla4_and10[0]), .b(s_cla4_or3[0]), .out(s_cla4_or4));
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or_gate or_gate_s_cla4_or5(.a(s_cla4_pg_logic3_and0[0]), .b(s_cla4_or4[0]), .out(s_cla4_or5));
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xor_gate xor_gate_s_cla4_xor4(.a(a[3]), .b(b[3]), .out(s_cla4_xor4));
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xor_gate xor_gate_s_cla4_xor5(.a(s_cla4_xor4[0]), .b(s_cla4_or5[0]), .out(s_cla4_xor5));
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assign s_cla4_out[0] = s_cla4_pg_logic0_xor0[0];
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assign s_cla4_out[1] = s_cla4_xor1[0];
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assign s_cla4_out[2] = s_cla4_xor2[0];
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assign s_cla4_out[3] = s_cla4_xor3[0];
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assign s_cla4_out[4] = s_cla4_xor5[0];
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endmodule |