mirror of
https://github.com/ehw-fit/ariths-gen.git
synced 2025-04-19 13:30:56 +01:00
56c86c13ca
* #10 CGP Circuits as inputs (#11) * CGP Circuits as inputs * #10 support of signed output in general circuit * input as output works * output connected to input (c) * automated verilog testing * output rename * Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. * Typos fix and code cleanup. * Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. * Updated automated testing scripts. * Small bugfix in python code generation (I initially thought this line is useless). * Updated generated circuits folder. Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
555 lines
23 KiB
Verilog
555 lines
23 KiB
Verilog
module u_cla24(input [23:0] a, input [23:0] b, output [24:0] u_cla24_out);
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wire u_cla24_pg_logic0_or0;
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wire u_cla24_pg_logic0_and0;
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wire u_cla24_pg_logic0_xor0;
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wire u_cla24_pg_logic1_or0;
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wire u_cla24_pg_logic1_and0;
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wire u_cla24_pg_logic1_xor0;
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wire u_cla24_xor1;
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wire u_cla24_and0;
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wire u_cla24_or0;
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wire u_cla24_pg_logic2_or0;
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wire u_cla24_pg_logic2_and0;
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wire u_cla24_pg_logic2_xor0;
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wire u_cla24_xor2;
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wire u_cla24_and1;
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wire u_cla24_and2;
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wire u_cla24_and3;
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wire u_cla24_and4;
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wire u_cla24_or1;
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wire u_cla24_or2;
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wire u_cla24_pg_logic3_or0;
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wire u_cla24_pg_logic3_and0;
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wire u_cla24_pg_logic3_xor0;
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wire u_cla24_xor3;
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wire u_cla24_and5;
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wire u_cla24_and6;
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wire u_cla24_and7;
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wire u_cla24_and8;
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wire u_cla24_and9;
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wire u_cla24_and10;
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wire u_cla24_and11;
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wire u_cla24_or3;
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wire u_cla24_or4;
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wire u_cla24_or5;
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wire u_cla24_pg_logic4_or0;
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wire u_cla24_pg_logic4_and0;
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wire u_cla24_pg_logic4_xor0;
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wire u_cla24_xor4;
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wire u_cla24_and12;
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wire u_cla24_or6;
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wire u_cla24_pg_logic5_or0;
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wire u_cla24_pg_logic5_and0;
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wire u_cla24_pg_logic5_xor0;
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wire u_cla24_xor5;
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wire u_cla24_and13;
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wire u_cla24_and14;
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wire u_cla24_and15;
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wire u_cla24_or7;
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wire u_cla24_or8;
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wire u_cla24_pg_logic6_or0;
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wire u_cla24_pg_logic6_and0;
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wire u_cla24_pg_logic6_xor0;
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wire u_cla24_xor6;
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wire u_cla24_and16;
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wire u_cla24_and17;
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wire u_cla24_and18;
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wire u_cla24_and19;
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wire u_cla24_and20;
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wire u_cla24_and21;
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wire u_cla24_or9;
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wire u_cla24_or10;
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wire u_cla24_or11;
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wire u_cla24_pg_logic7_or0;
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wire u_cla24_pg_logic7_and0;
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wire u_cla24_pg_logic7_xor0;
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wire u_cla24_xor7;
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wire u_cla24_and22;
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wire u_cla24_and23;
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wire u_cla24_and24;
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wire u_cla24_and25;
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wire u_cla24_and26;
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wire u_cla24_and27;
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wire u_cla24_and28;
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wire u_cla24_and29;
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wire u_cla24_and30;
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wire u_cla24_and31;
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wire u_cla24_or12;
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wire u_cla24_or13;
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wire u_cla24_or14;
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wire u_cla24_or15;
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wire u_cla24_pg_logic8_or0;
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wire u_cla24_pg_logic8_and0;
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wire u_cla24_pg_logic8_xor0;
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wire u_cla24_xor8;
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wire u_cla24_and32;
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wire u_cla24_or16;
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wire u_cla24_pg_logic9_or0;
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wire u_cla24_pg_logic9_and0;
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wire u_cla24_pg_logic9_xor0;
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wire u_cla24_xor9;
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wire u_cla24_and33;
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wire u_cla24_and34;
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wire u_cla24_and35;
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wire u_cla24_or17;
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wire u_cla24_or18;
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wire u_cla24_pg_logic10_or0;
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wire u_cla24_pg_logic10_and0;
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wire u_cla24_pg_logic10_xor0;
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wire u_cla24_xor10;
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wire u_cla24_and36;
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wire u_cla24_and37;
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wire u_cla24_and38;
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wire u_cla24_and39;
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wire u_cla24_and40;
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wire u_cla24_and41;
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wire u_cla24_or19;
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wire u_cla24_or20;
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wire u_cla24_or21;
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wire u_cla24_pg_logic11_or0;
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wire u_cla24_pg_logic11_and0;
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wire u_cla24_pg_logic11_xor0;
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wire u_cla24_xor11;
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wire u_cla24_and42;
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wire u_cla24_and43;
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wire u_cla24_and44;
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wire u_cla24_and45;
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wire u_cla24_and46;
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wire u_cla24_and47;
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wire u_cla24_and48;
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wire u_cla24_and49;
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wire u_cla24_and50;
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wire u_cla24_and51;
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wire u_cla24_or22;
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wire u_cla24_or23;
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wire u_cla24_or24;
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wire u_cla24_or25;
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wire u_cla24_pg_logic12_or0;
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wire u_cla24_pg_logic12_and0;
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wire u_cla24_pg_logic12_xor0;
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wire u_cla24_xor12;
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wire u_cla24_and52;
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wire u_cla24_or26;
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wire u_cla24_pg_logic13_or0;
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wire u_cla24_pg_logic13_and0;
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wire u_cla24_pg_logic13_xor0;
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wire u_cla24_xor13;
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wire u_cla24_and53;
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wire u_cla24_and54;
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wire u_cla24_and55;
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wire u_cla24_or27;
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wire u_cla24_or28;
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wire u_cla24_pg_logic14_or0;
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wire u_cla24_pg_logic14_and0;
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wire u_cla24_pg_logic14_xor0;
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wire u_cla24_xor14;
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wire u_cla24_and56;
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wire u_cla24_and57;
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wire u_cla24_and58;
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wire u_cla24_and59;
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wire u_cla24_and60;
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wire u_cla24_and61;
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wire u_cla24_or29;
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wire u_cla24_or30;
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wire u_cla24_or31;
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wire u_cla24_pg_logic15_or0;
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wire u_cla24_pg_logic15_and0;
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wire u_cla24_pg_logic15_xor0;
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wire u_cla24_xor15;
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wire u_cla24_and62;
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wire u_cla24_and63;
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wire u_cla24_and64;
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wire u_cla24_and65;
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wire u_cla24_and66;
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wire u_cla24_and67;
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wire u_cla24_and68;
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wire u_cla24_and69;
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wire u_cla24_and70;
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wire u_cla24_and71;
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wire u_cla24_or32;
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wire u_cla24_or33;
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wire u_cla24_or34;
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wire u_cla24_or35;
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wire u_cla24_pg_logic16_or0;
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wire u_cla24_pg_logic16_and0;
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wire u_cla24_pg_logic16_xor0;
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wire u_cla24_xor16;
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wire u_cla24_and72;
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wire u_cla24_or36;
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wire u_cla24_pg_logic17_or0;
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wire u_cla24_pg_logic17_and0;
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wire u_cla24_pg_logic17_xor0;
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wire u_cla24_xor17;
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wire u_cla24_and73;
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wire u_cla24_and74;
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wire u_cla24_and75;
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wire u_cla24_or37;
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wire u_cla24_or38;
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wire u_cla24_pg_logic18_or0;
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wire u_cla24_pg_logic18_and0;
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wire u_cla24_pg_logic18_xor0;
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wire u_cla24_xor18;
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wire u_cla24_and76;
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wire u_cla24_and77;
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wire u_cla24_and78;
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wire u_cla24_and79;
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wire u_cla24_and80;
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wire u_cla24_and81;
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wire u_cla24_or39;
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wire u_cla24_or40;
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wire u_cla24_or41;
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wire u_cla24_pg_logic19_or0;
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wire u_cla24_pg_logic19_and0;
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wire u_cla24_pg_logic19_xor0;
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wire u_cla24_xor19;
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wire u_cla24_and82;
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wire u_cla24_and83;
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wire u_cla24_and84;
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wire u_cla24_and85;
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wire u_cla24_and86;
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wire u_cla24_and87;
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wire u_cla24_and88;
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wire u_cla24_and89;
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wire u_cla24_and90;
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wire u_cla24_and91;
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wire u_cla24_or42;
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wire u_cla24_or43;
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wire u_cla24_or44;
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wire u_cla24_or45;
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wire u_cla24_pg_logic20_or0;
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wire u_cla24_pg_logic20_and0;
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wire u_cla24_pg_logic20_xor0;
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wire u_cla24_xor20;
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wire u_cla24_and92;
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wire u_cla24_or46;
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wire u_cla24_pg_logic21_or0;
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wire u_cla24_pg_logic21_and0;
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wire u_cla24_pg_logic21_xor0;
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wire u_cla24_xor21;
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wire u_cla24_and93;
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wire u_cla24_and94;
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wire u_cla24_and95;
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wire u_cla24_or47;
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wire u_cla24_or48;
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wire u_cla24_pg_logic22_or0;
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wire u_cla24_pg_logic22_and0;
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wire u_cla24_pg_logic22_xor0;
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wire u_cla24_xor22;
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wire u_cla24_and96;
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wire u_cla24_and97;
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wire u_cla24_and98;
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wire u_cla24_and99;
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wire u_cla24_and100;
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wire u_cla24_and101;
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wire u_cla24_or49;
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wire u_cla24_or50;
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wire u_cla24_or51;
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wire u_cla24_pg_logic23_or0;
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wire u_cla24_pg_logic23_and0;
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wire u_cla24_pg_logic23_xor0;
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wire u_cla24_xor23;
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wire u_cla24_and102;
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wire u_cla24_and103;
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wire u_cla24_and104;
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wire u_cla24_and105;
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wire u_cla24_and106;
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wire u_cla24_and107;
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wire u_cla24_and108;
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wire u_cla24_and109;
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wire u_cla24_and110;
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wire u_cla24_and111;
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wire u_cla24_or52;
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wire u_cla24_or53;
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wire u_cla24_or54;
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wire u_cla24_or55;
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assign u_cla24_pg_logic0_or0 = a[0] | b[0];
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assign u_cla24_pg_logic0_and0 = a[0] & b[0];
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assign u_cla24_pg_logic0_xor0 = a[0] ^ b[0];
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assign u_cla24_pg_logic1_or0 = a[1] | b[1];
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assign u_cla24_pg_logic1_and0 = a[1] & b[1];
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assign u_cla24_pg_logic1_xor0 = a[1] ^ b[1];
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assign u_cla24_xor1 = u_cla24_pg_logic1_xor0 ^ u_cla24_pg_logic0_and0;
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assign u_cla24_and0 = u_cla24_pg_logic0_and0 & u_cla24_pg_logic1_or0;
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assign u_cla24_or0 = u_cla24_pg_logic1_and0 | u_cla24_and0;
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assign u_cla24_pg_logic2_or0 = a[2] | b[2];
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assign u_cla24_pg_logic2_and0 = a[2] & b[2];
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assign u_cla24_pg_logic2_xor0 = a[2] ^ b[2];
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assign u_cla24_xor2 = u_cla24_pg_logic2_xor0 ^ u_cla24_or0;
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assign u_cla24_and1 = u_cla24_pg_logic2_or0 & u_cla24_pg_logic0_or0;
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assign u_cla24_and2 = u_cla24_pg_logic0_and0 & u_cla24_pg_logic2_or0;
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assign u_cla24_and3 = u_cla24_and2 & u_cla24_pg_logic1_or0;
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assign u_cla24_and4 = u_cla24_pg_logic1_and0 & u_cla24_pg_logic2_or0;
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assign u_cla24_or1 = u_cla24_and3 | u_cla24_and4;
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assign u_cla24_or2 = u_cla24_pg_logic2_and0 | u_cla24_or1;
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assign u_cla24_pg_logic3_or0 = a[3] | b[3];
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assign u_cla24_pg_logic3_and0 = a[3] & b[3];
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assign u_cla24_pg_logic3_xor0 = a[3] ^ b[3];
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assign u_cla24_xor3 = u_cla24_pg_logic3_xor0 ^ u_cla24_or2;
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assign u_cla24_and5 = u_cla24_pg_logic3_or0 & u_cla24_pg_logic1_or0;
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assign u_cla24_and6 = u_cla24_pg_logic0_and0 & u_cla24_pg_logic2_or0;
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assign u_cla24_and7 = u_cla24_pg_logic3_or0 & u_cla24_pg_logic1_or0;
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assign u_cla24_and8 = u_cla24_and6 & u_cla24_and7;
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assign u_cla24_and9 = u_cla24_pg_logic1_and0 & u_cla24_pg_logic3_or0;
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assign u_cla24_and10 = u_cla24_and9 & u_cla24_pg_logic2_or0;
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assign u_cla24_and11 = u_cla24_pg_logic2_and0 & u_cla24_pg_logic3_or0;
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assign u_cla24_or3 = u_cla24_and8 | u_cla24_and11;
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assign u_cla24_or4 = u_cla24_and10 | u_cla24_or3;
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assign u_cla24_or5 = u_cla24_pg_logic3_and0 | u_cla24_or4;
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assign u_cla24_pg_logic4_or0 = a[4] | b[4];
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assign u_cla24_pg_logic4_and0 = a[4] & b[4];
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assign u_cla24_pg_logic4_xor0 = a[4] ^ b[4];
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assign u_cla24_xor4 = u_cla24_pg_logic4_xor0 ^ u_cla24_or5;
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assign u_cla24_and12 = u_cla24_or5 & u_cla24_pg_logic4_or0;
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assign u_cla24_or6 = u_cla24_pg_logic4_and0 | u_cla24_and12;
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assign u_cla24_pg_logic5_or0 = a[5] | b[5];
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assign u_cla24_pg_logic5_and0 = a[5] & b[5];
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assign u_cla24_pg_logic5_xor0 = a[5] ^ b[5];
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assign u_cla24_xor5 = u_cla24_pg_logic5_xor0 ^ u_cla24_or6;
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assign u_cla24_and13 = u_cla24_or5 & u_cla24_pg_logic5_or0;
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assign u_cla24_and14 = u_cla24_and13 & u_cla24_pg_logic4_or0;
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assign u_cla24_and15 = u_cla24_pg_logic4_and0 & u_cla24_pg_logic5_or0;
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assign u_cla24_or7 = u_cla24_and14 | u_cla24_and15;
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assign u_cla24_or8 = u_cla24_pg_logic5_and0 | u_cla24_or7;
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assign u_cla24_pg_logic6_or0 = a[6] | b[6];
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assign u_cla24_pg_logic6_and0 = a[6] & b[6];
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assign u_cla24_pg_logic6_xor0 = a[6] ^ b[6];
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assign u_cla24_xor6 = u_cla24_pg_logic6_xor0 ^ u_cla24_or8;
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assign u_cla24_and16 = u_cla24_or5 & u_cla24_pg_logic5_or0;
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assign u_cla24_and17 = u_cla24_pg_logic6_or0 & u_cla24_pg_logic4_or0;
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assign u_cla24_and18 = u_cla24_and16 & u_cla24_and17;
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assign u_cla24_and19 = u_cla24_pg_logic4_and0 & u_cla24_pg_logic6_or0;
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assign u_cla24_and20 = u_cla24_and19 & u_cla24_pg_logic5_or0;
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assign u_cla24_and21 = u_cla24_pg_logic5_and0 & u_cla24_pg_logic6_or0;
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assign u_cla24_or9 = u_cla24_and18 | u_cla24_and20;
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assign u_cla24_or10 = u_cla24_or9 | u_cla24_and21;
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assign u_cla24_or11 = u_cla24_pg_logic6_and0 | u_cla24_or10;
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assign u_cla24_pg_logic7_or0 = a[7] | b[7];
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assign u_cla24_pg_logic7_and0 = a[7] & b[7];
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assign u_cla24_pg_logic7_xor0 = a[7] ^ b[7];
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assign u_cla24_xor7 = u_cla24_pg_logic7_xor0 ^ u_cla24_or11;
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assign u_cla24_and22 = u_cla24_or5 & u_cla24_pg_logic6_or0;
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assign u_cla24_and23 = u_cla24_pg_logic7_or0 & u_cla24_pg_logic5_or0;
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assign u_cla24_and24 = u_cla24_and22 & u_cla24_and23;
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assign u_cla24_and25 = u_cla24_and24 & u_cla24_pg_logic4_or0;
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assign u_cla24_and26 = u_cla24_pg_logic4_and0 & u_cla24_pg_logic6_or0;
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assign u_cla24_and27 = u_cla24_pg_logic7_or0 & u_cla24_pg_logic5_or0;
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assign u_cla24_and28 = u_cla24_and26 & u_cla24_and27;
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assign u_cla24_and29 = u_cla24_pg_logic5_and0 & u_cla24_pg_logic7_or0;
|
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assign u_cla24_and30 = u_cla24_and29 & u_cla24_pg_logic6_or0;
|
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assign u_cla24_and31 = u_cla24_pg_logic6_and0 & u_cla24_pg_logic7_or0;
|
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assign u_cla24_or12 = u_cla24_and25 | u_cla24_and30;
|
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assign u_cla24_or13 = u_cla24_and28 | u_cla24_and31;
|
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assign u_cla24_or14 = u_cla24_or12 | u_cla24_or13;
|
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assign u_cla24_or15 = u_cla24_pg_logic7_and0 | u_cla24_or14;
|
|
assign u_cla24_pg_logic8_or0 = a[8] | b[8];
|
|
assign u_cla24_pg_logic8_and0 = a[8] & b[8];
|
|
assign u_cla24_pg_logic8_xor0 = a[8] ^ b[8];
|
|
assign u_cla24_xor8 = u_cla24_pg_logic8_xor0 ^ u_cla24_or15;
|
|
assign u_cla24_and32 = u_cla24_or15 & u_cla24_pg_logic8_or0;
|
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assign u_cla24_or16 = u_cla24_pg_logic8_and0 | u_cla24_and32;
|
|
assign u_cla24_pg_logic9_or0 = a[9] | b[9];
|
|
assign u_cla24_pg_logic9_and0 = a[9] & b[9];
|
|
assign u_cla24_pg_logic9_xor0 = a[9] ^ b[9];
|
|
assign u_cla24_xor9 = u_cla24_pg_logic9_xor0 ^ u_cla24_or16;
|
|
assign u_cla24_and33 = u_cla24_or15 & u_cla24_pg_logic9_or0;
|
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assign u_cla24_and34 = u_cla24_and33 & u_cla24_pg_logic8_or0;
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assign u_cla24_and35 = u_cla24_pg_logic8_and0 & u_cla24_pg_logic9_or0;
|
|
assign u_cla24_or17 = u_cla24_and34 | u_cla24_and35;
|
|
assign u_cla24_or18 = u_cla24_pg_logic9_and0 | u_cla24_or17;
|
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assign u_cla24_pg_logic10_or0 = a[10] | b[10];
|
|
assign u_cla24_pg_logic10_and0 = a[10] & b[10];
|
|
assign u_cla24_pg_logic10_xor0 = a[10] ^ b[10];
|
|
assign u_cla24_xor10 = u_cla24_pg_logic10_xor0 ^ u_cla24_or18;
|
|
assign u_cla24_and36 = u_cla24_or15 & u_cla24_pg_logic9_or0;
|
|
assign u_cla24_and37 = u_cla24_pg_logic10_or0 & u_cla24_pg_logic8_or0;
|
|
assign u_cla24_and38 = u_cla24_and36 & u_cla24_and37;
|
|
assign u_cla24_and39 = u_cla24_pg_logic8_and0 & u_cla24_pg_logic10_or0;
|
|
assign u_cla24_and40 = u_cla24_and39 & u_cla24_pg_logic9_or0;
|
|
assign u_cla24_and41 = u_cla24_pg_logic9_and0 & u_cla24_pg_logic10_or0;
|
|
assign u_cla24_or19 = u_cla24_and38 | u_cla24_and40;
|
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assign u_cla24_or20 = u_cla24_or19 | u_cla24_and41;
|
|
assign u_cla24_or21 = u_cla24_pg_logic10_and0 | u_cla24_or20;
|
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assign u_cla24_pg_logic11_or0 = a[11] | b[11];
|
|
assign u_cla24_pg_logic11_and0 = a[11] & b[11];
|
|
assign u_cla24_pg_logic11_xor0 = a[11] ^ b[11];
|
|
assign u_cla24_xor11 = u_cla24_pg_logic11_xor0 ^ u_cla24_or21;
|
|
assign u_cla24_and42 = u_cla24_or15 & u_cla24_pg_logic10_or0;
|
|
assign u_cla24_and43 = u_cla24_pg_logic11_or0 & u_cla24_pg_logic9_or0;
|
|
assign u_cla24_and44 = u_cla24_and42 & u_cla24_and43;
|
|
assign u_cla24_and45 = u_cla24_and44 & u_cla24_pg_logic8_or0;
|
|
assign u_cla24_and46 = u_cla24_pg_logic8_and0 & u_cla24_pg_logic10_or0;
|
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assign u_cla24_and47 = u_cla24_pg_logic11_or0 & u_cla24_pg_logic9_or0;
|
|
assign u_cla24_and48 = u_cla24_and46 & u_cla24_and47;
|
|
assign u_cla24_and49 = u_cla24_pg_logic9_and0 & u_cla24_pg_logic11_or0;
|
|
assign u_cla24_and50 = u_cla24_and49 & u_cla24_pg_logic10_or0;
|
|
assign u_cla24_and51 = u_cla24_pg_logic10_and0 & u_cla24_pg_logic11_or0;
|
|
assign u_cla24_or22 = u_cla24_and45 | u_cla24_and50;
|
|
assign u_cla24_or23 = u_cla24_and48 | u_cla24_and51;
|
|
assign u_cla24_or24 = u_cla24_or22 | u_cla24_or23;
|
|
assign u_cla24_or25 = u_cla24_pg_logic11_and0 | u_cla24_or24;
|
|
assign u_cla24_pg_logic12_or0 = a[12] | b[12];
|
|
assign u_cla24_pg_logic12_and0 = a[12] & b[12];
|
|
assign u_cla24_pg_logic12_xor0 = a[12] ^ b[12];
|
|
assign u_cla24_xor12 = u_cla24_pg_logic12_xor0 ^ u_cla24_or25;
|
|
assign u_cla24_and52 = u_cla24_or25 & u_cla24_pg_logic12_or0;
|
|
assign u_cla24_or26 = u_cla24_pg_logic12_and0 | u_cla24_and52;
|
|
assign u_cla24_pg_logic13_or0 = a[13] | b[13];
|
|
assign u_cla24_pg_logic13_and0 = a[13] & b[13];
|
|
assign u_cla24_pg_logic13_xor0 = a[13] ^ b[13];
|
|
assign u_cla24_xor13 = u_cla24_pg_logic13_xor0 ^ u_cla24_or26;
|
|
assign u_cla24_and53 = u_cla24_or25 & u_cla24_pg_logic13_or0;
|
|
assign u_cla24_and54 = u_cla24_and53 & u_cla24_pg_logic12_or0;
|
|
assign u_cla24_and55 = u_cla24_pg_logic12_and0 & u_cla24_pg_logic13_or0;
|
|
assign u_cla24_or27 = u_cla24_and54 | u_cla24_and55;
|
|
assign u_cla24_or28 = u_cla24_pg_logic13_and0 | u_cla24_or27;
|
|
assign u_cla24_pg_logic14_or0 = a[14] | b[14];
|
|
assign u_cla24_pg_logic14_and0 = a[14] & b[14];
|
|
assign u_cla24_pg_logic14_xor0 = a[14] ^ b[14];
|
|
assign u_cla24_xor14 = u_cla24_pg_logic14_xor0 ^ u_cla24_or28;
|
|
assign u_cla24_and56 = u_cla24_or25 & u_cla24_pg_logic13_or0;
|
|
assign u_cla24_and57 = u_cla24_pg_logic14_or0 & u_cla24_pg_logic12_or0;
|
|
assign u_cla24_and58 = u_cla24_and56 & u_cla24_and57;
|
|
assign u_cla24_and59 = u_cla24_pg_logic12_and0 & u_cla24_pg_logic14_or0;
|
|
assign u_cla24_and60 = u_cla24_and59 & u_cla24_pg_logic13_or0;
|
|
assign u_cla24_and61 = u_cla24_pg_logic13_and0 & u_cla24_pg_logic14_or0;
|
|
assign u_cla24_or29 = u_cla24_and58 | u_cla24_and60;
|
|
assign u_cla24_or30 = u_cla24_or29 | u_cla24_and61;
|
|
assign u_cla24_or31 = u_cla24_pg_logic14_and0 | u_cla24_or30;
|
|
assign u_cla24_pg_logic15_or0 = a[15] | b[15];
|
|
assign u_cla24_pg_logic15_and0 = a[15] & b[15];
|
|
assign u_cla24_pg_logic15_xor0 = a[15] ^ b[15];
|
|
assign u_cla24_xor15 = u_cla24_pg_logic15_xor0 ^ u_cla24_or31;
|
|
assign u_cla24_and62 = u_cla24_or25 & u_cla24_pg_logic14_or0;
|
|
assign u_cla24_and63 = u_cla24_pg_logic15_or0 & u_cla24_pg_logic13_or0;
|
|
assign u_cla24_and64 = u_cla24_and62 & u_cla24_and63;
|
|
assign u_cla24_and65 = u_cla24_and64 & u_cla24_pg_logic12_or0;
|
|
assign u_cla24_and66 = u_cla24_pg_logic12_and0 & u_cla24_pg_logic14_or0;
|
|
assign u_cla24_and67 = u_cla24_pg_logic15_or0 & u_cla24_pg_logic13_or0;
|
|
assign u_cla24_and68 = u_cla24_and66 & u_cla24_and67;
|
|
assign u_cla24_and69 = u_cla24_pg_logic13_and0 & u_cla24_pg_logic15_or0;
|
|
assign u_cla24_and70 = u_cla24_and69 & u_cla24_pg_logic14_or0;
|
|
assign u_cla24_and71 = u_cla24_pg_logic14_and0 & u_cla24_pg_logic15_or0;
|
|
assign u_cla24_or32 = u_cla24_and65 | u_cla24_and70;
|
|
assign u_cla24_or33 = u_cla24_and68 | u_cla24_and71;
|
|
assign u_cla24_or34 = u_cla24_or32 | u_cla24_or33;
|
|
assign u_cla24_or35 = u_cla24_pg_logic15_and0 | u_cla24_or34;
|
|
assign u_cla24_pg_logic16_or0 = a[16] | b[16];
|
|
assign u_cla24_pg_logic16_and0 = a[16] & b[16];
|
|
assign u_cla24_pg_logic16_xor0 = a[16] ^ b[16];
|
|
assign u_cla24_xor16 = u_cla24_pg_logic16_xor0 ^ u_cla24_or35;
|
|
assign u_cla24_and72 = u_cla24_or35 & u_cla24_pg_logic16_or0;
|
|
assign u_cla24_or36 = u_cla24_pg_logic16_and0 | u_cla24_and72;
|
|
assign u_cla24_pg_logic17_or0 = a[17] | b[17];
|
|
assign u_cla24_pg_logic17_and0 = a[17] & b[17];
|
|
assign u_cla24_pg_logic17_xor0 = a[17] ^ b[17];
|
|
assign u_cla24_xor17 = u_cla24_pg_logic17_xor0 ^ u_cla24_or36;
|
|
assign u_cla24_and73 = u_cla24_or35 & u_cla24_pg_logic17_or0;
|
|
assign u_cla24_and74 = u_cla24_and73 & u_cla24_pg_logic16_or0;
|
|
assign u_cla24_and75 = u_cla24_pg_logic16_and0 & u_cla24_pg_logic17_or0;
|
|
assign u_cla24_or37 = u_cla24_and74 | u_cla24_and75;
|
|
assign u_cla24_or38 = u_cla24_pg_logic17_and0 | u_cla24_or37;
|
|
assign u_cla24_pg_logic18_or0 = a[18] | b[18];
|
|
assign u_cla24_pg_logic18_and0 = a[18] & b[18];
|
|
assign u_cla24_pg_logic18_xor0 = a[18] ^ b[18];
|
|
assign u_cla24_xor18 = u_cla24_pg_logic18_xor0 ^ u_cla24_or38;
|
|
assign u_cla24_and76 = u_cla24_or35 & u_cla24_pg_logic17_or0;
|
|
assign u_cla24_and77 = u_cla24_pg_logic18_or0 & u_cla24_pg_logic16_or0;
|
|
assign u_cla24_and78 = u_cla24_and76 & u_cla24_and77;
|
|
assign u_cla24_and79 = u_cla24_pg_logic16_and0 & u_cla24_pg_logic18_or0;
|
|
assign u_cla24_and80 = u_cla24_and79 & u_cla24_pg_logic17_or0;
|
|
assign u_cla24_and81 = u_cla24_pg_logic17_and0 & u_cla24_pg_logic18_or0;
|
|
assign u_cla24_or39 = u_cla24_and78 | u_cla24_and80;
|
|
assign u_cla24_or40 = u_cla24_or39 | u_cla24_and81;
|
|
assign u_cla24_or41 = u_cla24_pg_logic18_and0 | u_cla24_or40;
|
|
assign u_cla24_pg_logic19_or0 = a[19] | b[19];
|
|
assign u_cla24_pg_logic19_and0 = a[19] & b[19];
|
|
assign u_cla24_pg_logic19_xor0 = a[19] ^ b[19];
|
|
assign u_cla24_xor19 = u_cla24_pg_logic19_xor0 ^ u_cla24_or41;
|
|
assign u_cla24_and82 = u_cla24_or35 & u_cla24_pg_logic18_or0;
|
|
assign u_cla24_and83 = u_cla24_pg_logic19_or0 & u_cla24_pg_logic17_or0;
|
|
assign u_cla24_and84 = u_cla24_and82 & u_cla24_and83;
|
|
assign u_cla24_and85 = u_cla24_and84 & u_cla24_pg_logic16_or0;
|
|
assign u_cla24_and86 = u_cla24_pg_logic16_and0 & u_cla24_pg_logic18_or0;
|
|
assign u_cla24_and87 = u_cla24_pg_logic19_or0 & u_cla24_pg_logic17_or0;
|
|
assign u_cla24_and88 = u_cla24_and86 & u_cla24_and87;
|
|
assign u_cla24_and89 = u_cla24_pg_logic17_and0 & u_cla24_pg_logic19_or0;
|
|
assign u_cla24_and90 = u_cla24_and89 & u_cla24_pg_logic18_or0;
|
|
assign u_cla24_and91 = u_cla24_pg_logic18_and0 & u_cla24_pg_logic19_or0;
|
|
assign u_cla24_or42 = u_cla24_and85 | u_cla24_and90;
|
|
assign u_cla24_or43 = u_cla24_and88 | u_cla24_and91;
|
|
assign u_cla24_or44 = u_cla24_or42 | u_cla24_or43;
|
|
assign u_cla24_or45 = u_cla24_pg_logic19_and0 | u_cla24_or44;
|
|
assign u_cla24_pg_logic20_or0 = a[20] | b[20];
|
|
assign u_cla24_pg_logic20_and0 = a[20] & b[20];
|
|
assign u_cla24_pg_logic20_xor0 = a[20] ^ b[20];
|
|
assign u_cla24_xor20 = u_cla24_pg_logic20_xor0 ^ u_cla24_or45;
|
|
assign u_cla24_and92 = u_cla24_or45 & u_cla24_pg_logic20_or0;
|
|
assign u_cla24_or46 = u_cla24_pg_logic20_and0 | u_cla24_and92;
|
|
assign u_cla24_pg_logic21_or0 = a[21] | b[21];
|
|
assign u_cla24_pg_logic21_and0 = a[21] & b[21];
|
|
assign u_cla24_pg_logic21_xor0 = a[21] ^ b[21];
|
|
assign u_cla24_xor21 = u_cla24_pg_logic21_xor0 ^ u_cla24_or46;
|
|
assign u_cla24_and93 = u_cla24_or45 & u_cla24_pg_logic21_or0;
|
|
assign u_cla24_and94 = u_cla24_and93 & u_cla24_pg_logic20_or0;
|
|
assign u_cla24_and95 = u_cla24_pg_logic20_and0 & u_cla24_pg_logic21_or0;
|
|
assign u_cla24_or47 = u_cla24_and94 | u_cla24_and95;
|
|
assign u_cla24_or48 = u_cla24_pg_logic21_and0 | u_cla24_or47;
|
|
assign u_cla24_pg_logic22_or0 = a[22] | b[22];
|
|
assign u_cla24_pg_logic22_and0 = a[22] & b[22];
|
|
assign u_cla24_pg_logic22_xor0 = a[22] ^ b[22];
|
|
assign u_cla24_xor22 = u_cla24_pg_logic22_xor0 ^ u_cla24_or48;
|
|
assign u_cla24_and96 = u_cla24_or45 & u_cla24_pg_logic21_or0;
|
|
assign u_cla24_and97 = u_cla24_pg_logic22_or0 & u_cla24_pg_logic20_or0;
|
|
assign u_cla24_and98 = u_cla24_and96 & u_cla24_and97;
|
|
assign u_cla24_and99 = u_cla24_pg_logic20_and0 & u_cla24_pg_logic22_or0;
|
|
assign u_cla24_and100 = u_cla24_and99 & u_cla24_pg_logic21_or0;
|
|
assign u_cla24_and101 = u_cla24_pg_logic21_and0 & u_cla24_pg_logic22_or0;
|
|
assign u_cla24_or49 = u_cla24_and98 | u_cla24_and100;
|
|
assign u_cla24_or50 = u_cla24_or49 | u_cla24_and101;
|
|
assign u_cla24_or51 = u_cla24_pg_logic22_and0 | u_cla24_or50;
|
|
assign u_cla24_pg_logic23_or0 = a[23] | b[23];
|
|
assign u_cla24_pg_logic23_and0 = a[23] & b[23];
|
|
assign u_cla24_pg_logic23_xor0 = a[23] ^ b[23];
|
|
assign u_cla24_xor23 = u_cla24_pg_logic23_xor0 ^ u_cla24_or51;
|
|
assign u_cla24_and102 = u_cla24_or45 & u_cla24_pg_logic22_or0;
|
|
assign u_cla24_and103 = u_cla24_pg_logic23_or0 & u_cla24_pg_logic21_or0;
|
|
assign u_cla24_and104 = u_cla24_and102 & u_cla24_and103;
|
|
assign u_cla24_and105 = u_cla24_and104 & u_cla24_pg_logic20_or0;
|
|
assign u_cla24_and106 = u_cla24_pg_logic20_and0 & u_cla24_pg_logic22_or0;
|
|
assign u_cla24_and107 = u_cla24_pg_logic23_or0 & u_cla24_pg_logic21_or0;
|
|
assign u_cla24_and108 = u_cla24_and106 & u_cla24_and107;
|
|
assign u_cla24_and109 = u_cla24_pg_logic21_and0 & u_cla24_pg_logic23_or0;
|
|
assign u_cla24_and110 = u_cla24_and109 & u_cla24_pg_logic22_or0;
|
|
assign u_cla24_and111 = u_cla24_pg_logic22_and0 & u_cla24_pg_logic23_or0;
|
|
assign u_cla24_or52 = u_cla24_and105 | u_cla24_and110;
|
|
assign u_cla24_or53 = u_cla24_and108 | u_cla24_and111;
|
|
assign u_cla24_or54 = u_cla24_or52 | u_cla24_or53;
|
|
assign u_cla24_or55 = u_cla24_pg_logic23_and0 | u_cla24_or54;
|
|
|
|
assign u_cla24_out[0] = u_cla24_pg_logic0_xor0;
|
|
assign u_cla24_out[1] = u_cla24_xor1;
|
|
assign u_cla24_out[2] = u_cla24_xor2;
|
|
assign u_cla24_out[3] = u_cla24_xor3;
|
|
assign u_cla24_out[4] = u_cla24_xor4;
|
|
assign u_cla24_out[5] = u_cla24_xor5;
|
|
assign u_cla24_out[6] = u_cla24_xor6;
|
|
assign u_cla24_out[7] = u_cla24_xor7;
|
|
assign u_cla24_out[8] = u_cla24_xor8;
|
|
assign u_cla24_out[9] = u_cla24_xor9;
|
|
assign u_cla24_out[10] = u_cla24_xor10;
|
|
assign u_cla24_out[11] = u_cla24_xor11;
|
|
assign u_cla24_out[12] = u_cla24_xor12;
|
|
assign u_cla24_out[13] = u_cla24_xor13;
|
|
assign u_cla24_out[14] = u_cla24_xor14;
|
|
assign u_cla24_out[15] = u_cla24_xor15;
|
|
assign u_cla24_out[16] = u_cla24_xor16;
|
|
assign u_cla24_out[17] = u_cla24_xor17;
|
|
assign u_cla24_out[18] = u_cla24_xor18;
|
|
assign u_cla24_out[19] = u_cla24_xor19;
|
|
assign u_cla24_out[20] = u_cla24_xor20;
|
|
assign u_cla24_out[21] = u_cla24_xor21;
|
|
assign u_cla24_out[22] = u_cla24_xor22;
|
|
assign u_cla24_out[23] = u_cla24_xor23;
|
|
assign u_cla24_out[24] = u_cla24_or55;
|
|
endmodule |