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https://github.com/ehw-fit/ariths-gen.git
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56c86c13ca
* #10 CGP Circuits as inputs (#11) * CGP Circuits as inputs * #10 support of signed output in general circuit * input as output works * output connected to input (c) * automated verilog testing * output rename * Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. * Typos fix and code cleanup. * Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. * Updated automated testing scripts. * Small bugfix in python code generation (I initially thought this line is useless). * Updated generated circuits folder. Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
267 lines
11 KiB
Verilog
267 lines
11 KiB
Verilog
module u_cla12(input [11:0] a, input [11:0] b, output [12:0] u_cla12_out);
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wire u_cla12_pg_logic0_or0;
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wire u_cla12_pg_logic0_and0;
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wire u_cla12_pg_logic0_xor0;
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wire u_cla12_pg_logic1_or0;
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wire u_cla12_pg_logic1_and0;
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wire u_cla12_pg_logic1_xor0;
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wire u_cla12_xor1;
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wire u_cla12_and0;
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wire u_cla12_or0;
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wire u_cla12_pg_logic2_or0;
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wire u_cla12_pg_logic2_and0;
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wire u_cla12_pg_logic2_xor0;
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wire u_cla12_xor2;
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wire u_cla12_and1;
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wire u_cla12_and2;
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wire u_cla12_and3;
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wire u_cla12_and4;
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wire u_cla12_or1;
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wire u_cla12_or2;
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wire u_cla12_pg_logic3_or0;
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wire u_cla12_pg_logic3_and0;
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wire u_cla12_pg_logic3_xor0;
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wire u_cla12_xor3;
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wire u_cla12_and5;
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wire u_cla12_and6;
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wire u_cla12_and7;
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wire u_cla12_and8;
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wire u_cla12_and9;
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wire u_cla12_and10;
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wire u_cla12_and11;
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wire u_cla12_or3;
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wire u_cla12_or4;
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wire u_cla12_or5;
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wire u_cla12_pg_logic4_or0;
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wire u_cla12_pg_logic4_and0;
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wire u_cla12_pg_logic4_xor0;
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wire u_cla12_xor4;
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wire u_cla12_and12;
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wire u_cla12_or6;
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wire u_cla12_pg_logic5_or0;
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wire u_cla12_pg_logic5_and0;
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wire u_cla12_pg_logic5_xor0;
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wire u_cla12_xor5;
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wire u_cla12_and13;
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wire u_cla12_and14;
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wire u_cla12_and15;
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wire u_cla12_or7;
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wire u_cla12_or8;
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wire u_cla12_pg_logic6_or0;
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wire u_cla12_pg_logic6_and0;
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wire u_cla12_pg_logic6_xor0;
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wire u_cla12_xor6;
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wire u_cla12_and16;
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wire u_cla12_and17;
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wire u_cla12_and18;
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wire u_cla12_and19;
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wire u_cla12_and20;
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wire u_cla12_and21;
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wire u_cla12_or9;
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wire u_cla12_or10;
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wire u_cla12_or11;
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wire u_cla12_pg_logic7_or0;
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wire u_cla12_pg_logic7_and0;
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wire u_cla12_pg_logic7_xor0;
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wire u_cla12_xor7;
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wire u_cla12_and22;
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wire u_cla12_and23;
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wire u_cla12_and24;
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wire u_cla12_and25;
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wire u_cla12_and26;
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wire u_cla12_and27;
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wire u_cla12_and28;
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wire u_cla12_and29;
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wire u_cla12_and30;
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wire u_cla12_and31;
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wire u_cla12_or12;
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wire u_cla12_or13;
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wire u_cla12_or14;
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wire u_cla12_or15;
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wire u_cla12_pg_logic8_or0;
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wire u_cla12_pg_logic8_and0;
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wire u_cla12_pg_logic8_xor0;
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wire u_cla12_xor8;
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wire u_cla12_and32;
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wire u_cla12_or16;
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wire u_cla12_pg_logic9_or0;
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wire u_cla12_pg_logic9_and0;
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wire u_cla12_pg_logic9_xor0;
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wire u_cla12_xor9;
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wire u_cla12_and33;
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wire u_cla12_and34;
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wire u_cla12_and35;
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wire u_cla12_or17;
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wire u_cla12_or18;
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wire u_cla12_pg_logic10_or0;
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wire u_cla12_pg_logic10_and0;
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wire u_cla12_pg_logic10_xor0;
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wire u_cla12_xor10;
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wire u_cla12_and36;
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wire u_cla12_and37;
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wire u_cla12_and38;
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wire u_cla12_and39;
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wire u_cla12_and40;
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wire u_cla12_and41;
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wire u_cla12_or19;
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wire u_cla12_or20;
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wire u_cla12_or21;
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wire u_cla12_pg_logic11_or0;
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wire u_cla12_pg_logic11_and0;
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wire u_cla12_pg_logic11_xor0;
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wire u_cla12_xor11;
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wire u_cla12_and42;
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wire u_cla12_and43;
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wire u_cla12_and44;
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wire u_cla12_and45;
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wire u_cla12_and46;
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wire u_cla12_and47;
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wire u_cla12_and48;
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wire u_cla12_and49;
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wire u_cla12_and50;
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wire u_cla12_and51;
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wire u_cla12_or22;
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wire u_cla12_or23;
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wire u_cla12_or24;
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wire u_cla12_or25;
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assign u_cla12_pg_logic0_or0 = a[0] | b[0];
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assign u_cla12_pg_logic0_and0 = a[0] & b[0];
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assign u_cla12_pg_logic0_xor0 = a[0] ^ b[0];
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assign u_cla12_pg_logic1_or0 = a[1] | b[1];
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assign u_cla12_pg_logic1_and0 = a[1] & b[1];
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assign u_cla12_pg_logic1_xor0 = a[1] ^ b[1];
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assign u_cla12_xor1 = u_cla12_pg_logic1_xor0 ^ u_cla12_pg_logic0_and0;
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assign u_cla12_and0 = u_cla12_pg_logic0_and0 & u_cla12_pg_logic1_or0;
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assign u_cla12_or0 = u_cla12_pg_logic1_and0 | u_cla12_and0;
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assign u_cla12_pg_logic2_or0 = a[2] | b[2];
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assign u_cla12_pg_logic2_and0 = a[2] & b[2];
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assign u_cla12_pg_logic2_xor0 = a[2] ^ b[2];
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assign u_cla12_xor2 = u_cla12_pg_logic2_xor0 ^ u_cla12_or0;
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assign u_cla12_and1 = u_cla12_pg_logic2_or0 & u_cla12_pg_logic0_or0;
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assign u_cla12_and2 = u_cla12_pg_logic0_and0 & u_cla12_pg_logic2_or0;
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assign u_cla12_and3 = u_cla12_and2 & u_cla12_pg_logic1_or0;
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assign u_cla12_and4 = u_cla12_pg_logic1_and0 & u_cla12_pg_logic2_or0;
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assign u_cla12_or1 = u_cla12_and3 | u_cla12_and4;
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assign u_cla12_or2 = u_cla12_pg_logic2_and0 | u_cla12_or1;
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assign u_cla12_pg_logic3_or0 = a[3] | b[3];
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assign u_cla12_pg_logic3_and0 = a[3] & b[3];
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assign u_cla12_pg_logic3_xor0 = a[3] ^ b[3];
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assign u_cla12_xor3 = u_cla12_pg_logic3_xor0 ^ u_cla12_or2;
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assign u_cla12_and5 = u_cla12_pg_logic3_or0 & u_cla12_pg_logic1_or0;
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assign u_cla12_and6 = u_cla12_pg_logic0_and0 & u_cla12_pg_logic2_or0;
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assign u_cla12_and7 = u_cla12_pg_logic3_or0 & u_cla12_pg_logic1_or0;
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assign u_cla12_and8 = u_cla12_and6 & u_cla12_and7;
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assign u_cla12_and9 = u_cla12_pg_logic1_and0 & u_cla12_pg_logic3_or0;
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assign u_cla12_and10 = u_cla12_and9 & u_cla12_pg_logic2_or0;
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assign u_cla12_and11 = u_cla12_pg_logic2_and0 & u_cla12_pg_logic3_or0;
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assign u_cla12_or3 = u_cla12_and8 | u_cla12_and11;
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assign u_cla12_or4 = u_cla12_and10 | u_cla12_or3;
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assign u_cla12_or5 = u_cla12_pg_logic3_and0 | u_cla12_or4;
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assign u_cla12_pg_logic4_or0 = a[4] | b[4];
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assign u_cla12_pg_logic4_and0 = a[4] & b[4];
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assign u_cla12_pg_logic4_xor0 = a[4] ^ b[4];
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assign u_cla12_xor4 = u_cla12_pg_logic4_xor0 ^ u_cla12_or5;
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assign u_cla12_and12 = u_cla12_or5 & u_cla12_pg_logic4_or0;
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assign u_cla12_or6 = u_cla12_pg_logic4_and0 | u_cla12_and12;
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assign u_cla12_pg_logic5_or0 = a[5] | b[5];
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assign u_cla12_pg_logic5_and0 = a[5] & b[5];
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assign u_cla12_pg_logic5_xor0 = a[5] ^ b[5];
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assign u_cla12_xor5 = u_cla12_pg_logic5_xor0 ^ u_cla12_or6;
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assign u_cla12_and13 = u_cla12_or5 & u_cla12_pg_logic5_or0;
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assign u_cla12_and14 = u_cla12_and13 & u_cla12_pg_logic4_or0;
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assign u_cla12_and15 = u_cla12_pg_logic4_and0 & u_cla12_pg_logic5_or0;
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assign u_cla12_or7 = u_cla12_and14 | u_cla12_and15;
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assign u_cla12_or8 = u_cla12_pg_logic5_and0 | u_cla12_or7;
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assign u_cla12_pg_logic6_or0 = a[6] | b[6];
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assign u_cla12_pg_logic6_and0 = a[6] & b[6];
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assign u_cla12_pg_logic6_xor0 = a[6] ^ b[6];
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assign u_cla12_xor6 = u_cla12_pg_logic6_xor0 ^ u_cla12_or8;
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assign u_cla12_and16 = u_cla12_or5 & u_cla12_pg_logic5_or0;
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assign u_cla12_and17 = u_cla12_pg_logic6_or0 & u_cla12_pg_logic4_or0;
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assign u_cla12_and18 = u_cla12_and16 & u_cla12_and17;
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assign u_cla12_and19 = u_cla12_pg_logic4_and0 & u_cla12_pg_logic6_or0;
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assign u_cla12_and20 = u_cla12_and19 & u_cla12_pg_logic5_or0;
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assign u_cla12_and21 = u_cla12_pg_logic5_and0 & u_cla12_pg_logic6_or0;
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assign u_cla12_or9 = u_cla12_and18 | u_cla12_and20;
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assign u_cla12_or10 = u_cla12_or9 | u_cla12_and21;
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assign u_cla12_or11 = u_cla12_pg_logic6_and0 | u_cla12_or10;
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assign u_cla12_pg_logic7_or0 = a[7] | b[7];
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assign u_cla12_pg_logic7_and0 = a[7] & b[7];
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assign u_cla12_pg_logic7_xor0 = a[7] ^ b[7];
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assign u_cla12_xor7 = u_cla12_pg_logic7_xor0 ^ u_cla12_or11;
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assign u_cla12_and22 = u_cla12_or5 & u_cla12_pg_logic6_or0;
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assign u_cla12_and23 = u_cla12_pg_logic7_or0 & u_cla12_pg_logic5_or0;
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assign u_cla12_and24 = u_cla12_and22 & u_cla12_and23;
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assign u_cla12_and25 = u_cla12_and24 & u_cla12_pg_logic4_or0;
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assign u_cla12_and26 = u_cla12_pg_logic4_and0 & u_cla12_pg_logic6_or0;
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assign u_cla12_and27 = u_cla12_pg_logic7_or0 & u_cla12_pg_logic5_or0;
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assign u_cla12_and28 = u_cla12_and26 & u_cla12_and27;
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assign u_cla12_and29 = u_cla12_pg_logic5_and0 & u_cla12_pg_logic7_or0;
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assign u_cla12_and30 = u_cla12_and29 & u_cla12_pg_logic6_or0;
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assign u_cla12_and31 = u_cla12_pg_logic6_and0 & u_cla12_pg_logic7_or0;
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assign u_cla12_or12 = u_cla12_and25 | u_cla12_and30;
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assign u_cla12_or13 = u_cla12_and28 | u_cla12_and31;
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assign u_cla12_or14 = u_cla12_or12 | u_cla12_or13;
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assign u_cla12_or15 = u_cla12_pg_logic7_and0 | u_cla12_or14;
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assign u_cla12_pg_logic8_or0 = a[8] | b[8];
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assign u_cla12_pg_logic8_and0 = a[8] & b[8];
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assign u_cla12_pg_logic8_xor0 = a[8] ^ b[8];
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assign u_cla12_xor8 = u_cla12_pg_logic8_xor0 ^ u_cla12_or15;
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assign u_cla12_and32 = u_cla12_or15 & u_cla12_pg_logic8_or0;
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assign u_cla12_or16 = u_cla12_pg_logic8_and0 | u_cla12_and32;
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assign u_cla12_pg_logic9_or0 = a[9] | b[9];
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assign u_cla12_pg_logic9_and0 = a[9] & b[9];
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assign u_cla12_pg_logic9_xor0 = a[9] ^ b[9];
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assign u_cla12_xor9 = u_cla12_pg_logic9_xor0 ^ u_cla12_or16;
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assign u_cla12_and33 = u_cla12_or15 & u_cla12_pg_logic9_or0;
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assign u_cla12_and34 = u_cla12_and33 & u_cla12_pg_logic8_or0;
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assign u_cla12_and35 = u_cla12_pg_logic8_and0 & u_cla12_pg_logic9_or0;
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assign u_cla12_or17 = u_cla12_and34 | u_cla12_and35;
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assign u_cla12_or18 = u_cla12_pg_logic9_and0 | u_cla12_or17;
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assign u_cla12_pg_logic10_or0 = a[10] | b[10];
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assign u_cla12_pg_logic10_and0 = a[10] & b[10];
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assign u_cla12_pg_logic10_xor0 = a[10] ^ b[10];
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assign u_cla12_xor10 = u_cla12_pg_logic10_xor0 ^ u_cla12_or18;
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assign u_cla12_and36 = u_cla12_or15 & u_cla12_pg_logic9_or0;
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assign u_cla12_and37 = u_cla12_pg_logic10_or0 & u_cla12_pg_logic8_or0;
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assign u_cla12_and38 = u_cla12_and36 & u_cla12_and37;
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assign u_cla12_and39 = u_cla12_pg_logic8_and0 & u_cla12_pg_logic10_or0;
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assign u_cla12_and40 = u_cla12_and39 & u_cla12_pg_logic9_or0;
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assign u_cla12_and41 = u_cla12_pg_logic9_and0 & u_cla12_pg_logic10_or0;
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assign u_cla12_or19 = u_cla12_and38 | u_cla12_and40;
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assign u_cla12_or20 = u_cla12_or19 | u_cla12_and41;
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assign u_cla12_or21 = u_cla12_pg_logic10_and0 | u_cla12_or20;
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assign u_cla12_pg_logic11_or0 = a[11] | b[11];
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assign u_cla12_pg_logic11_and0 = a[11] & b[11];
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assign u_cla12_pg_logic11_xor0 = a[11] ^ b[11];
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assign u_cla12_xor11 = u_cla12_pg_logic11_xor0 ^ u_cla12_or21;
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assign u_cla12_and42 = u_cla12_or15 & u_cla12_pg_logic10_or0;
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assign u_cla12_and43 = u_cla12_pg_logic11_or0 & u_cla12_pg_logic9_or0;
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assign u_cla12_and44 = u_cla12_and42 & u_cla12_and43;
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assign u_cla12_and45 = u_cla12_and44 & u_cla12_pg_logic8_or0;
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assign u_cla12_and46 = u_cla12_pg_logic8_and0 & u_cla12_pg_logic10_or0;
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assign u_cla12_and47 = u_cla12_pg_logic11_or0 & u_cla12_pg_logic9_or0;
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assign u_cla12_and48 = u_cla12_and46 & u_cla12_and47;
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assign u_cla12_and49 = u_cla12_pg_logic9_and0 & u_cla12_pg_logic11_or0;
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assign u_cla12_and50 = u_cla12_and49 & u_cla12_pg_logic10_or0;
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assign u_cla12_and51 = u_cla12_pg_logic10_and0 & u_cla12_pg_logic11_or0;
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assign u_cla12_or22 = u_cla12_and45 | u_cla12_and50;
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assign u_cla12_or23 = u_cla12_and48 | u_cla12_and51;
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assign u_cla12_or24 = u_cla12_or22 | u_cla12_or23;
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assign u_cla12_or25 = u_cla12_pg_logic11_and0 | u_cla12_or24;
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assign u_cla12_out[0] = u_cla12_pg_logic0_xor0;
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assign u_cla12_out[1] = u_cla12_xor1;
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assign u_cla12_out[2] = u_cla12_xor2;
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assign u_cla12_out[3] = u_cla12_xor3;
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assign u_cla12_out[4] = u_cla12_xor4;
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assign u_cla12_out[5] = u_cla12_xor5;
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assign u_cla12_out[6] = u_cla12_xor6;
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assign u_cla12_out[7] = u_cla12_xor7;
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assign u_cla12_out[8] = u_cla12_xor8;
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assign u_cla12_out[9] = u_cla12_xor9;
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assign u_cla12_out[10] = u_cla12_xor10;
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assign u_cla12_out[11] = u_cla12_xor11;
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assign u_cla12_out[12] = u_cla12_or25;
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endmodule |