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https://github.com/ehw-fit/ariths-gen.git
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56c86c13ca
* #10 CGP Circuits as inputs (#11) * CGP Circuits as inputs * #10 support of signed output in general circuit * input as output works * output connected to input (c) * automated verilog testing * output rename * Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. * Typos fix and code cleanup. * Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. * Updated automated testing scripts. * Small bugfix in python code generation (I initially thought this line is useless). * Updated generated circuits folder. Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
118 lines
5.1 KiB
Plaintext
118 lines
5.1 KiB
Plaintext
.model s_pg_rca12
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.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] a[8] a[9] a[10] a[11] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7] b[8] b[9] b[10] b[11]
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.outputs s_pg_rca12_out[0] s_pg_rca12_out[1] s_pg_rca12_out[2] s_pg_rca12_out[3] s_pg_rca12_out[4] s_pg_rca12_out[5] s_pg_rca12_out[6] s_pg_rca12_out[7] s_pg_rca12_out[8] s_pg_rca12_out[9] s_pg_rca12_out[10] s_pg_rca12_out[11] s_pg_rca12_out[12]
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.names vdd
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1
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.names gnd
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0
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.subckt pg_fa a=a[0] b=b[0] cin=gnd pg_fa_xor0=s_pg_rca12_pg_fa0_xor0 pg_fa_and0=s_pg_rca12_pg_fa0_and0
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.subckt pg_fa a=a[1] b=b[1] cin=s_pg_rca12_pg_fa0_and0 pg_fa_xor0=s_pg_rca12_pg_fa1_xor0 pg_fa_and0=s_pg_rca12_pg_fa1_and0 pg_fa_xor1=s_pg_rca12_pg_fa1_xor1
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.subckt and_gate a=s_pg_rca12_pg_fa0_and0 b=s_pg_rca12_pg_fa1_xor0 out=s_pg_rca12_and1
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.subckt or_gate a=s_pg_rca12_and1 b=s_pg_rca12_pg_fa1_and0 out=s_pg_rca12_or1
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.subckt pg_fa a=a[2] b=b[2] cin=s_pg_rca12_or1 pg_fa_xor0=s_pg_rca12_pg_fa2_xor0 pg_fa_and0=s_pg_rca12_pg_fa2_and0 pg_fa_xor1=s_pg_rca12_pg_fa2_xor1
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.subckt and_gate a=s_pg_rca12_or1 b=s_pg_rca12_pg_fa2_xor0 out=s_pg_rca12_and2
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.subckt or_gate a=s_pg_rca12_and2 b=s_pg_rca12_pg_fa2_and0 out=s_pg_rca12_or2
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.subckt pg_fa a=a[3] b=b[3] cin=s_pg_rca12_or2 pg_fa_xor0=s_pg_rca12_pg_fa3_xor0 pg_fa_and0=s_pg_rca12_pg_fa3_and0 pg_fa_xor1=s_pg_rca12_pg_fa3_xor1
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.subckt and_gate a=s_pg_rca12_or2 b=s_pg_rca12_pg_fa3_xor0 out=s_pg_rca12_and3
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.subckt or_gate a=s_pg_rca12_and3 b=s_pg_rca12_pg_fa3_and0 out=s_pg_rca12_or3
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.subckt pg_fa a=a[4] b=b[4] cin=s_pg_rca12_or3 pg_fa_xor0=s_pg_rca12_pg_fa4_xor0 pg_fa_and0=s_pg_rca12_pg_fa4_and0 pg_fa_xor1=s_pg_rca12_pg_fa4_xor1
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.subckt and_gate a=s_pg_rca12_or3 b=s_pg_rca12_pg_fa4_xor0 out=s_pg_rca12_and4
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.subckt or_gate a=s_pg_rca12_and4 b=s_pg_rca12_pg_fa4_and0 out=s_pg_rca12_or4
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.subckt pg_fa a=a[5] b=b[5] cin=s_pg_rca12_or4 pg_fa_xor0=s_pg_rca12_pg_fa5_xor0 pg_fa_and0=s_pg_rca12_pg_fa5_and0 pg_fa_xor1=s_pg_rca12_pg_fa5_xor1
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.subckt and_gate a=s_pg_rca12_or4 b=s_pg_rca12_pg_fa5_xor0 out=s_pg_rca12_and5
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.subckt or_gate a=s_pg_rca12_and5 b=s_pg_rca12_pg_fa5_and0 out=s_pg_rca12_or5
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.subckt pg_fa a=a[6] b=b[6] cin=s_pg_rca12_or5 pg_fa_xor0=s_pg_rca12_pg_fa6_xor0 pg_fa_and0=s_pg_rca12_pg_fa6_and0 pg_fa_xor1=s_pg_rca12_pg_fa6_xor1
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.subckt and_gate a=s_pg_rca12_or5 b=s_pg_rca12_pg_fa6_xor0 out=s_pg_rca12_and6
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.subckt or_gate a=s_pg_rca12_and6 b=s_pg_rca12_pg_fa6_and0 out=s_pg_rca12_or6
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.subckt pg_fa a=a[7] b=b[7] cin=s_pg_rca12_or6 pg_fa_xor0=s_pg_rca12_pg_fa7_xor0 pg_fa_and0=s_pg_rca12_pg_fa7_and0 pg_fa_xor1=s_pg_rca12_pg_fa7_xor1
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.subckt and_gate a=s_pg_rca12_or6 b=s_pg_rca12_pg_fa7_xor0 out=s_pg_rca12_and7
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.subckt or_gate a=s_pg_rca12_and7 b=s_pg_rca12_pg_fa7_and0 out=s_pg_rca12_or7
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.subckt pg_fa a=a[8] b=b[8] cin=s_pg_rca12_or7 pg_fa_xor0=s_pg_rca12_pg_fa8_xor0 pg_fa_and0=s_pg_rca12_pg_fa8_and0 pg_fa_xor1=s_pg_rca12_pg_fa8_xor1
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.subckt and_gate a=s_pg_rca12_or7 b=s_pg_rca12_pg_fa8_xor0 out=s_pg_rca12_and8
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.subckt or_gate a=s_pg_rca12_and8 b=s_pg_rca12_pg_fa8_and0 out=s_pg_rca12_or8
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.subckt pg_fa a=a[9] b=b[9] cin=s_pg_rca12_or8 pg_fa_xor0=s_pg_rca12_pg_fa9_xor0 pg_fa_and0=s_pg_rca12_pg_fa9_and0 pg_fa_xor1=s_pg_rca12_pg_fa9_xor1
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.subckt and_gate a=s_pg_rca12_or8 b=s_pg_rca12_pg_fa9_xor0 out=s_pg_rca12_and9
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.subckt or_gate a=s_pg_rca12_and9 b=s_pg_rca12_pg_fa9_and0 out=s_pg_rca12_or9
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.subckt pg_fa a=a[10] b=b[10] cin=s_pg_rca12_or9 pg_fa_xor0=s_pg_rca12_pg_fa10_xor0 pg_fa_and0=s_pg_rca12_pg_fa10_and0 pg_fa_xor1=s_pg_rca12_pg_fa10_xor1
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.subckt and_gate a=s_pg_rca12_or9 b=s_pg_rca12_pg_fa10_xor0 out=s_pg_rca12_and10
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.subckt or_gate a=s_pg_rca12_and10 b=s_pg_rca12_pg_fa10_and0 out=s_pg_rca12_or10
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.subckt pg_fa a=a[11] b=b[11] cin=s_pg_rca12_or10 pg_fa_xor0=s_pg_rca12_pg_fa11_xor0 pg_fa_and0=s_pg_rca12_pg_fa11_and0 pg_fa_xor1=s_pg_rca12_pg_fa11_xor1
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.subckt and_gate a=s_pg_rca12_or10 b=s_pg_rca12_pg_fa11_xor0 out=s_pg_rca12_and11
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.subckt or_gate a=s_pg_rca12_and11 b=s_pg_rca12_pg_fa11_and0 out=s_pg_rca12_or11
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.subckt xor_gate a=a[11] b=b[11] out=s_pg_rca12_xor0
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.subckt xor_gate a=s_pg_rca12_xor0 b=s_pg_rca12_or11 out=s_pg_rca12_xor1
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.names s_pg_rca12_pg_fa0_xor0 s_pg_rca12_out[0]
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1 1
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.names s_pg_rca12_pg_fa1_xor1 s_pg_rca12_out[1]
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1 1
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.names s_pg_rca12_pg_fa2_xor1 s_pg_rca12_out[2]
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1 1
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.names s_pg_rca12_pg_fa3_xor1 s_pg_rca12_out[3]
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1 1
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.names s_pg_rca12_pg_fa4_xor1 s_pg_rca12_out[4]
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1 1
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.names s_pg_rca12_pg_fa5_xor1 s_pg_rca12_out[5]
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1 1
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.names s_pg_rca12_pg_fa6_xor1 s_pg_rca12_out[6]
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1 1
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.names s_pg_rca12_pg_fa7_xor1 s_pg_rca12_out[7]
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1 1
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.names s_pg_rca12_pg_fa8_xor1 s_pg_rca12_out[8]
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1 1
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.names s_pg_rca12_pg_fa9_xor1 s_pg_rca12_out[9]
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1 1
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.names s_pg_rca12_pg_fa10_xor1 s_pg_rca12_out[10]
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1 1
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.names s_pg_rca12_pg_fa11_xor1 s_pg_rca12_out[11]
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1 1
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.names s_pg_rca12_xor1 s_pg_rca12_out[12]
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1 1
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.end
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.model pg_fa
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.inputs a b cin
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.outputs pg_fa_xor0 pg_fa_and0 pg_fa_xor1
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.names vdd
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1
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.names gnd
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0
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.subckt xor_gate a=a b=b out=pg_fa_xor0
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.subckt and_gate a=a b=b out=pg_fa_and0
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.subckt xor_gate a=pg_fa_xor0 b=cin out=pg_fa_xor1
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.end
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.model or_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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1- 1
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-1 1
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.end
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.model and_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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11 1
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.end
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.model xor_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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01 1
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10 1
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.end
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