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56c86c13ca
* #10 CGP Circuits as inputs (#11) * CGP Circuits as inputs * #10 support of signed output in general circuit * input as output works * output connected to input (c) * automated verilog testing * output rename * Implemented CSA and Wallace tree multiplier composing of CSAs. Also did some code cleanup. * Typos fix and code cleanup. * Added new (approximate) multiplier architectures and did some minor changes regarding sign extension for c output formats. * Updated automated testing scripts. * Small bugfix in python code generation (I initially thought this line is useless). * Updated generated circuits folder. Co-authored-by: Vojta Mrazek <mrazek@fit.vutbr.cz>
139 lines
6.1 KiB
Plaintext
139 lines
6.1 KiB
Plaintext
.model s_cla8
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.inputs a[0] a[1] a[2] a[3] a[4] a[5] a[6] a[7] b[0] b[1] b[2] b[3] b[4] b[5] b[6] b[7]
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.outputs s_cla8_out[0] s_cla8_out[1] s_cla8_out[2] s_cla8_out[3] s_cla8_out[4] s_cla8_out[5] s_cla8_out[6] s_cla8_out[7] s_cla8_out[8]
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.names vdd
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1
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.names gnd
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0
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.subckt pg_logic a=a[0] b=b[0] pg_logic_or0=s_cla8_pg_logic0_or0 pg_logic_and0=s_cla8_pg_logic0_and0 pg_logic_xor0=s_cla8_pg_logic0_xor0
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.subckt pg_logic a=a[1] b=b[1] pg_logic_or0=s_cla8_pg_logic1_or0 pg_logic_and0=s_cla8_pg_logic1_and0 pg_logic_xor0=s_cla8_pg_logic1_xor0
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.subckt xor_gate a=s_cla8_pg_logic1_xor0 b=s_cla8_pg_logic0_and0 out=s_cla8_xor1
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.subckt and_gate a=s_cla8_pg_logic0_and0 b=s_cla8_pg_logic1_or0 out=s_cla8_and0
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.subckt or_gate a=s_cla8_pg_logic1_and0 b=s_cla8_and0 out=s_cla8_or0
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.subckt pg_logic a=a[2] b=b[2] pg_logic_or0=s_cla8_pg_logic2_or0 pg_logic_and0=s_cla8_pg_logic2_and0 pg_logic_xor0=s_cla8_pg_logic2_xor0
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.subckt xor_gate a=s_cla8_pg_logic2_xor0 b=s_cla8_or0 out=s_cla8_xor2
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.subckt and_gate a=s_cla8_pg_logic2_or0 b=s_cla8_pg_logic0_or0 out=s_cla8_and1
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.subckt and_gate a=s_cla8_pg_logic0_and0 b=s_cla8_pg_logic2_or0 out=s_cla8_and2
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.subckt and_gate a=s_cla8_and2 b=s_cla8_pg_logic1_or0 out=s_cla8_and3
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.subckt and_gate a=s_cla8_pg_logic1_and0 b=s_cla8_pg_logic2_or0 out=s_cla8_and4
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.subckt or_gate a=s_cla8_and3 b=s_cla8_and4 out=s_cla8_or1
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.subckt or_gate a=s_cla8_pg_logic2_and0 b=s_cla8_or1 out=s_cla8_or2
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.subckt pg_logic a=a[3] b=b[3] pg_logic_or0=s_cla8_pg_logic3_or0 pg_logic_and0=s_cla8_pg_logic3_and0 pg_logic_xor0=s_cla8_pg_logic3_xor0
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.subckt xor_gate a=s_cla8_pg_logic3_xor0 b=s_cla8_or2 out=s_cla8_xor3
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.subckt and_gate a=s_cla8_pg_logic3_or0 b=s_cla8_pg_logic1_or0 out=s_cla8_and5
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.subckt and_gate a=s_cla8_pg_logic0_and0 b=s_cla8_pg_logic2_or0 out=s_cla8_and6
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.subckt and_gate a=s_cla8_pg_logic3_or0 b=s_cla8_pg_logic1_or0 out=s_cla8_and7
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.subckt and_gate a=s_cla8_and6 b=s_cla8_and7 out=s_cla8_and8
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.subckt and_gate a=s_cla8_pg_logic1_and0 b=s_cla8_pg_logic3_or0 out=s_cla8_and9
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.subckt and_gate a=s_cla8_and9 b=s_cla8_pg_logic2_or0 out=s_cla8_and10
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.subckt and_gate a=s_cla8_pg_logic2_and0 b=s_cla8_pg_logic3_or0 out=s_cla8_and11
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.subckt or_gate a=s_cla8_and8 b=s_cla8_and11 out=s_cla8_or3
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.subckt or_gate a=s_cla8_and10 b=s_cla8_or3 out=s_cla8_or4
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.subckt or_gate a=s_cla8_pg_logic3_and0 b=s_cla8_or4 out=s_cla8_or5
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.subckt pg_logic a=a[4] b=b[4] pg_logic_or0=s_cla8_pg_logic4_or0 pg_logic_and0=s_cla8_pg_logic4_and0 pg_logic_xor0=s_cla8_pg_logic4_xor0
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.subckt xor_gate a=s_cla8_pg_logic4_xor0 b=s_cla8_or5 out=s_cla8_xor4
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.subckt and_gate a=s_cla8_or5 b=s_cla8_pg_logic4_or0 out=s_cla8_and12
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.subckt or_gate a=s_cla8_pg_logic4_and0 b=s_cla8_and12 out=s_cla8_or6
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.subckt pg_logic a=a[5] b=b[5] pg_logic_or0=s_cla8_pg_logic5_or0 pg_logic_and0=s_cla8_pg_logic5_and0 pg_logic_xor0=s_cla8_pg_logic5_xor0
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.subckt xor_gate a=s_cla8_pg_logic5_xor0 b=s_cla8_or6 out=s_cla8_xor5
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.subckt and_gate a=s_cla8_or5 b=s_cla8_pg_logic5_or0 out=s_cla8_and13
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.subckt and_gate a=s_cla8_and13 b=s_cla8_pg_logic4_or0 out=s_cla8_and14
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.subckt and_gate a=s_cla8_pg_logic4_and0 b=s_cla8_pg_logic5_or0 out=s_cla8_and15
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.subckt or_gate a=s_cla8_and14 b=s_cla8_and15 out=s_cla8_or7
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.subckt or_gate a=s_cla8_pg_logic5_and0 b=s_cla8_or7 out=s_cla8_or8
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.subckt pg_logic a=a[6] b=b[6] pg_logic_or0=s_cla8_pg_logic6_or0 pg_logic_and0=s_cla8_pg_logic6_and0 pg_logic_xor0=s_cla8_pg_logic6_xor0
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.subckt xor_gate a=s_cla8_pg_logic6_xor0 b=s_cla8_or8 out=s_cla8_xor6
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.subckt and_gate a=s_cla8_or5 b=s_cla8_pg_logic5_or0 out=s_cla8_and16
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.subckt and_gate a=s_cla8_pg_logic6_or0 b=s_cla8_pg_logic4_or0 out=s_cla8_and17
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.subckt and_gate a=s_cla8_and16 b=s_cla8_and17 out=s_cla8_and18
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.subckt and_gate a=s_cla8_pg_logic4_and0 b=s_cla8_pg_logic6_or0 out=s_cla8_and19
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.subckt and_gate a=s_cla8_and19 b=s_cla8_pg_logic5_or0 out=s_cla8_and20
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.subckt and_gate a=s_cla8_pg_logic5_and0 b=s_cla8_pg_logic6_or0 out=s_cla8_and21
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.subckt or_gate a=s_cla8_and18 b=s_cla8_and20 out=s_cla8_or9
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.subckt or_gate a=s_cla8_or9 b=s_cla8_and21 out=s_cla8_or10
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.subckt or_gate a=s_cla8_pg_logic6_and0 b=s_cla8_or10 out=s_cla8_or11
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.subckt pg_logic a=a[7] b=b[7] pg_logic_or0=s_cla8_pg_logic7_or0 pg_logic_and0=s_cla8_pg_logic7_and0 pg_logic_xor0=s_cla8_pg_logic7_xor0
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.subckt xor_gate a=s_cla8_pg_logic7_xor0 b=s_cla8_or11 out=s_cla8_xor7
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.subckt and_gate a=s_cla8_or5 b=s_cla8_pg_logic6_or0 out=s_cla8_and22
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.subckt and_gate a=s_cla8_pg_logic7_or0 b=s_cla8_pg_logic5_or0 out=s_cla8_and23
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.subckt and_gate a=s_cla8_and22 b=s_cla8_and23 out=s_cla8_and24
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.subckt and_gate a=s_cla8_and24 b=s_cla8_pg_logic4_or0 out=s_cla8_and25
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.subckt and_gate a=s_cla8_pg_logic4_and0 b=s_cla8_pg_logic6_or0 out=s_cla8_and26
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.subckt and_gate a=s_cla8_pg_logic7_or0 b=s_cla8_pg_logic5_or0 out=s_cla8_and27
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.subckt and_gate a=s_cla8_and26 b=s_cla8_and27 out=s_cla8_and28
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.subckt and_gate a=s_cla8_pg_logic5_and0 b=s_cla8_pg_logic7_or0 out=s_cla8_and29
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.subckt and_gate a=s_cla8_and29 b=s_cla8_pg_logic6_or0 out=s_cla8_and30
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.subckt and_gate a=s_cla8_pg_logic6_and0 b=s_cla8_pg_logic7_or0 out=s_cla8_and31
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.subckt or_gate a=s_cla8_and25 b=s_cla8_and30 out=s_cla8_or12
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.subckt or_gate a=s_cla8_and28 b=s_cla8_and31 out=s_cla8_or13
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.subckt or_gate a=s_cla8_or12 b=s_cla8_or13 out=s_cla8_or14
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.subckt or_gate a=s_cla8_pg_logic7_and0 b=s_cla8_or14 out=s_cla8_or15
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.subckt xor_gate a=a[7] b=b[7] out=s_cla8_xor8
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.subckt xor_gate a=s_cla8_xor8 b=s_cla8_or15 out=s_cla8_xor9
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.names s_cla8_pg_logic0_xor0 s_cla8_out[0]
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1 1
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.names s_cla8_xor1 s_cla8_out[1]
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1 1
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.names s_cla8_xor2 s_cla8_out[2]
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1 1
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.names s_cla8_xor3 s_cla8_out[3]
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1 1
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.names s_cla8_xor4 s_cla8_out[4]
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1 1
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.names s_cla8_xor5 s_cla8_out[5]
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1 1
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.names s_cla8_xor6 s_cla8_out[6]
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1 1
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.names s_cla8_xor7 s_cla8_out[7]
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1 1
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.names s_cla8_xor9 s_cla8_out[8]
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1 1
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.end
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.model pg_logic
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.inputs a b
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.outputs pg_logic_or0 pg_logic_and0 pg_logic_xor0
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.names vdd
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1
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.names gnd
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0
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.subckt or_gate a=a b=b out=pg_logic_or0
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.subckt and_gate a=a b=b out=pg_logic_and0
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.subckt xor_gate a=a b=b out=pg_logic_xor0
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.end
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.model xor_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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01 1
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10 1
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.end
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.model and_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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11 1
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.end
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.model or_gate
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.inputs a b
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.outputs out
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.names vdd
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1
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.names gnd
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0
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.names a b out
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1- 1
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-1 1
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.end
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